JPS62183162A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the process of manufacture as well as to contrive improvement in electric reliability by a method wherein, in a mask ROM, a data line is formed on the MISFET (metal insulation semiconductor field effect transistor) formed with a low impurity density source and drain region through the intermediary of an interlayer insulating film, impurities are introduced into a part of the prescribed source or drain region through the interlayer insulating film, and an information write-in operation is performed. CONSTITUTION:An MISFET Qm is formed with a low impurity density source or drain region 6A, and a wiring (DL and SL) 12 is formed thereon through the intermediary of an interlayer insulating film 9. Then, impurities are introduced into a part 2 of the region 6a. As a writing-in of information can be performed after the wiring 12 forming process, which is the final process of manufacture, by forming the MISFET Qm on which the region 6A is substantially disconnected, the process of manufacture can be achieved. Also, when impurities are introduced into A, they can be introduced with low energy, because they pass through the interlayer insulating film 9 only. Accordingly, the electric reliability of the mask ROM can be enhanced by reducing the fluctuation of threshold voltage of the MISFET Qm caused by a contaminant.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, to a semiconductor integrated circuit bag having a read-only nonvolatile memory function! (hereinafter referred to as mask ROM).

[Conventional technology]

The horizontal mask R○M constitutes a memory cell using an lMISFET. +l OB of the memory cell, 111 +
The information of 1 is written by changing the threshold voltage of the MISFET in the information writing process.

In this type of mask ROM, the information writing process is performed by the following manufacturing process as described in Japanese Patent Laid-Open No. 130963/1983.

First, a MISFET (memory cell) having a first threshold +a lightning voltage is formed. After that, an interlayer insulating film covering the MISFET is formed, and a data line and a source line (aluminum film) connected to the MISFET are formed. Thereafter, a photoresist mask is formed which has an opening above the channel formation region of the MISFET where information is to be written. Then, using this photoresist mask, the interlayer insulating film is removed to expose the gate electrode, and then an impurity (boron or phosphorus) is introduced into the channel forming region through the exposed gate electrode. The purpose of removing the interlayer insulating film is to perform ion implantation with low energy. By introducing this impurity, a MI S FET having a second threshold voltage different from the first threshold voltage is formed, and information is written. Thereafter, a passivation film is formed to complete the manufacturing process of the mask ROM.

In this mask ROM, information can be written after forming the data lines and source lines, which is the final manufacturing process, so the time required to complete the manufacturing process can be shortened (
Hereinafter, it has a characteristic called 1 address reduction.

[Problem that the invention seeks to solve]

As a result of studies on this technology, the present inventor found that the following problems occur.

The impurity for writing information is introduced with the interlayer insulating film removed to expose the gate electrode. For this reason,
Heavy metal contaminants such as Na+ are trapped in the gate insulating film and at the interface between the gate insulating film and the semiconductor substrate, causing damage to the MISFET (
Since the threshold voltage of the memory cell (memory cell) fluctuates, electrical reliability decreases.

Further, since a steep step is formed by removing the interlayer insulating film, the coverage of the data line and source line is reduced.

Furthermore, the impurity is introduced at high energy of about 200 to 300 [KeV] in order to pass through the gate electrode. Therefore, crystal defects occur in the pn junction portions of the channel forming region, source region, and drain region.

What are the crystal defects at the pn junction?

This occurs because the opening in the photoresist film is configured to have a larger dimension than the channel forming region in consideration of mask alignment misalignment. Crystal defects at the pn junction occur over a wide area along the pn junction. These crystal defects can only be heat treated at a low temperature of about 450['C] in order to prevent the data lines made of aluminum film from melting.

Unable to fully recover. Therefore, leakage current increases at the pn junction surface of the source region or drain region. This leakage current causes increased power consumption and latch-up due to parasitic thyristors.

An object of the present invention is to provide a technology that can shorten the length of a mask ROM by 1, reduce fluctuations in threshold voltage of memory cells caused by contaminants, and improve electrical reliability. It is in.

Another object of the present invention is to provide a technique that can reduce leakage current due to crystal defects in a mask ROM, thereby reducing power consumption or preventing latch-up.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the mask ROM, an M I S [7ET (memory cell) is formed in a source region and a drain region with low impurity concentration, and a data line is formed on the M I S FET with an interlayer insulating film interposed therebetween.

Impurities are introduced into a part of the source region or drain region of a predetermined MISFET through the interlayer #a edge film.

Information is written by substantially disconnecting the source region or drain region.

[Effect]

According to the above-mentioned means, information can be stored once after the data lines are formed, so that it is possible to reduce the number of complete times.

Moreover, since it does not pass through the gate electrode of the MI S FET, the impurity can be introduced with low energy.
By eliminating the step of removing the interlayer insulating film, the gate electrode can be prevented from being exposed. In other words, it prevents contaminants from entering,
Since fluctuations in the threshold voltage of the MISFET (memory cell) can be reduced, the electrical reliability of the mask (0M) can be improved.

In addition, by forming the source region or drain region with a low impurity concentration, it is possible to reduce the amount of impurities introduced that actually cause wire breakage, and reduce leakage current due to crystal defects, reducing power consumption and preventing latch-up. This can be prevented.

〔Example〕

Hereinafter, regarding the configuration of the present invention, the present invention will be explained as follows.
Horizontal mask RO with ISFET as a memory cell
This will be explained along with an example applied to M.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

A memory cell array of a horizontal mask ROM which is an embodiment of the present invention is shown in FIG.
Cross section taken along line II and MISF that constitutes the peripheral circuit
A cross section of the ET is shown in FIG. In FIG. 1, insulating films other than the field insulating film provided between each conductive layer are not shown in order to make the structure of this embodiment easier to understand.

In FIG. 1, reference numeral 1 denotes a P-type semiconductor substrate (or well region) made of crystalline silicon. Reference numeral 2 indicates a field insulating film, and reference numeral 3 indicates a p-type channel stopper region, which are configured to electrically separate the semiconductor M.

MISFETQm that constitutes a memory cell and MISFET that constitutes a peripheral circuit (for example, a decoder circuit)
T Q n are respectively provided on the main surface of the semiconductor substrate 1 in a region surrounded by the field insulating film 2 .

M I S F E T Q m is, as shown on the left side of FIGS. 1 and 2, a semiconductor substrate 1, a gate insulating film 4,
The electrode 5 includes an n-type (low impurity concentration) source region and drain region 6A.

MISFETQm to which no information is written is conductive when the word line is at the selection level, and is set to "O" (or ``1'').
Its threshold voltage is set to have information.

The MI SFETQm in which δ information is embedded has an i-type (P-type) in a part of the source region or drain region 6A.

A semiconductor region 13 of an n-type (intrinsic state that is not of any conductivity type) is provided and is substantially disconnected. In other words, an i-type region 13 having extremely high resistance is inserted between a data line DL and a source line SL, which will be described later.

As a result, the data line DL maintains the precharge potential (for example, 3 [V]) of the data line DL even if the memory cell Qm in which information is written is selected. Since the resistance of the i-type conductor region 13 is high, the potential of the source line SL (for example, O[V]) hardly appears on the data line DL, and does not substantially change from the precharge potential during the read period. That is, this MI SFETQm is "i"
<or 'O'') information.Disconnection of the source region and drain region 6A will be described later, but
This is done by introducing an impurity (boron) into a region marked 14 in FIG. 1 and surrounded by a dashed line. In addition, i
There is no problem with the leakage current between the semiconductor region 13 of the mold and the semiconductor substrate 1 because the read period (word line selection time) is short and its value is not very sensitive.

Furthermore, the semiconductor region 13 can be made of p-type by introducing a large amount of impurities. The p-type semiconductor region 13 is configured with an impurity concentration within a range that ensures a junction withstand voltage with the source region or the train region 6A and allows leakage current due to crystal defects caused by introduction of impurities. Since an inversion layer is not formed on the surface of the p-type conductor region 13 compared to the i-type conductor region 13, the source region or drain region 6A can be reliably disconnected.

The gate electrode 5 is made of high melting point metal silicide (MoSi2.Ti5j2.T, ]S on the second part of the polycrystalline silicon film.
It is composed of a composite (polycide) film provided with a 121 W S 12 ) film. Further, the gate electrode 5
may be composed of, for example, a single-layer polycrystalline silicon film, a refractory metal silicide film, a refractory metal (Mo, Ti, Ta, W) film, or a composite film thereof.

The gate electrode 5 connects other MISFETs arranged in the column direction.
It is constructed integrally with the gate pole 5 of Qm, and constitutes a word line (WL) 5A.

M I S FETQ constituting the memory cell of this example
The source region or drain region 6A of MI SFETQm is configured integrally with the source region or train region 6A of the other three adjacent MI SFETQm.

As shown on the right side of FIG. 2, M I 5FETQn is
Semiconductor substrate 1, gate isolation B film 4. Gate electrode 5, n-type (
The semiconductor region 6B includes a semiconductor region 6B (low impurity concentration) and an n1 type (high impurity concentration) source and drain region 8. The semiconductor region 6B is provided between the channel forming region and the source or drain region 8, and the LD
It is used as a D (Lightly Doped Drajn) section and constitutes a MISFETQn having a WLDD structure. The source region and drain region 8 are configured with an impurity introduction mask (sidewall spacer) 7 made of an insulating film provided on the side of the goo 1-electrode 5 to form an LDD structure. .

9 is an interlayer insulating film covering MI SFETQm and Qn, 1
0 is a connection hole, 11 is an n+ type (high impurity concentration) semiconductor region, and 12 is a wiring. The interlayer insulating film 9 is made of, for example, C
A silicon oxide film formed by VD.

It consists of a PSG film formed by CVD on top of it. The semiconductor region 11 is provided on the main surface of the source region or drain region 6A or 8 at the connection portion with the wiring 12,
It is configured to reduce the connection resistance value and prevent so-called aluminum spikes. The wiring 12 extending inside the memory cell array is a source line (SL) or data A! X(DL), and is electrically connected to a predetermined source region or drain region 6Δ through a contact hole 10.

The wiring 12 other than the memory cell array constitutes a reference voltage, a power supply voltage, or a signal wiring. Wiring 1
2 is composed of a conductive layer having a small specific resistance value, such as an aluminum film or an aluminum film doped with a predetermined impurity.

Although not shown, the mask ROM configured in this manner is covered with a passivation film and sealed with resin.

Next, the manufacturing method of this example will be briefly explained.

A method for manufacturing a mask ROM, which is an embodiment of the present invention, is described below.
Each of the 11 manufacturing steps is shown in FIGS. 3 to 6 (cross-sectional views).

First, on the main surface of the semiconductor substrate 1 between the semiconductor element formation regions,
Field insulating film 2 and p-type channel stopper region 3
form.

Thereafter, a gate insulating film 4 is formed on the main surface of the semiconductor substrate 1 in a region surrounded by the field insulating film 2. The gate insulating film 4 is formed of, for example, a silicon oxide film formed by thermal oxidation technology.

As shown in FIG. 3, a gate electrode 5 and a word line (WL (not shown)) are formed on a predetermined portion of the gate insulating film 4.
Form 5A. The gate electrode 5 and the word line 5A are formed of, for example, a polycide film in which a refractory metal silicide film is laminated on a polycrystalline silicon film.

After the step of forming the gate electrode 5 and word n5A shown in FIG. 3, as shown in FIG.
N-type source and drain regions 6A are formed on the main surface of the semiconductor substrate 1 on the sides thereof. These source and drain regions 6A are located in the MiSFETQn formation region (peripheral circuit) 11, and are formed in an n-type semiconductor region (LDD section) 6B formed on the main surface of the semiconductor substrate 1 on the side of the gate electrode 5.
It is formed in the same manufacturing process.

The source region, the drain region 6A, and the semiconductor region 6B are
lXl0'''~2X10''' [atoms/
It is formed by introducing phosphorus with a low impurity concentration of about 1.a++'' by ion implantation technology.In other words, the source region and drain region 6A are composed of a series resistor of about 40 KΩ or more that can read information. do.

Below this, no read operation is performed.

In this way, in a mask ROM in which an LDD structure MISFET is formed in one peripheral circuit, MISFET Q
MISFETQ that constitutes a memory cell in the same manufacturing process as the process of forming the nLD part (semiconductor region 6B)
m source and drain regions 6A can be formed. In this step of forming the source region and drain region 6A, it is possible to form a plurality of MISFETs Qm with '0'' (or "1") information having a predetermined threshold voltage. and semiconductor region 6B may be formed in separate steps in order to optimize each.

After the step of forming the source region, drain region 6A, and semiconductor region 6B shown in FIG. 4, an impurity introducing mask 7, that is, a side wall spacer (side wall) for forming an LDD is formed on the side of the gate electrode #@5. do. The impurity introduction mask 7 is formed, for example, by subjecting a silicon oxide film formed by CVD to anisotropic etching such as reactive ion etching.

After this, although no reference numerals are given, the anisotropic etching removes the goo 1-zetsuyu 1-4 on the source fiH, drain region 6A, and semiconductor region 6B.

A new insulating film is formed on this removed portion.

This insulating film acts as a barrier for contaminants that change the threshold voltages of MISFETQrn and Qn when impurities are introduced by ion implantation.

Then, n-type impurities are introduced only in the M I S F E T Q n formation region (peripheral circuit), and as shown in FIG.
form. The source region and drain region 8.

Mainly, using the impurity introduction mask 7, 1 to 2 × 10
” It is formed by introducing arsenic with a high impurity concentration of about [atoms/cm2] by ion implantation.In the process of forming the source region and drain region 8, MISF
ETQn is formed.

After the step of forming the M I S F E T Q n shown in FIG. 5, the interlayer insulating film 9. is formed as shown in FIG. A contact hole 10, an n' type semiconductor region 11, and a wiring 12 are sequentially formed.

After the step of forming the wiring 12 shown in FIG.
As shown in the figure, a mask for impurity introduction is formed in order to write "1" (or raO") information.

This mask, as shown by the dashed line in FIG.
It has an opening 14 through which a portion of the source region or drain region 6A of Qm is exposed.

The mask is formed of, for example, a photoresist film.

Thereafter, using the mask, a part of the source or drain region 6A is passed through the interlayer insulating film 9.

A p-type impurity (boron) is introduced by ion implantation. As a result, as shown in FIG. 2 above.

An i-type semiconductor region 13 can be formed in which a portion of the source region and drain region 6A is substantially disconnected, and a MI SFETQm in which information is written is completed.

Semiconductor region 13 (iHt, e.g. 2Xlo13-10
It can be formed by introducing boron of about XIO13 [atoms/cm"] or more by ion implantation. With ion implantation, the amount of impurity implanted can be accurately determined by knowing the current value, so the source A part of the region or drain region 6A is precisely i-type (or p-type).
type). Furthermore, it is sufficient to consider the implantation energy, the rate of impurity arrival at the substrate due to ion species, the ion activation rate due to annealing, and the like. Since the impurity is introduced after forming the wiring (for example, aluminum film) 12, heat treatment at only about 450['C] can be performed. Therefore, since the activation rate of the impurity is lower than that of the impurity forming the source and drain regions 6A,
The impurities are introduced in large amounts. However, since the source region and drain region 6A are formed with a low impurity concentration, crystal defects may occur that degrade the pn junction breakdown voltage between the semiconductor region 7 and the source or drain region 6A or cause leakage current. Impurities can be introduced at a low impurity concentration to the extent that there is no impurity. The impurity can be introduced through the gate electrode 5 at a low energy that does not reach the channel formation region, for example, at an energy of about 150-200 [KeV]. Therefore, it is possible to introduce single-charged impurities and increase productivity.

In this way, MISFETQm is formed with the source region or drain region 6A having a low impurity concentration.

Wiring (DL and 5L) 1 via interlayer insulation 'plA9
2, impurities were introduced into a part of the source region and drain region 6A of MISFETQm to substantially disconnect the source region and drain region 6A.
By forming ETQm.

Since information can be written after the process of forming the wiring 12, which is the final stage of the manufacturing process, it is possible to reduce the number of addresses by one.

Furthermore, by introducing impurities into the source region and the drain region 6A, the interlayer insulating film 9 can be removed without passing through the gate electrode 5.
Because it only passes through, impurities can be introduced with low energy. Therefore, one layer of insulation! Since it is no longer necessary to remove the gate 119 and expose the gate Wi[lI5, it is possible to reduce fluctuations in the threshold voltage of the M I SFETQm due to contaminants and improve the electrical reliability of the mask ROM. Further, since the interlayer insulating film 9 is not removed, there is no step difference caused by its removal, and the coverage of the wiring 12 can be improved.

In addition, by introducing impurities with low energy and low impurity concentration, it is possible to reduce crystal defects that occur particularly in the pn junction portions of the source and drain regions 6A, thereby reducing leakage electrodes and reducing power consumption. It is possible to reduce or prevent the occurrence of latch-up. Moreover,
Since crystal defects occur only in extremely narrow areas at the junction between the source or drain region 6A and the semiconductor region 13(i), they contribute to the leakage current, so the leakage current can also be reduced from this point of view. I can do it.

In addition, by introducing impurities at low energy and low impurity concentration, even if crystal defects occur, the degree of occurrence is small, so heat treatment at a low temperature of about /150 ['C] can sufficiently eliminate crystal defects. can be recovered.

Further, by forming the gate electrode 5 with a conductive layer such as a polycide film through which impurities hardly pass, the difference in transmittance of impurities can be increased.

The energy of impurities introduced into the source region and drain region 6A can be easily controlled.

Further, a semiconductor region 13(i) is formed in a part of the drain region 6A.
In the case where M is formed, the semiconductor region 13(i) has M
In order to isolate the ISFET from the voltage applied to the electrode 12, it is possible to reduce hot carriers caused by junction leakage current due to crystal defects from being captured in the gate insulating film 4 by the action of the electric field of the gate electrode 5. MIS seen
Since fluctuations in the threshold voltage of FETQrn and increases in junction leakage current can be reduced, the electrical reliability of the mask ROM can be improved.

Note that, although not shown, a passivation film is formed after the step of forming MISFETQm shown in FIG. 2.

Through these series of manufacturing steps, the mask ROM of this embodiment
is completed.

Although the invention made by the present inventor has been specifically explained above based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in one aspect of the present invention, the semiconductor region 13 (
Impurities forming i) may be introduced.

Further, according to the present invention, impurities forming the semiconductor region 13(i) may be introduced into the source region and the drain region 6A.

Further, the present invention can be applied to a horizontal mask ROM using a p-channel MISFET as a memory cell.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

In a mask ROM, a MISFET (memory cell) is formed in a source region and a drain region with low impurity concentration, and a data line is formed with an interlayer insulating film interposed therebetween.
By introducing impurities into part of the source or drain region of the IS FET to form a MIS FET with the source or drain region essentially disconnected, a data line, which is the final stage of the manufacturing process, is formed. Since the information can be written after the process of , it is possible to reduce the number of addresses by one.

Moreover, since it does not pass through the gate electrode of the MI S FET, impurities can be introduced with low energy and low impurity concentration, and the gate electrode can be prevented from being exposed by eliminating the step of removing the interlayer insulating film. That is, M I S
Since fluctuations in the threshold voltage of the FET can be reduced, the electrical reliability of the mask ROM can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view of essential parts of a mask ROM which is an embodiment of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIGS. 3 to 6 are FIG. 3 is a cross-sectional view of a main part of a mask ROM according to an embodiment showing each manufacturing process. In the figure, Qm, Qn-M I SFE T, ■...''-
L conductor substrate, 4... gate insulating film, 5... gate 7
Ii pole, 6A. 8... Source region or drain region, 6B... Semiconductor region (LDD part), 9... Interlayer insulating film, 12... Wiring (source line or data line), 13... Semiconductor region, 1
4... It is an opening.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device with a non-volatile memory function in which a memory cell is configured by MISFET, comprising:
The memory cell is formed by a MISFET having a source region and a drain region with a lower impurity concentration than other MISFETs.
A step of forming an ISFET, a step of forming a data line on the memory cell with an interlayer insulating film interposed therebetween, and a step of forming the interlayer insulating film in the source region or drain region of a predetermined memory cell among the memory cells 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of introducing impurities of opposite conductivity type through the semiconductor integrated circuit device and substantially disconnecting a part of the source region or the drain region. 2. The semiconductor integrated circuit device according to claim 1, wherein the step of disconnecting a part of the source region or drain region of the memory cell is a step of writing information into the memory cell. manufacturing method. 3. A patent characterized in that the MISFET other than the memory cell is formed with an LDD structure, and the source region or drain region of the memory cell is formed in the same manufacturing process as the LDD portion of the MISFET other than the memory cell. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 4. The method of manufacturing a semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the memory cell constitutes a horizontal mask ROM.