JPS62188263A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPS62188263A JPS62188263A JP61030020A JP3002086A JPS62188263A JP S62188263 A JPS62188263 A JP S62188263A JP 61030020 A JP61030020 A JP 61030020A JP 3002086 A JP3002086 A JP 3002086A JP S62188263 A JPS62188263 A JP S62188263A
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- memory cells
- column
- wires
- row
- ground
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Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 239000011159 matrix material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 2
- 210000004027 cell Anatomy 0.000 description 44
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体記憶装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.
半導体記憶装置の高密度化に対して、回路技術、微細化
技術及びレイアウト技術等様々な面からの努力がなされ
て来ているが、最近では、その傾向が一段と進み、半導
体記憶装置の動作特性を損わない範囲で出来るだけ重複
や繰返しを避は配線等素子以外の部分の占める面積を極
力減らしてさらに高密度化を計るというところまで来て
いる。Efforts have been made to increase the density of semiconductor memory devices from various aspects such as circuit technology, miniaturization technology, and layout technology.Recently, this trend has progressed further, and the operating characteristics of semiconductor memory devices have improved. We have reached the point where we are trying to avoid duplication and repetition as much as possible without damaging the design, and to further increase the density by reducing the area occupied by wiring and other parts as much as possible.
従来、この種の半導体記憶装置としては、行列状に配置
した複数の記憶セルの接地点を行(又は列)ごとに接地
線に直接接続するのではなく、記憶セルの接地点を行(
又は列)ごとに接続線に接続し、所定数の記憶セルの列
(又は行)ごとに接地線によって接続線を接続した構成
となっていた。Conventionally, in this type of semiconductor memory device, the ground points of a plurality of memory cells arranged in a matrix are not directly connected to a ground line for each row (or column), but the ground points of the memory cells are connected to a ground line in each row (or column).
The connection line is connected to a connection line for each column (or column) of a predetermined number of memory cells, and the connection line is connected to a ground line for each column (or row) of a predetermined number of memory cells.
第2図は従来の半導体記憶装置の一例の回路図、第3図
は半導体記憶装置を構成する記憶セルの回路図である。FIG. 2 is a circuit diagram of an example of a conventional semiconductor memory device, and FIG. 3 is a circuit diagram of a memory cell forming the semiconductor memory device.
この半導体記憶装置は、記憶セルMA−MHと第1及び
第2の読出し書込みトランジスタA1〜H1及びA2〜
H2とを行列に配置し、第1及び第2の読出し書込みト
ランジスタA1〜H1及びA2〜H2のそれぞれ一方の
電極を記憶セルMA−MHにそれぞれ接続し、第1及び
第2の読出し書込みトランジスタA工〜H□及びA2〜
H2の他方の電極なそれぞれ列に接続してこれをそれぞ
れ第1及び第2のビット線d及び1とし、記憶セルの接
地点を行ごとに接続してこれを接続線4及び6とし、所
定数の記憶セルの列(ここでは4列)ごとに接続線4及
び6を接続しこれを接地線1及び2とし、@1及び第2
の読出し書込みトランジスタA1〜H1及びA2〜H2
のゲートを行ごとに共通に接続してこれをワード線3′
及び5′とした構成になりていた。This semiconductor memory device includes memory cells MA-MH and first and second read/write transistors A1 to H1 and A2 to
H2 are arranged in a matrix, one electrode of each of the first and second read/write transistors A1-H1 and A2-H2 is connected to the memory cells MA-MH, and the first and second read/write transistors A Engineering~H□ and A2~
The other electrodes of H2 are connected to the respective columns to form the first and second bit lines d and 1, respectively, and the ground points of the memory cells are connected to each row to form the connection lines 4 and 6. Connection lines 4 and 6 are connected for each column of memory cells (4 columns in this case), and these are used as ground lines 1 and 2.
read/write transistors A1-H1 and A2-H2 of
The gates of each row are commonly connected and connected to the word line 3'.
and 5'.
即ち、複数の記憶セルの列(ここでは4列)に共通に接
地線を設けることにより、比較的記憶容量の少ないこれ
までの半導体記憶装置のように記憶セルの各列ごとに接
地線を設ける構成に比べて接地線の領域面積を減らし、
半導体記憶装置の集積度を一段と向上させることができ
た。That is, by providing a common ground line for multiple columns of memory cells (four columns in this case), it is possible to provide a ground line for each column of memory cells, unlike conventional semiconductor memory devices with relatively small storage capacity. Reduce the area area of the ground wire compared to the configuration,
The degree of integration of semiconductor memory devices could be further improved.
また、この半導体記憶装置に含まれる記憶セルMA−M
Hは、第3図に示すように、メモリトランジスタQ1及
びQ2によって一種の7リツプ70ツブ回路を構成して
いる。Furthermore, memory cells MA-M included in this semiconductor memory device
As shown in FIG. 3, H constitutes a kind of 7-lip, 70-tub circuit with memory transistors Q1 and Q2.
上述した従来の半導体記憶装置は、記憶セルの接地点が
接続線を介して接地線と接続しているので、接続線の抵
抗によって、記憶セルの接地点と接地線との間に電流が
流れると記憶セルの接地点と接地線間に電位差が生じる
という欠点がある。In the conventional semiconductor memory device described above, the ground point of the memory cell is connected to the ground line via the connection line, so a current flows between the ground point of the memory cell and the ground line due to the resistance of the connection line. There is a drawback that a potential difference occurs between the ground point of the memory cell and the ground line.
このことについて、第2図を参照しながら、具体的に説
明すると、先ずワード線3′に高レベルの電位を与えて
、読出し書込みトランジスタA1+A2〜D□+D2を
オン状態にすると、記憶セルMA〜MDのメモリトラン
ジスタQ1及びQ2とピット線d及びτとが接続され駆
動状態となる。この時、tmz−らオン状態のメモリト
ランジスタから記憶セルの接地点を通りて接地線1及び
2へ流れ込む電流1hxe iAz〜tpt、tpzは
、第2図に示すように流れる。ただし、駆動状態にない
記憶セルにも電流は流れるが、一般に駆動状態の時より
も非常に小さい。従って、記憶セルMA及びMBの接地
点A及びBの電位vA及びvdは、接地線の抵抗をRと
すると、
VA==RX(i人1+1B1−1− i01+1D1
) ・”=(1)VB =VA+2RX(tni+io
x+1nt−i人z)−(z)となる。To explain this in detail with reference to FIG. 2, first, a high level potential is applied to the word line 3' to turn on the read/write transistors A1+A2 to D□+D2, and then the memory cells MA to The memory transistors Q1 and Q2 of the MD are connected to the pit lines d and τ and are in a driven state. At this time, currents 1hxe iAz - tpt, tpz flowing from the memory transistors in the on state through the grounding points of the storage cells to the grounding lines 1 and 2 flow as shown in FIG. However, although current also flows in memory cells that are not in the driven state, it is generally much smaller than when the memory cells are in the driven state. Therefore, the potentials vA and vd of the ground points A and B of the memory cells MA and MB are as follows, where the resistance of the ground line is R, VA==RX(i person 1+1B1-1-i01+1D1
) ・”=(1)VB=VA+2RX(tni+io
x+1nt-i personz)-(z).
ここで、各記憶セルの各々の電流比1A1/1人2〜i
D1/ID2は記憶セルMA−MDの各接地点から左の
接地線1及び右の接地線2を見たそ名ぞれのインピーダ
ンスの比の逆数によって決まるのでとなる。Here, each current ratio of each memory cell is 1A1/12~i
This is because D1/ID2 is determined by the reciprocal of the ratio of the impedances of the left ground line 1 and the right ground line 2 viewed from each ground point of the memory cells MA-MD.
又、各記憶セルの電流の和iA1+iAz、〜1iDl
+inzが等しく
iA1+1A2=:1B1−1−iB2:・・・・・・
=iD1−1−iD2=Iと置けるとし、更に、接地線
1と接地線2との間でその中央から左右が対称であると
すると、左の接地線1に流れ込む電流の合計と右の接地
線2に流れ込む電流の合計とが等しくなり
iAx+・・・・・・+1D1=i、+u+・・・・・
・+tD2=2Iと表わすことができる。したがって、
■=810 と置いて、式(1)及び(2)を展開す
るとVi=16ia R=2IR−・・・・・−(31
V B ”MA + 16 lo R” 32 io
R= 4 I R・・・・・・・” t4)となる。Also, the sum of the currents of each memory cell iA1+iAz, ~1iDl
+inz are equal iA1+1A2=:1B1-1-iB2:...
=iD1-1-iD2=I, and further assume that grounding wire 1 and grounding wire 2 are symmetrical from the center, then the sum of the current flowing into left grounding wire 1 and the right grounding The total current flowing into line 2 is equal to iAx+...+1D1=i, +u+...
・It can be expressed as +tD2=2I. therefore,
If we set ■=810 and expand equations (1) and (2), we get Vi=16ia R=2IR-...-(31
V B “MA + 16 lo R” 32 io
R= 4 I R..." t4).
■(又はto )及びRは回路構成やプロセス条件によ
シ様々な値に設定することができるが、代表的な値とし
て、I =200〜300μA 、 R=20〜30Ω
を用いると、Vλ=8〜18 mV + Vi3 =
16〜36mVとなる。この値は半導体基板の浮き電位
によるトランジスタのしきい電圧の変動や個々のトラン
ジスタのばらつき等を考えると無視できない値である。(or to) and R can be set to various values depending on the circuit configuration and process conditions, but typical values are I = 200 to 300 μA, R = 20 to 30 Ω.
Using, Vλ=8~18 mV + Vi3 =
It becomes 16-36mV. This value cannot be ignored when considering fluctuations in the threshold voltage of the transistor due to the floating potential of the semiconductor substrate, variations in individual transistors, and the like.
又、この値は、記憶セルが4列ごとに接地線を設けた場
合であるが、もっと集積度を向上させる為に、16列ご
とあるいは32列ごとに接地線を設ける場合等はもっと
深刻な問題となって来る。Also, this value is for the case where a ground line is provided for every 4 columns of memory cells, but if a ground line is provided for every 16 columns or every 32 columns in order to further improve the degree of integration, the situation becomes more serious. It becomes a problem.
本発明の目的は、複数の記憶セルの列(又は行)が接続
線を介して接地線を共有することにより記憶密度を向上
し、しかも記憶セルの接地点と接地線との間の電位差を
極力減らして安定に動作することができる半導体記憶装
置を提供することにある。An object of the present invention is to improve storage density by allowing a plurality of columns (or rows) of memory cells to share a ground line via a connection line, and to reduce the potential difference between the ground point of the memory cell and the ground line. It is an object of the present invention to provide a semiconductor memory device that can operate stably with as little reduction as possible.
本発明の半導体記憶装置は、行列に配置された複数の記
憶セルと、所定数の前記記憶セルの列(又は行)ごとに
列(又は行)方向に配置された接地線と、該接地線の間
の中央またはその近傍で隣り合う二つの行(又は列)の
組ごとにたすき掛けとなるように配線されかつ前記記憶
セルを行(又は列)方向に共通接続するワード線、また
は前記接地線の間の中央またはその近傍で隣り合う二つ
の行(又は列)の組ごとにたすき掛けとなるように配線
されかつ前記記憶セルの接地点及び接地線を行(又は列
)方向に接続する接続線とを含んで構成される。A semiconductor memory device of the present invention includes a plurality of memory cells arranged in rows and columns, a ground line arranged in the column (or row) direction for each column (or row) of a predetermined number of the memory cells, and the ground line a word line that is wired so as to cross each other for each pair of two adjacent rows (or columns) at or near the center between them, and commonly connects the memory cells in the row (or column) direction, or the ground; Wiring is done so that each set of two adjacent rows (or columns) is crossed at or near the center between the lines, and the ground point and ground line of the memory cell are connected in the row (or column) direction. and a connecting line.
次に、本発明の一実施例について図面を参照して説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.
第1図は本発明の半導体記憶装置の一実施例の回路図で
ある。FIG. 1 is a circuit diagram of an embodiment of the semiconductor memory device of the present invention.
この実施例の半導体記憶装置は、記憶セルMA〜MHと
第1及び第2の読出し書込みトランジスタAl−Hl及
びA2〜H2とを行列に配置し、第1及び第2の読出し
書込みトランジスタA1〜H1及びA2〜H2のそれぞ
れ一方の電極を記憶セルMA〜MHに接続し、他方の電
極をそれぞれ列に接続してこれを第1及び第2のビット
線d及び1とし、記憶セルMA−MHの接地点を行ごと
に接続してこれを接続線4及び6とし、所定数の記憶セ
ル列(ここでは4列)ごとに接続線4及び6を接続しこ
れを接地線1及び2とし、接地線1及び20間の中央で
隣り合う二つの行の組ごとにたすき掛けとなるように配
線されかつ第1及び第2の読出し書込みトランジスタA
l〜B2.C,〜D 2 、 E 1〜F2及び01〜
H2のゲートを行方向に共通接続しこれをワード線3及
び5として構成される。The semiconductor memory device of this embodiment has memory cells MA to MH and first and second read and write transistors Al-Hl and A2 to H2 arranged in a matrix, and first and second read and write transistors A1 to H1. One electrode of each of A2 to A2 to H2 is connected to the memory cells MA to MH, and the other electrode is connected to a column to form the first and second bit lines d and 1. Connect the grounding points for each row and use them as connection lines 4 and 6. Connect the connection lines 4 and 6 for every predetermined number of memory cell columns (here, 4 columns) and use them as grounding lines 1 and 2. The first and second read/write transistors A are wired so as to cross each other in pairs of two adjacent rows at the center between the lines 1 and 20.
l~B2. C, ~D2, E1~F2 and 01~
The gates of H2 are commonly connected in the row direction and are configured as word lines 3 and 5.
次に、この実施例の動作について第1図を参照しながら
説明する。Next, the operation of this embodiment will be explained with reference to FIG.
ワード線3を高レベルの電位、ワード線5を低レベルの
電位にそれぞれすると、第1及び第2の読出し書込みト
ランジスタA1〜B2及び01〜H2がオン状態、第1
及び第2の読出し書込みトランジスタC□〜D2及びE
l〜F2がオフ状態にそれぞれなシ、記憶セルMAaM
B、MG及びMHはビット線d及び丁と接続され駆動状
態となるが、記憶セルM□+MD 1MB及びM、はビ
ット線d及びτと接続されない。この場合、駆動状態に
ない記憶セルM() + MD t MB及びM、の電
流io1〜iD2及びfit〜iF2の大きさは駆動状
態にある記憶セルM人。When the word line 3 is set to a high level potential and the word line 5 is set to a low level potential, the first and second read/write transistors A1 to B2 and 01 to H2 are turned on, and the first
and second read/write transistors C□-D2 and E
When l to F2 are in the off state, the memory cell MAaM
B, MG, and MH are connected to bit lines d and d and are in a driven state, but memory cells M□+MD 1MB and M are not connected to bit lines d and τ. In this case, the magnitudes of the currents io1~iD2 and fit~iF2 of the memory cells M()+MDt MB and M, which are not in the driven state, are the same as those of the memory cells M who are in the driven state.
MB、MG及びMHの電流iAt 〜inz及びtot
〜lH,zの大きさに比べて一般に非常に小さいので
、記憶セルM人及びMBの接地点A及びBの′電位vA
及びVBは、はぼ
VA=R・(iAt+i+n )=12io R=(3
/2)IR−(5)VB=VA+2R−(1nx−fA
2) =20io R= (5/2)IR−(a)とな
って、従来例と比較すると
v人=〒V大
と表わすことができる。Currents iAt ~inz and tot of MB, MG and MH
Since it is generally very small compared to the magnitude of ~lH,z, the potential vA of the ground points A and B of the memory cell M and MB
and VB is VA=R・(iAt+i+n)=12io R=(3
/2)IR-(5)VB=VA+2R-(1nx-fA
2)=20io R=(5/2)IR-(a), and when compared with the conventional example, it can be expressed that v people=〒V large.
従りて、接地点A及びBの電位が従来例の75%及び6
2.5%にそれぞれ減少し、このような高記憶密度の半
導体記憶装置の動作をより安定にすることができる。Therefore, the potentials of ground points A and B are 75% and 6% of the conventional example.
2.5%, respectively, and the operation of such a high storage density semiconductor memory device can be made more stable.
又、このような傾向は、この実施例のように記憶セルが
4列ごとに接地線を設けた場合よりも、16列ごとある
いは32列ごとと、接地線を設ける間隔を広げる程、そ
の減少効果はより顕著になる。In addition, this tendency is more likely to decrease as the spacing between ground wires is increased, such as every 16th or 32nd column, compared to the case where a grounding line is provided every 4th column of memory cells as in this embodiment. The effect becomes more pronounced.
なお、本実施例では、偶数の記憶セルの列ごとに接地線
を設けているが必ずしも偶数の列ごとに設ける必要はな
く奇数の列ごとでもかまわない。In this embodiment, a ground line is provided for each even-numbered column of memory cells, but it is not necessarily necessary to provide a ground line for each even-numbered column, and it may be provided for each odd-numbered column.
ただし、奇数の列ごとに接地線を設ける場合には、ワー
ド線をたすき掛けに接続する場所は接地線の間の中央よ
り左右どちらか一方にずれた所となるが、偶数の場合と
同様の効果が期待できる。However, if a ground line is provided for each odd-numbered column, the place where the word line is connected cross-wise is offset to the left or right from the center between the ground lines, but the same You can expect good results.
更に、この実施例では、ワード線を接地線の間の中央で
隣り合う行同士たすき掛けをするように接続しているが
、ワード線の代シに筬続線を隣り合う行同士たすき掛け
をするように接続しても艮いことは自明である。Furthermore, in this embodiment, the word lines are connected so that adjacent rows cross each other at the center between the ground lines, but in place of the word lines, a reed connecting line is connected so that adjacent rows cross each other. It is obvious that there is no problem in connecting it as shown.
以上説明したように本発明は、複数の記憶セルの列(又
は行)ごとに設けられた接地線の間の中央又はその近傍
において行(又は列)方向に配したワード線又は接続線
を隣シ同士たすき掛けに接続することにより、より一層
高密度化を意図する半導体記憶装置の記憶セルの接地点
と接地線との間の電位差を極力減らして安定に動作をさ
せるという効果がある。As explained above, the present invention connects word lines or connection lines arranged in the row (or column) direction at or near the center between the ground lines provided for each column (or row) of a plurality of memory cells. By cross-connecting the semiconductor memory devices, the potential difference between the ground point and the ground line of the memory cells of a semiconductor memory device intended to be further increased can be reduced as much as possible, resulting in stable operation.
第1図は本発明の半導体記憶装置の一実施例の回路図、
第2図は従来の半導体記憶装置の一例の回路図、第3図
は半導体記憶装置を構成する記憶セルの回路図である。
1.2・・・・・・接地線、3,3′・・・・・・ワー
ド線、4・・・・・・接続線、5,5′・・・・・・ワ
ード線、6・・・・・・接続線、A1+A2〜Hl、H
2・・・・・・読出し書込みトランジスタ、d、d・・
・・・・ビット線、iAl 、 iA2〜iH1,iH
2・・・・・・記憶セルの接地電流、MA−MH・・・
・・・記憶セル、Q□、Q2・・・・・・トランジスタ
、R,r・・・・・・抵抗、vcc・・・・・・電源電
圧。FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention;
FIG. 2 is a circuit diagram of an example of a conventional semiconductor memory device, and FIG. 3 is a circuit diagram of a memory cell forming the semiconductor memory device. 1.2...Grounding line, 3,3'...Word line, 4...Connection line, 5,5'...Word line, 6. ...Connection wire, A1+A2~Hl, H
2...Read/write transistor, d, d...
...Bit line, iAl, iA2~iH1, iH
2...Memory cell ground current, MA-MH...
...Memory cell, Q□, Q2...Transistor, R, r...Resistance, vcc...Power supply voltage.
Claims (1)
憶セルの列(又は行)ごとに列(又は行)方向に配置さ
れた接地線と、該接地線の間の中央またはその近傍で隣
り合う二つの行(又は列)の組ごとにたすき掛けとなる
ように配線されかつ前記記憶セルを行(又は列)方向に
共通接続するワード線、または前記接地線の間の中央ま
たはその近傍で隣り合う二つの行(又は列)の組ごとに
たすき掛けとなるように配線されかつ前記記憶セルの接
地点及び接地線を行(又は列)方向に接続する接続線と
を含むことを特徴とする半導体記憶装置。A plurality of memory cells arranged in a matrix, a ground line arranged in the column (or row) direction for each column (or row) of a predetermined number of the memory cells, and a ground line at or near the center between the ground lines. A word line that is wired across each pair of adjacent rows (or columns) and commonly connects the memory cells in the row (or column) direction, or the center or the vicinity thereof between the ground lines. and a connection line that is wired so as to cross each other between two adjacent rows (or columns) and connects the ground point and ground line of the memory cell in the row (or column) direction. A semiconductor storage device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61030020A JPH079949B2 (en) | 1986-02-13 | 1986-02-13 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61030020A JPH079949B2 (en) | 1986-02-13 | 1986-02-13 | Semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62188263A true JPS62188263A (en) | 1987-08-17 |
JPH079949B2 JPH079949B2 (en) | 1995-02-01 |
Family
ID=12292154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61030020A Expired - Lifetime JPH079949B2 (en) | 1986-02-13 | 1986-02-13 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH079949B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5379247A (en) * | 1992-09-28 | 1995-01-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including memory cells connected to a ground line |
KR100486025B1 (en) * | 1998-06-29 | 2005-07-18 | 현대중공업 주식회사 | Motor driven control method of steel rolling line. |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56130886A (en) * | 1980-03-14 | 1981-10-14 | Nec Corp | Semiconductor memory device |
JPS6028261A (en) * | 1983-07-27 | 1985-02-13 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1986
- 1986-02-13 JP JP61030020A patent/JPH079949B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56130886A (en) * | 1980-03-14 | 1981-10-14 | Nec Corp | Semiconductor memory device |
JPS6028261A (en) * | 1983-07-27 | 1985-02-13 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5379247A (en) * | 1992-09-28 | 1995-01-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including memory cells connected to a ground line |
US5463576A (en) * | 1992-09-28 | 1995-10-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including memory cells connected to a ground line |
EP0817270A2 (en) * | 1992-09-28 | 1998-01-07 | Mitsubishi Denki Kabushiki Kaisha | Improved semiconductor memory device including memory cells connected to a ground line |
EP0817270A3 (en) * | 1992-09-28 | 1998-03-18 | Mitsubishi Denki Kabushiki Kaisha | Improved semiconductor memory device including memory cells connected to a ground line |
USRE36531E (en) * | 1992-09-28 | 2000-01-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including memory cells connected to a ground line |
KR100486025B1 (en) * | 1998-06-29 | 2005-07-18 | 현대중공업 주식회사 | Motor driven control method of steel rolling line. |
Also Published As
Publication number | Publication date |
---|---|
JPH079949B2 (en) | 1995-02-01 |
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