JPS62151768A - Testing method for interface signal between channel device and input/output controller - Google Patents

Abstract

PURPOSE:To take a test efficiently by a channel incorporated program by delaying the transmission timing of a tag-out signal from a channel device corresponding to a tag-in signal optionally when the tag-in signal from an input/ output controller is detected. CONSTITUTION:The channel device 104 operates according to a program in control storage 111 under the command of an input/output processor 103. Namely, the program sets and resets the tag-out signal of a tag-out register 112 according to the procedure of data interchange and detects a tag-in signal from a corresponding to an input/output controller 105 through a tag-in register 113 to interchange addresses and data at the response timing of the tag-in and -out signals. For the purpose, the timing where the tag-out signal detected by the program is set in the register 112 is delayed by the program to delay an interface signal viewed from the device 104 without cascading many devices 105, thereby testing the allowable limit of the delay of the device 15 automatically and easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a test method for testing the permissible limit of delay in an interface signal between a channel device and an input/output control device.

[Background of the invention]

Many input/output control devices, especially video terminals, are often serially connected to the same channel device. At this time, propagation delays of interface signals due to each input/output control device are superimposed, resulting in a large delay as a whole, which may cause unexpected failures. To predict this in advance and take countermeasures, tolerance limit tests are performed on the delay of interface signals between channel devices and input/output control devices. However, conventionally, tests have been conducted by serially connecting a large number of actual input/output control devices to a cable and bypassing unnecessary input/output control devices. In addition to requiring the following, there was a problem in that the test required a large amount of time.

Note that Japanese Patent Application Laid-Open No. 55-59523, for example, is related to a method of testing the permissible limit of delay of this type of interface signal.

[Purpose of the invention]

An object of the present invention is to test the limit value of a channel device, an input/output control device, or an input/output device that causes a failure due to a signal delay occurring on the interface between the channel device and the input/output control device. The purpose of the present invention is to provide a method for easily and efficiently testing using a built-in channel program without serially connecting a large number of channels.

[Summary of the invention]

The present invention provides a timer that generates an arbitrary delay time, a function for inserting the timer between an arbitrary tag-in and a corresponding tag-out, and a value that defines the insertion timing and the time at which the timer is generated. The channel program has a function to hold the value and a function to update the value by itself, so that the interface signal can be arbitrarily delayed by the channel device. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of an embodiment of the present invention.

In FIG. 1, a central processing unit (CPU) 101 and an input/output processing unit (■○P) 103 are connected to a main storage device (MS) 10.
2, and a channel device (C
H) 104 is connected to the channel device 104, and an input/output control device (IOC) 105 is connected to the channel device 104. Although not shown in FIG. 1, an input/output device is connected to the input/output control device 105. The channel logic unit 110 of the channel device 104 includes a control memory (C8) 111, which stores a program for controlling the operation of the channel. 1
12 is a tag-out register, 113 is a tag-in register, 114 is a bus-out register, 115 is a pass-in register, and 116 is a register that holds a test code and a timer code.

The channel device 104 operates according to the program in the control memory 111 based on instructions from the input/output processing device 103 . The program sets/resets each tag-out signal included in the tag-out register 112 according to a predetermined data exchange procedure, and sends the tag-in signal from the input/output control device 105 in response to this via the tag-in register 113. Detect. Then, at an appropriate timing in response to the tag-out/in signal, addresses and data are exchanged by writing/writing to the bus-out register 114 and the pass-in register 115. In the present invention, the program delays the timing at which the program sets the tag-out signal in the tag-out register 112 in response to the tag-in signal detected by the program.

FIG. 2 is a timing chart showing an example of the response of an interface signal between the channel device 104 and the input/output control device 105, and is an example of an initial select sequence. Here, an example is shown in which a delay is implemented for command out among timing out signals. In fig.

T-T4 indicates the change points of the tag-in signal to be tested. T1' to T4' indicate changing points of the tag-out signal with respect to the tag-in signal. t□~t4 is T n = T
It shows the time required for a response of n' (n = 1-4).

The program flow of the channel device 104 according to FIG. 2 is shown in FIG. Symbols correspond to FIG. Also,
1 to 11 in FIGS. 2 and 3 indicate sequence numbers,
This corresponds to the item number in the explanation below.

(1) The channel device 104 that has received the command to activate the input/output control device 105 sets the address of the device to be activated in the bus out register 114, and sends the address via the tag out register 112. Raise out. Next, raise select out to request a response from the device. I/O controller 105 responds with an operational in.

(2) The channel detects an operational in via the tag in register 113 at the timing of T. The program jumps to a determination routine that corresponds one-to-one to T4.

The judgment routine determines whether or not to apply a delay in register 1 in advance.
The determination is made based on the program parameters set in No. 16, and the timer routine is executed when necessary. The parameters include
There is a test code that determines whether a delay is possible and a timer code that determines the delay time.

In the example shown in FIG. 2, it is determined that no delay is necessary, the tag-in process is ended without executing the timer routine, and the process proceeds to the next tag-out process.

(3) Lower address out at T1'. Then the address in will go up.

(4) When address-in is detected at T2, the above (2)
Perform the same processing as . In the example shown in FIG. 2, test code T2 is set, so it is determined that it is the timing to execute the timer routine, and the timer routine is executed.

(5) The timer routine refers to the timer code in the register 116 and generates a waiting time t2 in accordance with the timer code.

Since the process then proceeds to tag-out processing, the time t2 is extended, resulting in a delay at the command-out change point T2'.

After the timer is executed, the timer code is updated by +1.

As a result, at the next startup, a delay time corresponding to the value updated by +1 from the previous time is automatically provided. When the timer code exceeds a predetermined value, increase the test code by +1.
Update and return the timer code to its initial value. After implementing the test code at all the specified timings (
In this example, after the test code T4 is completed), it is returned to the initial value T1.

As described above, while T2 is set, the delay width is gradually increased until the specified timer code is reached, and when the specified timer code is reached, the test code T3 is set next.

The rising edge of service out is delayed while increasing the delay width sequentially.Then, by setting T4, the falling edge of service out is delayed while increasing the delay width sequentially, and it wraps out to Tyu and repeats endlessly. To go. This makes it possible to test the interface signal delay at the limit where channels, input/output control devices, and input/output devices fail.

Note that by prohibiting the automatic update described above, it is also possible to perform repeated tests at specific timings and with a constant timer value.

〔Effect of the invention〕

According to the present invention, regarding signal delays occurring on the interface between channel devices and input/output control devices, it is possible to delay interface signals seen from the channel side without connecting a large number of actual input/output control devices, and various input/output This has the advantage that the tolerance limit of the delay of the control device can be automatically and easily tested.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a timing chart showing an example of response of an interface signal between a channel device and an input/output control device, and FIG. 3 is a channel device according to FIG. 2. FIG. 2 is a diagram showing the flow of a program. 104... Channel device, 105... Input/output control device, 110... Channel logic unit, 111...
control memory, 112...tagout register,
113... Tag-in register, 114... Bus-out register, 115... Pass-in register, 1
16...Test/timer code register, T-T
4...Change points of tag-in signal, T1' to T4'...
Change point of tagout signal. Representative Patent Attorney Makoto Suzuki7. Sword Figure 3 Main Sequence;
L-ke/ayLfu-kesis

Claims (1)

[Claims] (1) In a method of testing the permissible limit of the delay of an interface signal between a channel device and an input/output control device, the channel device is provided with a means for generating an arbitrary delay time, and the tag-in signal from the input/output control device is detected. On the other hand, a method for testing an interface signal between a channel device and an input/output control device, characterized in that the sending timing of a tag-out signal from a channel device corresponding to the tag-in signal is arbitrarily delayed.