JPS62130437A - Lsi tracing system - Google Patents

Abstract

PURPOSE:To perform real-time tracing operation by providing two LSIs which have a switching circuit for a normal output and an internal state, and putting one LSI in operation and outputting the normal output and internal state from the other. CONSTITUTION:A master mode LSI 6 and a debugging mode LSI 14 which perform the same operation are provided with switching circuits 7 and 15, and mode signals 3 and 11 are received by the circuits 7 and 15, which output the normal output signal 4 and a normal output and internal state output signal 12 to an external circuit 5 and a tracing circuit 13. Then, a normal input signal 17 and data 18 are inputted to the LSIs 6 and 14 in common to connect the circuit 5 to a main memory 10 and also trace it by the circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Two LSIs capable of outputting a normal output signal and an internal state output signal are provided in a system, and an actual operating state for the system is generated in one of these two LSIs.
The other LSI, which is performing the same operation, outputs normal output signals and internal status output signals as trace information signals to perform real-time tracing of internal and external data of the system LSI.

[Industrial application field]

The present invention relates to an LSI tracing method, and more particularly to an LSI tracing method that can perform real-time tracing of internal and external data of an LSI when the LSI has a buffer memory.

An information processing system is provided with a debug function as a means for checking its normal operation. This debugging function is typically performed under non-normal operating conditions of the system.

However, depending on the field of use of the system, conventional debugging techniques may cause inconveniences, and there is a need for the development of means to technically solve these problems.

[Conventional technology]

Conventionally, a processor LSI with an internal buffer memory
The means to trace a program was to obtain trace information using software. This is the fourth
As shown in the figure, a process in which each time an instruction is executed, the processor is placed in a trace state or the contents of the program counter, etc. are stored in a specific memory area (trace memory) by a trace interrupt, and then returned to the instruction execution state. is repeated.

[Problem that the invention seeks to solve]

As mentioned above, this technique enters the execution of the trace routine and returns to the main program each time each instruction is executed.
It is insufficient to perform real-time tracing, and cannot be applied to fields that require a high degree of real-time performance.

The present invention was created in view of such problems, and is an LSI that can trace actual programs in real time.
- Aims to provide a racing format.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. In the figure,
1 is a device printed board, and 2 is a debug printed board.

The device printed board 1 has a master mode LS that receives the mode signal “0” 3 and outputs the normal output signal 4 to the external circuit 5.
There is an I6. Normal output signal 4 output is mode signal “0”
(3) is produced by the action of the switching circuit 7 which receives (3).

External circuit 5 is connected to main memory 10 via address line 8 and data line 9. On the debug printed board 2,
There is a debug mode LS 114 that receives a mode signal "1" 11 and outputs a normal output and an internal state output signal 12 to the trace circuit 13.

The normal output and the output of the internal state output signal 12 are produced by the action of the switching circuit 15 which receives the mode signal "1". Debug mode LS114 is master mode L
It operates exactly the same as the SI 6 and receives data 18 exchanged between the master mode LSI 6 and the external circuit 4 in addition to the normal human input signal 17 input to the master mode LSI 6 .

[Effect]

The master mode LSI 6 performs the necessary calculations in its processor section in response to the normal input signals and data supplied thereto by the action of the switching circuit 7 that receives the mode signal "0" 3, and generates the calculation result data and the address therefor. It is sent to the main memory 10 via the external circuit 5. Further, the master mode LS6 sends the normal output signal 4 to the external circuit 5.

Exactly the same process performed in the master mode LSI 6 is also performed in the Devaheg mode LS 114.

For this purpose, normal input signals and data sent to the master mode LSI 6 are also sent to the debug mode LSIL 4, and the same calculations as those performed in the LSI 6 are performed in the LS 114. At this time, since the switching circuit 15 receives the mode signal "1", the normal output and internal state output signal 12 are sent to the trace circuit 13 along with the address 19 for that purpose, so that the operation being performed in the master mode LS6 is sent to the trace circuit 13. Output signals of internal states, whose processes could not conventionally be extracted outside the LSI 6, can also be sent to the trace circuit 13 in real time and traced.

〔Example〕

FIG. 2 is a detailed diagram of an embodiment of the LSI section of the block diagram shown in FIG. 1. In this figure, 20 is an LSI in the device printed board (master mode LSI), and 22 is an LSI in the debug print (debug mode LSI). All of these have the same configuration and consist of the following constituent elements, but here these constituent elements are indicated only by their constituent numbers without adding subscripts to distinguish between them.

Common normal input signal 30 and clock reset signal 3
2, a directory 36 that receives the internal address strobe F, a gate 38 that receives the control signal and mode switching signal 37 from the directory 36, and an external address bus A that receives the main memory address from the directory 36. a driver 42 that supplies data to the main memory 40 and trace memory 41 via an external data bus B; a receiver 44 that receives data sent from the main memory 40 via an external data bus B; D
a buffer memory 46 that stores data in the storage location indicated by the address sent via the directory 36, and a multiplexer 48 that selectively outputs data from the receiver 44 or data from the buffer memory 46 in response to a switching control signal from the directory 36; A driver 50 that outputs data from the processor section 34 to an external data bus B, and a multiplexer 54 that outputs a data output signal 52 from the multiplexer 48 or a normal output signal such as ACK from the directory 36 after being switched by the mode switching signal 37. configured. However, the mode switching signal 372 to the gate 382 and multiplexer 522 of the debug printed board LSI 22 is the mode switching signal sent to the device printed board LSI 20 via the inverter 56. or,
To simplify the drawing, the address strobe C is always available for output from the multiplexer.

With this configuration, each processor section 341
, 342 receive the same output signals, that is, data and normal input signals, and perform exactly the same operations. In its operation, directories 36. .

362 has a miss, that is, the processor section 341.
The data required by 342 is stored in buffer memories 461 and 4.
If it is found that the data does not exist in the main memory 40, the data is fetched from the main memory 40 (see T1 and T3 in FIG. 3). This captured data is supplied to processor sections 341, 342 and multiplexers 521, 522 via multiplexers 481, 482 which are switched and controlled by directories 361, 362. The data supplied to the multiplexer 522 is transferred to the trace memory 41
The address used to read the data supplied to the processor unit 342 is the directory 3.
It is supplied to the trace memory 41 via the address bus A under the control of 61 and 362. Thus, directory 3
The behavior of the program when 61 and 362 are not hit can be traced in real time. Processing results in the processor section 342 are also traced under the control of the processor section 342 and the directory 362.

If the directories 361, 362 are hinted, the data is provided from the buffer memories 461, 462 to the processor sections 341, 342 via the corresponding multiplexers 48+, 482 (see T2 in FIG. 3). In the master mode LSI 20 at this hint, the mode switching signal "0" is sent to the multiplexer 52. Internal address bus D internal data bus E
And internal address strobe F is master mode LS■
It does not appear outside of 20 (see Figure 3A).

On the other hand, in the debug mode LST22, the mode switching signal "1" is supplied to the multiplexer 52□, so the internal address bus D, internal data bus E, and internal address strobe F are visible outside the debug mode LSI 22. (See Figure 3B). That is, the data supplied from the buffer memory 462 to the processor section 342 is supplied to the trace memory 41 as an internal data output signal via the multiplexer 522, and the address used for reading the data supplied to the processor section 34□ is also supplied to the trace memory 41 as an internal data output signal. The directory 36° is supplied from the directory 362 to the trace memory 41 via the driver 42, and the address strobe output of the address is used as the clock input for the count amplifier of the counter 58, and the output of the counter is used as addressing for the trace memory 41. LSI when a hint occurs in 36□
Internal data (buffer memory output) can also be traced. Processing results in the processor section 342 are also traced under the control of the processor section 342 and the directory 362.

In the above embodiment, the buffer memory output was explained as an example of LSI internal data to be traced, but other LSI internal data can also be traced using the same technique.

〔Effect of the invention〕

As described above, according to the present invention, all data required by a program being executed inside the LSI can be traced in real time from the terminals of the LSI. Therefore, the behavior of the program can be determined from the outside.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention; Figure 3 is a timing chart, FIG. 4 is a diagram showing a conventional tracing method. In Figure 1, 7.15 is a switching circuit, 3.11 is a switching signal supply means; 13 is a trace circuit. In Figure 2, 341.342 is the processor part, 361.362 is the directory, 371.372 is a mode switching signal, 41 is trace memory, 461.462 is buffer memory, 48+, 482, 521.522 is a multiplexer, 58 is a counter.

Claims (1)

[Claims] In a system configured using LSI, the L
Switching circuits (7), (15) for switching the output mode of the normal output of the SI and the internal state output of the LSI, and signal supply means (3), (11) for supplying a switching signal that causes switching of the switching circuit. Two LSIs with (
6) and (14) are provided, and the signal input of both LSIs is made common, and the output mode of the switching circuit is switched by the switching signal, so that one of the two LSIs is brought into an actual operating state. An LSI tracing method characterized in that a normal output and an internal state output from another LSI performing the same operation are outputted as trace information output to generate a real-time trace.