JPS62123773A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Technical Field] This invention relates to semiconductor memory device technology and EPROM
(Electrically writable non-volatile semiconductor memory devices), such as large storage capacity EEPROMs (non-volatile semiconductor memory devices that can be electrically written and erased) It is related to effective technology that can be used for. [Background Art] As shown in FIGS. 3(a) and 3(b), a nonvolatile semiconductor memory device such as an EEPROM has a memory element of n
A floating gate electrode (FG) 6 is provided on the channel region narrowed between the + drain region 4 and the n+ type source region 3 via the first insulating film 2a, and further on the floating gate a electrode 6. It is formed by disposing a control gate electrode (PG) 5 with a second insulating film 7 interposed therebetween. In the semiconductor device shown in the figure, as the first insulating film 2a,
A part of the oxide film 2 formed entirely on the surface of the p-type semiconductor substrate 10 is used. Further, as the second insulating film 7, a nitride film having a relatively high dielectric constant is used. Reference numeral 8 indicates a wiring electrode made of aluminum or the like. D indicates a drain, and S indicates a source. Writing of storage information in this type of semiconductor memory device is performed by applying a voltage Vp between the control gate 4 poles 5 and the substrate 1. In other words, the control gate 4 poles 5 and the floating gate electrode 6 In between is an electrostatic answer ttC1,
A capacitance tCo is formed between the floating gate' electrode 6 and the substrate 1, respectively. These two capacitances CI and Co are isometrically connected in series between the control gate 11L pole 5 and the substrate 1. Therefore, when a voltage Vp is applied between the control gate electrode 5 and the substrate J, this applied voltage vp is divided according to the inverse ratio of the two capacitances tc] and CO, and this divided voltage [VpCo/( Co+C1)'
:] is applied to the floating gate electrode 6. When this divided voltage CVpCo/(Co+CI)] reaches a certain level, charges are injected and stored in the floating gate electrode 6 due to the so-called tunnel effect, and writing is performed. In the semiconductor memory device described above, in order to increase its write efficiency, it is necessary to make the divided voltage [VpCo/(Co+C1)] applied to the floating gate electrode 6 as high as possible. This divided voltage [VpCo/
(Co+CI) ], the 7°-ting gate is
The relative magnitude of o or C. It is necessary to make /C1 as small as possible, and for this purpose it is necessary to increase the distance do between the floating gate electrode 6 and the stripes. However, if the distance do is increased, the tunnel barrier between the floating gate electrode 6 and the substrate 1 becomes higher, making it difficult to inject charges into the floating gate 1 [electrode 6] due to the tunnel effect. The inventors of the present invention have found that this contradictory problem arises. As one of the means to solve the above-mentioned problems, for example, published by Nikkei McGraw-Hill [Nikkei Electronics 1985
As described in Figure 9.10 (memory cell structure of EEPROM) on page 152, page 153 of the October 21, 2015 issue (Zui 360), a part of the floating gate electrode 6 has a convex portion protruding toward the substrate 1 side. and by this convex part,
There is a technique for making it easier to inject charge into the floating gate' direct pole 6 while keeping the capacitance '%Co relatively small. However, in semiconductor memory devices that are highly microfabricated to have a storage capacity of more than 256 bits or IM pits, for example, the dimensions of the convex portions are so small that they exceed the limits of machining accuracy. Therefore, it has become difficult to form convex portions with good reproducibility that can reliably lower the tunnel barrier to a predetermined height.
The inventors have found that another problem arises in that the inlay conditions for each individual memory element tend to vary. [Object of the Invention] An object of the present invention is to secure a high divided voltage to be applied to the floating gate electrode, and to create a tunnel barrier between the floating gate electrode and the substrate without depending greatly on processing accuracy. A semiconductor memory device in which K can be lowered to a predetermined height with good reproducibility, thereby reliably increasing write efficiency and reducing variations in write conditions for individual memory elements. The goal is to provide technology. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Summary of the Invention] Representative inventions disclosed in this application are briefly explained below. That is, by providing a step in the first insulating film interposed between the floating gate electrode and the substrate, a thick part and a small part are formed in the first insulating film, and the thin part is used as the channel. The structure in which the floating gate electrode is arranged in a portion spanning from the region to the drain region and is bent in a stepped manner along the upper surface of the first insulating film makes it possible to reduce the gap between the floating gate electrode and the substrate. By making the capacitance of
While ensuring a high voltage that is divided and applied to the floating gate electrode, the tunnel barrier between the floating gate electrode and the substrate can be lowered to a predetermined height with good reproducibility without relying heavily on processing accuracy. This achieves the purpose of reliably increasing write efficiency and reducing variations in write conditions for individual memory elements. [Embodiments] Hereinafter, typical embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. FIGS. 1(a) and 1(b) show an embodiment of a main part of a semiconductor memory device to which the present invention is applied. The semiconductor memory device shown in the figure is formed as an EEPROM, and its memory element has a first insulating film on a channel region narrowed between an n+ drain region 4 and an n+ type source region 3, as described above. A floating gate electrode 6 is disposed via the floating gate electrode 2a, and a control gate electrode 5 is disposed on the floating gate electrode 6 via a second insulating film 7.
It is formed by arranging. First insulating film 2a
As such, a part of the oxide film 2 formed entirely on the surface of the p-type semiconductor substrate 10 is used. Further, as the second insulating film 7, a nitride film having a relatively high dielectric constant is used. Reference numeral 8 indicates a wiring electrode made of aluminum or the like. D represents a drain, and S represents a source. Writing of storage information in this EEFROM is performed by applying voltage Vp between control gate electrode 5 and substrate 1, as described above. That is, a capacitance C1 is formed between the control gate electrode 5 and the floating gate electrode 6, and a capacitance it Co is formed between the floating gate electrode 6 and the substrate 1, respectively. These two capacitances CI and C6 are connected to the control gate electrode 5.
and the substrate 1 are connected isometrically in series. Therefore, if a voltage Vp is applied between the control gate electrode 5 and the substrate, this applied voltage Vp will be applied to the two capacitances C1 and CO
The voltage is divided according to the inverse ratio of the voltage [VpCo/(
Co+CI)': l is the floating gate electrode 6
is applied to This divided voltage [VpCo/(Co+C1
)) exceeds a certain level, charges are injected and stored in the floating gate electrode 6 due to the so-called tunnel effect, and writing is performed. Here, in this embodiment, in addition to the above-described structure, by providing a step in the first insulating film 2a, the first insulating film 2a is provided with a step.
A thicker portion and a thinner portion are formed in the insulating film 2a, and the thinner portion is disposed in a portion extending from the channel region to the drain region 4. At the same time, the floating gate electrode 6 is bent in a stepped manner along the upper surface of the first insulating film 2a. As a result, the floating gate electrode 6 has a step portion 6C along the step shape of the first insulating film 2a, and a portion 6a with a large distance do from the substrate 1 on both sides of the step portion 6C, and a portion 6a with a large distance do from the substrate 1, and A portion 6b having a narrow d1 is formed in a divided manner. Due to the above structure, even if the distance d1 between the portion 6b and the substrate 1 is made small, by making the distance do between the portion 6a and the substrate 1 larger than a certain level, the floating gate

〔effect〕

(1) Floating Gate I! By providing a step in the first insulating film interposed between the pole and the substrate, a thick part and a small part are formed in the first insulating film,
The structure in which the floating gate electrode is bent in a stepped manner along the upper surface of the first insulating film is formed by disposing the thinner part in the part extending from the channel region to the drain region. - By making the electrostatic capacitance between the floating gate electrode and the substrate relatively small and ensuring a high voltage that is divided and applied to one pole of the floating gate, the capacitance between the floating gate electrode and the substrate is It is now possible to reproducibly lower the tunnel barrier between the two to a predetermined height without relying heavily on processing accuracy, thereby reliably increasing writing efficiency and reducing the variation in writing conditions for individual memory elements. This has the effect of making it possible to make it smaller. Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the second insulating film 7 may be an oxide film. [Field of Application] Above, we have explained the case in which the invention made by the present inventor is applied to the EEPROM technology, which is the field of application that forms the background of the invention, but it is not limited thereto. random·
K, such as access/memory technology, can also be applied. At least floating games)! It can be applied to conditions that have poles.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are cross-sectional views showing the main parts of a semiconductor memory device according to the present invention, and FIGS. 2(a) to (f) mainly illustrate an embodiment of a method for manufacturing a semiconductor memory device according to the present invention. FIGS. 3(a) and 3(b) are cross-sectional views partially showing an example of the structure of a semiconductor memory device prior to this invention. 1...p-type semiconductor substrate, 2...oxide film, 2a...
・First insulating film, 3... n+ type insulating region, 4...
n+ type drain region, 5... control gate electrode (PG)
, 6... floating gate electrode (FG), 6c.
...Stepped portion, 7...Second IIA membrane. Figure 2 (eft)

Claims (1)

[Claims] 1. A floating gate electrode is provided on the channel region narrowed between the drain region and the source region via a first insulating film, and a second
A semiconductor memory device in which a control gate electrode is disposed through an insulating film, wherein a step is provided in the first insulating film, and the step allows the first insulating film to have a thick portion. The floating gate electrode is bent in a step shape along the upper surface shape of the first insulating film. A semiconductor memory device characterized in that: 2. The semiconductor memory device according to claim 1, wherein the control gate electrode and the second insulating film are bent in parallel to the floating gate electrode so as to maintain the same spacing. .