JPS62122236A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62122236A JPS62122236A JP60261130A JP26113085A JPS62122236A JP S62122236 A JPS62122236 A JP S62122236A JP 60261130 A JP60261130 A JP 60261130A JP 26113085 A JP26113085 A JP 26113085A JP S62122236 A JPS62122236 A JP S62122236A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- outer end
- film
- pad
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特にドライエッチ法で加工された
アルミニウム（Ａで）を用いた電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to an electrode structure using aluminum (A) processed by a dry etching method.
ＩＣやトランジスタなどの半導体装置のＡｐ電極形成法
において、加工寸法の微細化に伴い、従来のウェットエ
ッチ法に代ってドライエッチ法が多く採用されている。BACKGROUND ART In methods for forming Ap electrodes of semiconductor devices such as ICs and transistors, a dry etching method is often used instead of a conventional wet etching method as processing dimensions become smaller.
このドライエッチ法は７レオンＣＦ４ガス等を用いリア
クティブ・イオン・エツチング（ＲＩＥ）技術を用いて
行なうことにより基板面に垂直方向にエッチし、このエ
ツチングされるＡ１膜の側面が垂直になる。このように
エッチされたＡβ膜の上にＣＶＤ（化学的気相堆積）法
により無機絶縁膜を形成した場合、ＡＡ膜による段差を
充分にカハーシきれず、オーバーハングを生じることが
知られている。そのことが「日経マグロウヒル社発行ｒ
ＮＩＫＫＥＩ ＭＩＣＲＯ−ＤＥＶＩＣＥ８１９８５年
９月号ｊｐ、ｓｓに記載されている。This dry etching method is performed using reactive ion etching (RIE) technology using 7 Leon CF4 gas or the like to etch in a direction perpendicular to the substrate surface, and the side surfaces of the A1 film to be etched become vertical. It is known that when an inorganic insulating film is formed by CVD (chemical vapor deposition) on an Aβ film that has been etched in this way, the steps caused by the AA film cannot be sufficiently covered, resulting in overhang. . That is why "Published by Nikkei McGraw-Hill"
It is described in NIKKEI MICRO-DEVICE 8 September 1985 issue jp, ss.
第５図は単体トランジスタの電極部構造の一例を示す平
面図である。FIG. 5 is a plan view showing an example of the electrode structure of a single transistor.
１はトランジスタのエミッタ又はベースとオーミックコ
ンタクトするＡ２電極部分であり、２は；Ｃ＋７） Ａ
Ａ ［極を延長した外端部でワイヤボンデイングパッ
ドとなる部分である。３はＡｎ配線部でトランジスタ側
と外端部とを連結する。これらＡｌ電極部は第６図（第
５図のＢ−Ｂ視断面図）下地の第１のバッフベイジョン
膜（一般に熱酸化５ｉｆｔからなる）４の上に形成され
、ＡＡ［極の上はＣＶＤ−ＰＳＧ（リンシリケートガラ
ス）等の第２のパッシベーション膜５で覆われ、Ａ９電
極の外端部２上面及び側面が露出するようにスルーホー
ル６が形成される。このように外端部２の上をスルーホ
ールにより絶縁膜５で覆わない理由は、ワイヤボンディ
ングの際のポンディビリティの低下を防ぐこと及び、バ
ットを小寸法として絶縁膜とＡｌ膜とによるＭＯ８容量
を小さくし、それにより高周波特性を改善することにあ
る。第２のパッシベーションＫＰＳＧを使用するのはＰ
ＳＧはＣＶＤ法により低温（４００ｔ：’前後）で成長
させることができ、この温度ではＡａ電極が溶融するこ
となく、Ａｋピットの発生を防止できるためである。1 is the A2 electrode part that makes ohmic contact with the emitter or base of the transistor, and 2 is; C+7) A
A [This is the outer end of the extended pole that becomes the wire bonding pad. Reference numeral 3 denotes an An wiring portion that connects the transistor side and the outer end. These Al electrode parts are formed on the underlying first buff basin film (generally made of thermally oxidized 5ift) 4 as shown in FIG. It is covered with a second passivation film 5 such as CVD-PSG (phosphosilicate glass), and a through hole 6 is formed so that the top and side surfaces of the outer end 2 of the A9 electrode are exposed. The reason why the top of the outer end 2 is not covered with the insulating film 5 through a through hole is to prevent deterioration of the pondability during wire bonding, and to reduce the size of the butt so that the MO8 due to the insulating film and the Al film is not covered. The objective is to reduce the capacitance and thereby improve high frequency characteristics. The second passivation KPSG is used by P
This is because SG can be grown at a low temperature (around 400 t:') by the CVD method, and at this temperature, the Aa electrode does not melt and the generation of Ak pits can be prevented.
ところでドライエッチされたＡＡ電極の配線部は第７図
（第６図Ｃ−Ｃ視断面図）に示されるように、第２のパ
ッシベーション膜５により覆わｊ。By the way, the wiring portion of the dry-etched AA electrode is covered with a second passivation film 5, as shown in FIG. 7 (cross-sectional view taken along line CC in FIG. 6).
るが、前記したようにこの部分のＡ１段差でオーバーハ
ングを生じ、急峻なＡＥ電極側面にそって空洞部１１を
生じることが多いことがわかった。However, as described above, it has been found that overhang occurs at the A1 level difference in this portion, and a cavity 11 is often formed along the steep side surface of the AE electrode.
このため、第２パツシベーシプン膜５をウェットエッチ
によりエッチ加工してスルーホール６を形成する工程で
、上記空洞部をエッチトンネル、（通路）に成長させ、
このトンネル内にエッチ液が残存し、細線部３０Ａｋ膜
を腐食し、断線不良等の原因になることがあきらかとさ
れた。For this reason, in the step of etching the second passivation film 5 by wet etching to form the through hole 6, the cavity is grown into an etch tunnel (passage).
It has been found that the etchant remains in this tunnel and corrodes the thin wire portion 30Ak film, causing disconnection and other defects.
本発明は上記した問題を克服するためになされたもので
あり、その目的は上記したエッチトンネルの成長を阻止
し、ｌｔＷ極の信頼度を向上することにある。The present invention has been made to overcome the above-mentioned problems, and its purpose is to prevent the growth of the above-mentioned etch tunnels and improve the reliability of the ltW pole.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面から明らかＫなろう。The above and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基体上で素子に接続するへβ電極を覆
って絶縁膜が形成され、この絶縁膜の一部が開口して上
記Ａｌ電極の外端部の上面及び側面が露出する半導体装
置であって、王妃外端を素子との間のＡｌ電極（配線）
の一部に側面方向へ突出する突出部乃至屈曲部を形成す
ることにより、その部分をストッパとして上記Ａ杉電極
に沿ったエッチトンネルの成長を阻止し、ＡＥ電極構造
の信頼性を向上して前記目的を達成するものである。That is, in a semiconductor device, an insulating film is formed on a semiconductor substrate to cover a β electrode connected to an element, and a part of this insulating film is opened to expose the upper surface and side surface of the outer end of the Al electrode. Al electrode (wiring) between the outer end of the queen and the element
By forming a protruding part or a bent part that protrudes in the side direction in a part of the AE electrode, this part can be used as a stopper to prevent the growth of an etch tunnel along the A cedar electrode, thereby improving the reliability of the AE electrode structure. This achieves the above objective.
第１図は本発明の一実施例を示すものであって、単体ト
ランジスタにおけるコレクタ（又はエミッタ）電極の平
面図である。FIG. 1 shows one embodiment of the present invention, and is a plan view of a collector (or emitter) electrode in a single transistor.
第２図は第１図におけるＡ −Ａ視縦断面図である。FIG. 2 is a longitudinal sectional view taken along line A-A in FIG. 1.
同図において前記した従来例（第５図〜第７図）と共通
な構成部分に対しては同一の指示番号が使用されている
。In the same figure, the same reference numbers are used for components common to those of the conventional example (FIGS. 5 to 7) described above.
第２図において、８は半導体チップ（Ｓｉ基板）、９は
基板表面に選択拡散により形成した素子、たとえばトラ
ンジスタのエミッタ領域である。４は基板表面に熱酸化
により形成されたフィールド８１０２膜でＡｌ電極の下
地となる部分である。In FIG. 2, 8 is a semiconductor chip (Si substrate), and 9 is an element formed on the surface of the substrate by selective diffusion, such as an emitter region of a transistor. Reference numeral 4 denotes a field 8102 film formed on the substrate surface by thermal oxidation, which serves as a base for the Al electrode.
エミッタ領域９にはＡＡ電極１がオーミックコンタクト
し、上記フィールド５ｉｆｔ膜４上に延在してその外端
部２はポンディングパッドとして第１図に示すようにそ
のパターンは円形状である。An AA electrode 1 is in ohmic contact with the emitter region 9, extends over the field 5ift film 4, and its outer end 2 serves as a bonding pad and has a circular pattern as shown in FIG.
Ａｌ電極１と外端部２との間を接続する配線部３の一部
は左右側面方向に突出するようにたとえば十字状の突出
部７が形成される。（第２ａ図参照）
ＡＡ電極１の上を覆ってＰＳＧ膜５がパッシベーション
として形成される。このＰＳＧ膜５には上記ＡＡ電極の
外端部（バンド）の上面及び側面が露出するようにパッ
ドよりも広いパターンでスルーホール５が形成される。A portion of the wiring portion 3 connecting the Al electrode 1 and the outer end portion 2 is formed with, for example, a cross-shaped protrusion 7 so as to protrude in the left and right side directions. (See FIG. 2a) A PSG film 5 is formed covering the AA electrode 1 as passivation. A through hole 5 is formed in this PSG film 5 in a pattern wider than the pad so that the upper and side surfaces of the outer end (band) of the AA electrode are exposed.
上記パッド上面にボンディングされたワ、イヤーボール
１２が点線で示される。The ear ball 12 bonded to the upper surface of the pad is shown in dotted lines.
絶縁膜で覆われたＡＥ配線の一部に横方向に突出する突
出部を設けることにより、絶縁膜とＡＡ配線の側面との
間に空洞部が存在する場合にも。By providing a protrusion that protrudes laterally in a part of the AE wiring covered with the insulating film, even when a cavity exists between the insulating film and the side surface of the AA wiring.
ＡＩ３配線の側面が屈曲することにより距離が長くなり
、それＫよってエッチ後の流水洗浄で洗浄残りの発生し
易い空洞の成長が緩和され、ストッパとしての作用をも
つことになる。The bending of the side surface of the AI3 wiring lengthens the distance, which alleviates the growth of cavities that tend to leave cleaning residue during washing with running water after etching, and acts as a stopper.
このようなストッパ作用によるエッチ液等の残存がない
ことにより、Ａ！腐融等が阻止され、製品の信頼性が向
上する。Because there is no residual etchant etc. due to this stopper action, A! Corrosion, etc. is prevented and product reliability is improved.
本発明はＡ４膜より電極形成のためにエッチする際Ｋ、
パターンを変えるのみで工程を変えることなく、実現す
ることができる。In the present invention, when etching an A4 film for electrode formation, K,
This can be achieved without changing the process by simply changing the pattern.
以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
である。Although the invention made by the present invention has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.
たとえば、ＡＢ配線の一部に設けるストッパの形状は、
第３図に示すように突出部をＸ印形状に形成し、あるい
は、第４図に示すようにＡ召配線の内側に切り込み９を
つくることにより屈曲させた形状としてもよい。For example, the shape of a stopper provided on a part of AB wiring is
As shown in FIG. 3, the protrusion may be formed in the shape of an X mark, or as shown in FIG. 4, it may be bent by making a notch 9 inside the A lead wire.
本発明はＡｐ電極を有する半導体装置（単体トランジス
タ、ＩＣ）一般に応用できる。The present invention can be generally applied to semiconductor devices (single transistors, ICs) having Ap electrodes.
本発明は特に第２パンシベーシ３ンか２層（プラズマＳ
ｉ Ｎ＋Ｐ Ｓ Ｇ ）で下地（第１パツシベーシヨ
ン）がＣＶＤ系膜、ステップカバレージの悪い膜で上の
膜がＣＶＤのエッチ液圧よりエッチされることのない膜
を使用する場合の半導体装置に適用するとき最も効果を
有する。The present invention is particularly suitable for the second pansy
Applicable to semiconductor devices in which the base (first passivation) is a CVD film, the upper film is a film with poor step coverage, and is not etched by the CVD etch liquid pressure. It is most effective when
第１図は本発明の一実施例を示す半導体装置電極部の平
面図である。
第２図は第１図におけるＡ−Ａ視縦断面図である。
第３図、第４図は本発明による変形例を示すｌｉ！配線
部の一部平面図である。
第５図はこれまでの半導体装置電極部の一例を示す平面
図である。
第６図は第５図におけるＢ−Ｂ視断面図、第７図は同じ
＜Ｃ−Ｃ視断面図である。
１・・・エミッタ（ペース）と接続するＡｎ電極、２・
・・ＡＡ電電極端端部パッド）、３・・・ＡＡＡ極配線
部、４・・・下地絶縁膜（ＳｉＯｘ膜）、５・・・保護
絶縁膜、６・・・スルーホール、７・・・突出部、８・
・・半導体基板、９・・・素子、１０・・・切り込み部
、１１・・・空洞部。
代理人 弁理士 小 川 勝 男
第 １ 図
二４FIG. 1 is a plan view of an electrode portion of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a longitudinal sectional view taken along the line AA in FIG. 1. FIGS. 3 and 4 show variations according to the present invention! FIG. 3 is a partial plan view of the wiring section. FIG. 5 is a plan view showing an example of an electrode section of a conventional semiconductor device. FIG. 6 is a sectional view taken along the line BB in FIG. 5, and FIG. 7 is a sectional view taken along the line <CC in FIG. 1... An electrode connected to the emitter (pace), 2.
...AA electrode end pad), 3...AAA electrode wiring part, 4...base insulating film (SiOx film), 5...protective insulating film, 6...through hole, 7... Projection, 8.
...Semiconductor substrate, 9...Element, 10...Notch, 11...Cavity. Agent: Patent Attorney Katsoo Ogawa No. 1 Figure 24
Claims (1)
体の上記素子に配線電極が接続され、この配線電極を覆
って保護用絶縁膜が形成され、この保護用絶縁膜の一部
が開口して上記配線電極の延在部の上面及び側面が露出
する半導体装置であって、上記外端部と素子との間の配
線電極の一部に側面方向へ突出する突出部乃至屈曲部が
形成されていることを特徴とする半導体装置。 ２、上記配線電極は基板にに対し直角又は直角に近い側
面を有する特許請求の範囲第１項に記載の半導体装置。[Claims] 1. A wiring electrode is connected to the element of a semiconductor substrate in which a semiconductor element is formed on a part of one main surface, a protective insulating film is formed covering the wiring electrode, and a protective insulating film is formed to cover the wiring electrode. A semiconductor device in which a part of the insulating film is opened to expose an upper surface and a side surface of the extending portion of the wiring electrode, the part of the wiring electrode between the outer end portion and the element protruding in the side direction. A semiconductor device characterized in that a protruding portion or a bent portion is formed. 2. The semiconductor device according to claim 1, wherein the wiring electrode has a side surface that is perpendicular or nearly perpendicular to the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60261130A JPS62122236A (en) | 1985-11-22 | 1985-11-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60261130A JPS62122236A (en) | 1985-11-22 | 1985-11-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62122236A true JPS62122236A (en) | 1987-06-03 |
Family
ID=17357509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60261130A Pending JPS62122236A (en) | 1985-11-22 | 1985-11-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62122236A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100517496B1 (en) * | 2002-01-04 | 2005-09-28 | 삼성전자주식회사 | Cantilever having step-up structure and method for manufacturing the same |
| US9851011B2 (en) | 2014-06-02 | 2017-12-26 | Mactaggart Scott (Holdings) Limited | Snorkel valve |
-
1985
- 1985-11-22 JP JP60261130A patent/JPS62122236A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100517496B1 (en) * | 2002-01-04 | 2005-09-28 | 삼성전자주식회사 | Cantilever having step-up structure and method for manufacturing the same |
| US9851011B2 (en) | 2014-06-02 | 2017-12-26 | Mactaggart Scott (Holdings) Limited | Snorkel valve |
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