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JPS62125670A - Manufacture of bipolar transistor - Google Patents

Manufacture of bipolar transistor

Info

Publication number
JPS62125670A
JPS62125670A JP26648285A JP26648285A JPS62125670A JP S62125670 A JPS62125670 A JP S62125670A JP 26648285 A JP26648285 A JP 26648285A JP 26648285 A JP26648285 A JP 26648285A JP S62125670 A JPS62125670 A JP S62125670A
Authority
JP
Japan
Prior art keywords
region
base region
conductivity type
polysilicon film
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26648285A
Other languages
Japanese (ja)
Inventor
Kazufumi Mitsumoto
三本 和文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP26648285A priority Critical patent/JPS62125670A/en
Publication of JPS62125670A publication Critical patent/JPS62125670A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To improve high frequency characteristic and noise characteristic by implanting first conductivity type impurity from a polysilicon film into a predetermined region by removing a mask layer to form an emitter region. CONSTITUTION:A second conductivity type impurity is implanted to the surface of a first conductivity type semiconductor substrate 11 to form a base region 13, while the base region is covered with a polysilicon film 14, and the polysilicon film on the predetermined region in the base region is covered with a mask layer 15 wider than the predetermined region. Then, the polysilicon film is isotropically etched to expose a base region surface except the predetermined region, the mask layer is formed in overhang state, second conductivity type impurity is implanted to the exposed base region except the base region under the mask layer to form a graft base region 17. Thereafter, the mask layer is removed, the first conductivity type impurity is implanted from the polysilicon film into the predetermined region to form an emitter region 18. Thus, the regions 17, 18 are not superposed to obtain a preferable high frequency characteristic and noise resistance.

Description

【発明の詳細な説明】 〈産業」−の利用分野〉 本発明はバイポーラトランジスタ装置の製造方法に係わ
り、特に、グラフトベース領域とエミッタ領域とを自己
整合的に形成するバイポーラトランジスタ装置の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Field of Application in Industry> The present invention relates to a method for manufacturing a bipolar transistor device, and particularly relates to a method for manufacturing a bipolar transistor device in which a graft base region and an emitter region are formed in a self-aligned manner. .

〈従来の技術〉 第2図(a)乃至(e)は従来のバイポーラトランジス
タ装置の製造方法の各工程を示す断面図であり、該製造
方法においては、まず、n型の半導体基板1の表面を熱
酸化して二酸化シリコン膜2を成長させる(第2図(a
))。続いて、ホトエツチングにより二酸化シリコン膜
2を選択的に除去し、グラフトベース形成予定領域を露
出させる。このグラフトベース形成予定領域にp型の不
純物を導入してグラフトベース領域3を形成する(第2
図(b))。この後、ホトレジスト工程を経て二酸化シ
リコン膜2を選択的に除去し、ベース形成予定領域を露
出させ、n型の不純物を導入してベース領域4を形成す
る(第2図(C))。
<Prior Art> FIGS. 2(a) to 2(e) are cross-sectional views showing each step of a conventional method for manufacturing a bipolar transistor device. is thermally oxidized to grow a silicon dioxide film 2 (see Fig. 2(a)
)). Subsequently, the silicon dioxide film 2 is selectively removed by photoetching to expose the region where the graft base is to be formed. A p-type impurity is introduced into this region where the graft base is to be formed to form the graft base region 3 (second
Figure (b)). Thereafter, the silicon dioxide film 2 is selectively removed through a photoresist process to expose a region where a base is to be formed, and an n-type impurity is introduced to form a base region 4 (FIG. 2(C)).

ベース領域4の形成工程が終了すると、1へ導体基板1
の表面は再び二酸化シリコン膜2で被われるので、ホト
レジス1〜工程により二酸化シリコン膜2を選択的に除
去してベース領域4中のエミッタ形成予定領域を露出さ
せ、該エミッタ形成予定領域を電極突き抜は防止用のポ
リシリコン膜5で被う(第2図(d))。続く工程では
エミッタ形成予定領域にn型の不純物を導入してエミッ
タ領域6を形成しく第2図(e))、以後標準的な工程
を経てバイポーラ1ヘランジスタ装置が完成する。
When the step of forming the base region 4 is completed, the conductor substrate 1 is transferred to the base region 1.
Since the surface of is again covered with the silicon dioxide film 2, the silicon dioxide film 2 is selectively removed in the photoresist step 1 to expose the area where the emitter is to be formed in the base region 4, and the area where the emitter is to be formed is covered with an electrode. It is covered with a polysilicon film 5 to prevent removal (FIG. 2(d)). In the next step, n-type impurities are introduced into the region where the emitter is to be formed to form the emitter region 6 (FIG. 2(e)), and the bipolar one helangister device is completed through standard steps.

〈発明の解決しようとする問題点〉 上記従来の製造方法では、グラフトベース領域3の形成
とベース領域4の形成とエミッタ領域6の形成とが互い
に何等関係のない独立したホ)−レジスト工程を経て形
成されていたので、マスク合せの誤差により第73図に
示されているようにエミッタ領域6の一部が高不純物濃
度のグラフトベース領域3内に及ぶ恐れがあり、この場
合、ベース・エミッタ間のキャパシタンスが大きくなる
ことと、エミッタ注入効率のバランスがくずれることに
より、バイポーラトランジスタ装置の高周波特性が悪化
するという欠点がある。かかるグラフI−ベース領域3
とエミッタ領域6との重なりを防止するためグラフトベ
ース領域の内周とエミッタ領域の外周との間隔を大きく
とらざるを得なかった。
<Problems to be Solved by the Invention> In the above conventional manufacturing method, the formation of the graft base region 3, the formation of the base region 4, and the formation of the emitter region 6 are performed in independent resist steps that have no relation to each other. Since the emitter region 6 was formed over a long period of time, there is a risk that a part of the emitter region 6 may extend into the graft base region 3 with a high impurity concentration due to an error in mask alignment, as shown in FIG. There is a drawback that the high frequency characteristics of the bipolar transistor device deteriorate due to an increase in the capacitance between the two and an imbalance in emitter injection efficiency. Such graph I - base region 3
In order to prevent overlap between the graft base region and the emitter region 6, it is necessary to provide a large distance between the inner circumference of the graft base region and the outer circumference of the emitter region.

一般にバイポーラトランジスタ装置のベース抵抗Rb 
b ’は、 Rbb’ = (ρ、WE/12L+ρ、S、/2L十
ρ3S 2 / 2 T−) / rnと表わされる。
Generally, the base resistance Rb of a bipolar transistor device
b' is expressed as Rbb' = (ρ, WE/12L+ρ, S, /2L + ρ3S 2 / 2 T-) / rn.

ここで、ρ3.ρ2.ρ3は比抵抗、WEはエミッタ領
域6の幅、S、、S2はそれぞれグラフトベース領域の
外周とエミッタ領域の外周との間隔と、グラフ1−ベー
ス領域の内周とベース電極の内周との間隔、■7は]一
本のエミy夕電極の長さ、mはベース電極の数を表わし
ている。従って、グラフトベース領域3とエミッタ領域
6との重なりを防止するためグラフ1〜ベース領域;3
の内周とエミッタ領域の外周との間隔を大きくすると、
Slが大きくなり、この領域はグラフトベース領域3よ
りも比抵抗が大きいこともあって、ベース抵抗Rbb’
の増大を招く。その結果、バイポーラトランジスタ装置
の高周波特性とノイズ特性とを悪化させるという問題点
があった。従って、マスク合せ誤差による不都合を避け
るにはベース抵抗の増大による高周波特性の低下を避け
ることができなかった。
Here, ρ3. ρ2. ρ3 is the specific resistance, WE is the width of the emitter region 6, S, and S2 are the distance between the outer circumference of the graft base region and the outer circumference of the emitter region, and graph 1 - the distance between the inner circumference of the base region and the inner circumference of the base electrode, respectively. The interval, 7, is the length of one emitter electrode, and m is the number of base electrodes. Therefore, in order to prevent the graft base region 3 and the emitter region 6 from overlapping, graph 1 to base region;
By increasing the distance between the inner circumference of the emitter region and the outer circumference of the emitter region,
As Sl increases and this region has a higher specific resistance than the graft base region 3, the base resistance Rbb'
leading to an increase in As a result, there has been a problem in that the high frequency characteristics and noise characteristics of the bipolar transistor device are deteriorated. Therefore, in order to avoid inconveniences due to mask alignment errors, it has been impossible to avoid deterioration of high frequency characteristics due to an increase in base resistance.

従って、本発明はグラフ1〜ベース領域とエミッタ領域
との自己整合を可能にし、グラフトベース領域の内周と
エミッタ領域の外周との間隔を可及的に小さく設定でき
るようにして、高周波特性とノイズ特性に優れたバイポ
ーラトランジスタ装置の製造方法を提供することを目的
にしている。
Therefore, the present invention enables self-alignment between the base region and the emitter region as shown in graph 1, and enables the interval between the inner circumference of the graft base region and the outer circumference of the emitter region to be set as small as possible, thereby improving high frequency characteristics. The purpose of this invention is to provide a method for manufacturing a bipolar transistor device with excellent noise characteristics.

〈問題点を解決するための手段〉 本発明は、第1導電型の半導体基板の表面部に第2導電
型の不純物を導入してベース領域を形成し、該ベース領
域の表面を第1導電型の不純物を含むポリシリコン膜で
被った後、ベース領域内の所定領域上の前記ボリシ゛リ
コン膜を前記所定領域より広いマスク層で被う。続いて
、前記ポリシリコン膜を等方的にエツチングし前記所定
領域外のベース領域表面を露出させると共に前記マスク
層をオーバーハング状態にし、前記マスク層下のベース
領域を除く露出したベース領域に第2導電型の不純物を
導入しグラフトベース領域を形成する。
<Means for Solving the Problems> The present invention involves introducing impurities of a second conductivity type into the surface of a semiconductor substrate of a first conductivity type to form a base region, and converting the surface of the base region into a first conductivity type. After covering with a polysilicon film containing type impurities, the polysilicon film on a predetermined region in the base region is covered with a mask layer that is wider than the predetermined region. Subsequently, the polysilicon film is isotropically etched to expose the surface of the base region outside the predetermined region, the mask layer is left in an overhanging state, and etching is performed on the exposed base region except for the base region under the mask layer. A graft base region is formed by introducing impurities of two conductivity types.

この後、前記マスク層を除去し該所定領域内に第1導電
型の不純物を前記ポリシリコン膜から導入してエミッタ
領域を形成することを要旨とする。
Thereafter, the mask layer is removed and a first conductivity type impurity is introduced from the polysilicon film into the predetermined region to form an emitter region.

〈実施例〉 第1図(a)乃至(e)は本発明の第1実施例の各工程
を示す断面図であり、NPN形バイポーラ1〜ランジス
タの場合について説明しである。まず、n型の半導体基
板11の表面を熱酸化して二酸化シリコン膜12を約5
000人成長させる(第1図(a))。続いて、ホトエ
ンチングによりベース形成予定領域を露出させ、ボロン
を1013乃至〕014注入する。この後、窒素雰囲気
中で約900℃で約30分間加熱し、深さ約0.15乃
至0.2μrnのベース領域】3を形成する(第1図(
b))。この後、露出している半導体基板11の表面と
二酸化シリコンIIIX+12とを被うP型のドープト
ポリシリコン11% ] 4を約5000人波着し、さ
らに窒化シリコン膜154約2000人被着する(第1
図(c))。窒化シリコン膜15の上にホトレジスト膜
]−6を塗布し、これをパターン形成してベース領域】
−73中の所定領域をホトレジスト膜】−(3で被う。
<Embodiment> FIGS. 1(a) to 1(e) are cross-sectional views showing each step of a first embodiment of the present invention, and explain the cases of NPN type bipolar 1 to transistor. First, the surface of the n-type semiconductor substrate 11 is thermally oxidized to form a silicon dioxide film 12 of about 50%
000 people (Figure 1 (a)). Subsequently, the region where the base is to be formed is exposed by photo-etching, and 1013 to 014 boron is implanted. Thereafter, heating is performed at approximately 900° C. for approximately 30 minutes in a nitrogen atmosphere to form a base region 3 with a depth of approximately 0.15 to 0.2 μrn (see Fig. 1).
b)). After this, approximately 5,000 layers of P-type doped polysilicon (11%) 4 to cover the exposed surface of the semiconductor substrate 11 and silicon dioxide IIIX+12 are deposited, and approximately 2,000 layers of silicon nitride film 154 is further deposited. (1st
Figure (c)). A photoresist film ]-6 is applied on the silicon nitride film 15 and patterned to form a base region]
- Cover a predetermined area in 73 with a photoresist film]-(3.

この後、ホトレジスト膜16をマスクとして窒化シリコ
ン膜15を選択的に除去し、露出したポリシリコン膜1
4を等方的にエツチングする。こうした等方性エツチン
グの結果、窒化シリコン膜1−5の下のポリシリコンI
I*14も窒化シリコン膜15の外周から約50o。
Thereafter, the silicon nitride film 15 is selectively removed using the photoresist film 16 as a mask, and the exposed polysilicon film 1
4 isotropically etched. As a result of such isotropic etching, the polysilicon I under the silicon nitride film 1-5 is removed.
I*14 is also approximately 50o from the outer periphery of the silicon nitride film 15.

λ程度内方にエツチングされる。続いて、ホトレジスト
膜16をマスクとして約60keyでボロンをイオン注
入し、半導体基板]1のグラフトベース形成予定領域を
規定する(第1図(d))。
It is etched inward by about λ. Next, using the photoresist film 16 as a mask, boron ions are implanted in approximately 60 keys to define a region of the semiconductor substrate 1 where a graft base is to be formed (FIG. 1(d)).

ホトレジスト膜]−6を除去した後、約800乃至90
0″Cの酸化雰囲気中で加熱してグラフI−ベース領域
17を形成すると共にドープ1−ポリシリコン膜14か
らn型の不純物、例えば、燐を半導体基板]−1に拡散
しエミッタ領域18を形成する。
After removing photoresist film]-6, approximately 800 to 90
The base region 17 is formed by heating in an oxidizing atmosphere of 0"C, and an n-type impurity, such as phosphorus, is diffused from the doped polysilicon film 14 into the semiconductor substrate ]-1 to form the emitter region 18. Form.

この間、半導体基板11の表面は酸化され二酸化シリコ
ン膜で被われる(第1図(e))。以後、電極が形成さ
れてバイポーラトランジスタ装置が完成される。
During this time, the surface of the semiconductor substrate 11 is oxidized and covered with a silicon dioxide film (FIG. 1(e)). Thereafter, electrodes are formed to complete the bipolar transistor device.

このようにグラフトベース領域17とエミッタ領域】−
8との間隔はポリシリコン膜1−7′1の膜厚に対応し
て定まるので、グラフ1〜ベース領域]−7の外周とエ
ミッタ領域18の外周との間隔S1を正確に制御できる
。しかも、エミッタ領域18はマスク層15の丁の半導
体基板]−1の内方に、グラフ1〜ベース領域]7はそ
の外方にそれぞれ形成され、互いが重なり合うことがな
い。従って、従来例のようにマスク合せの誤差を見越し
て間隔S。
In this way, the graft base region 17 and the emitter region】-
8 is determined in accordance with the thickness of the polysilicon film 1-7'1, so that the distance S1 between the outer periphery of graph 1-base region]-7 and the outer periphery of emitter region 18 can be accurately controlled. Moreover, the emitter region 18 is formed inside the semiconductor substrate 1-1 of the mask layer 15, and the base regions 1-7 are formed outside thereof, so that they do not overlap with each other. Therefore, as in the conventional example, the interval S is set in anticipation of errors in mask alignment.

を大きく定める必要がなくなり、間隔S1を減少させる
ことにより、バイポーラトランジスタ装置の高周波特性
と、ノイズ特性とを向上させることができる。
It is no longer necessary to set a large distance, and by reducing the interval S1, the high frequency characteristics and noise characteristics of the bipolar transistor device can be improved.

〈効果〉 以1―説明してきたように、この発明によれば、マスク
層に被われたベース形成予定領域の所定領域外にグラフ
トベース領域を、所定領域内にエミッタ領域をそれぞれ
形成したので、グラフトベース領域とエミッタ領域とが
重なる事がなく、良好な高周波特性とノイズ特性とを有
するバイポーラトランジスタ装置が得られる。
<Effects> As described in 1 above, according to the present invention, the graft base region is formed outside the predetermined region of the base formation planned region covered by the mask layer, and the emitter region is formed within the predetermined region. The graft base region and the emitter region do not overlap, and a bipolar transistor device having good high frequency characteristics and noise characteristics can be obtained.

【図面の簡単な説明】 第1−図(a)乃至(e)は本発明の−・実施例の各工
程を表わす断面図、第2図(a)乃至(e)は従来例の
各工程を表わす断面図、第3図は従来例の問題点を説明
する断面図である。 1]−・・・・・・・半導体基板、 13・・・・・・・ベース領域、 ]4・・・・・・・ポリシリコン膜。 ]−5・・・・・・・マスク層、 17・・・・・・・グラフ1〜ベース領域、18・・・
・・・・エミッタ領域。 特許出願人      ローム株式会社代理人   弁
理士  桑 井 清 −(b) (C) 第1図 (C1) 第1図 (q) (b) (C) 第2図 (cl) (e) 第Z図
[BRIEF DESCRIPTION OF THE DRAWINGS] Figures 1 (a) to (e) are sectional views showing each process of the embodiment of the present invention, and Figures 2 (a) to (e) are each process of the conventional example. FIG. 3 is a cross-sectional view illustrating the problems of the conventional example. 1] -... Semiconductor substrate, 13... Base region, ]4... Polysilicon film. ]-5...Mask layer, 17...Graph 1 to base region, 18...
...Emitter area. Patent Applicant: ROHM Co., Ltd. Representative Patent Attorney Kiyoshi Kuwai - (b) (C) Figure 1 (C1) Figure 1 (q) (b) (C) Figure 2 (cl) (e) Figure Z

Claims (1)

【特許請求の範囲】[Claims] 第1導電型の半導体基板の表面部に第2導電型の不純物
を導入してベース領域を形成する工程と、該ベース領域
の表面を第1導電型の不純物を含むポリシリコン膜で被
う工程と、ベース領域内の所定領域上の前記ポリシリコ
ン膜を前記所定領域より広いマスク層で被う工程と、前
記ポリシリコン膜を等方的にエッチングし前記所定領域
外のベース領域表面を露出させると共に前記マスク層を
オーバーハング状態にする工程と、前記マスク層下のベ
ース領域を除く露出したベース領域に第2導電型の不純
物を導入しグラフトベース領域を形成する工程と、前記
マスク層を除去し該所定領域内に第1導電型の不純物を
前記ポリシリコン膜から導入してエミッタ領域を形成す
る工程とを有するバイポーラトランジスタ装置の製造方
法。
A step of introducing impurities of a second conductivity type into the surface of a semiconductor substrate of a first conductivity type to form a base region, and a step of covering the surface of the base region with a polysilicon film containing impurities of a first conductivity type. a step of covering the polysilicon film on a predetermined region in the base region with a mask layer wider than the predetermined region; and isotropically etching the polysilicon film to expose the surface of the base region outside the predetermined region. and forming a graft base region by introducing impurities of a second conductivity type into the exposed base region excluding the base region under the mask layer, and removing the mask layer. and forming an emitter region by introducing impurities of a first conductivity type into the predetermined region from the polysilicon film.
JP26648285A 1985-11-26 1985-11-26 Manufacture of bipolar transistor Pending JPS62125670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26648285A JPS62125670A (en) 1985-11-26 1985-11-26 Manufacture of bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26648285A JPS62125670A (en) 1985-11-26 1985-11-26 Manufacture of bipolar transistor

Publications (1)

Publication Number Publication Date
JPS62125670A true JPS62125670A (en) 1987-06-06

Family

ID=17431544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26648285A Pending JPS62125670A (en) 1985-11-26 1985-11-26 Manufacture of bipolar transistor

Country Status (1)

Country Link
JP (1) JPS62125670A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4982281A (en) * 1972-12-11 1974-08-08
JPS5024083A (en) * 1973-07-04 1975-03-14

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4982281A (en) * 1972-12-11 1974-08-08
JPS5024083A (en) * 1973-07-04 1975-03-14

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