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JPS62118624A - Limiter circuit - Google Patents

Limiter circuit

Info

Publication number
JPS62118624A
JPS62118624A JP60257700A JP25770085A JPS62118624A JP S62118624 A JPS62118624 A JP S62118624A JP 60257700 A JP60257700 A JP 60257700A JP 25770085 A JP25770085 A JP 25770085A JP S62118624 A JPS62118624 A JP S62118624A
Authority
JP
Japan
Prior art keywords
resistor
diode
output
operational amplifier
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60257700A
Other languages
Japanese (ja)
Other versions
JPH0638570B2 (en
Inventor
Minoru Nagai
永井 稔
Ritsuo Hasegawa
長谷川 律雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Precision Co Ltd
Original Assignee
Mitsubishi Precision Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Precision Co Ltd filed Critical Mitsubishi Precision Co Ltd
Priority to JP60257700A priority Critical patent/JPH0638570B2/en
Publication of JPS62118624A publication Critical patent/JPS62118624A/en
Publication of JPH0638570B2 publication Critical patent/JPH0638570B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE:To obtain a flat limiter characteristic by connecting a cathode of the 1st diode and the 1st resistor, an anode of the 2nd diode and the 2nd resistor in series respectively, connecting the anode of the 1st diode and the cathode of the 2nd diode to an output terminal of an operational amplifier and connecting the other terminal of the 1st and 2nd resistors to the output of a feedback resistor so as to use the connecting point as the output terminal of the operational amplifier circuit. CONSTITUTION:The 1st resistor R1 and the cathode of the 1st diode D1, and the 2nd resistor R2 and the anode of the 2nd diode D2 are connected in series respectively, the anode of the 1st diode D1 and the cathode of the 2nd diode D2 are connected to the output terminal of the operational amplifier A1 at a connecting point (b), the other terminal of the 1st and 2nd resistors R1, R2 not connected to the diodes D1, D2 is connected to the output point (e) of the feedback resistor Rf and the point is used as the output point of the operational amplifier A1. Further, an input resistor Ri is connected to an inverting input of the operational amplifier A1 and the feedback resistor Rf is provided to the feedback circuit.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明はリミッタ回路に係り、特に演算増巾器の正側
出力飽和電圧、負側出力飽和電圧を夫々単独に設定でき
、平坦な振巾制限特性をうろことができるリミッタ回路
である。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a limiter circuit, and in particular, the positive output saturation voltage and negative output saturation voltage of an operational amplifier can be set independently, and a flat amplitude can be achieved. This is a limiter circuit that allows you to wander the limiting characteristics.

(従来の技術) 従来リミッタ機能を実現する具体的な回路としては飽和
電圧を別途に出力端子に与える回路、シャントリミッタ
回路、フィードバックリミッタ回路等種々考えられてい
る。第2図aはフィードバックリミッタ回路として最も
簡単で代表的な回路構成を示している。ここで演算増巾
器A1の負の入力端子には入力抵抗Riをへて入力電圧
Eiが与えられる。ス、この負の入力端子はダイオード
D°2をへて抵抗R4により出力端子に接続される。
(Prior Art) Conventionally, various specific circuits for realizing the limiter function have been considered, such as a circuit that separately supplies a saturation voltage to an output terminal, a shunt limiter circuit, and a feedback limiter circuit. FIG. 2a shows the simplest and typical circuit configuration of a feedback limiter circuit. Here, an input voltage Ei is applied to the negative input terminal of the operational amplifier A1 through an input resistor Ri. This negative input terminal is connected to the output terminal by a resistor R4 through a diode D°2.

一方、出力端子から饋還抵抗Rfを介して演算増巾器A
、の負の入力端子に接続される饋還回路が設けられる。
On the other hand, the operational amplifier A is connected from the output terminal through the feedback resistor Rf.
A feedback circuit is provided which is connected to the negative input terminal of .

また下限の飽和値をもたらすための電源端子から+E2
が抵抗R3をへて前記抵抗R4とダイオードD′2のカ
ソードの接続点に与えられ、更に上限の飽和値をもたら
すための電源端子か゛ら−E1が抵抗R′1をへて抵抗
R’2と、ダイオードD°、のアノードとの接続点に与
えられ、ダイオードD゛、のカソードは演算増巾器AI
の負の入力端子に接続される。演算増巾器A、の正の入
力端子は接地される。全入力電圧Eiが零であればダイ
オードD’、D’2はオフ状態であり、又出力電圧Eo
も零であるが入力電圧Eiに正電圧を徐々に加えていく
と、ダイオードD’、D’2がオフ状f 態では利得が−Riの逆相増中器であるから入力電圧に
比例して徐々に負の出力電圧が現れる。この状態が第2
図すの線形領域B’−C−D’である。
Also, +E2 from the power supply terminal to bring the lower limit saturation value.
is applied to the connection point between the resistor R4 and the cathode of the diode D'2 through the resistor R3, and -E1 is applied from the power supply terminal to provide the upper limit saturation value to the resistor R'2 through the resistor R'1. , the anode of the diode D°, and the cathode of the diode D゛, is connected to the operational amplifier AI.
connected to the negative input terminal of The positive input terminal of operational amplifier A is grounded. If the total input voltage Ei is zero, the diodes D' and D'2 are in the off state, and the output voltage Eo
is zero, but when a positive voltage is gradually added to the input voltage Ei, when the diodes D' and D'2 are off, they are negative-phase multipliers with a gain of -Ri, so the gain is proportional to the input voltage. A negative output voltage gradually appears. This state is the second
The figure shows the linear region B'-C-D'.

入力電圧を更に高くするとダイオードD°2がオンにな
り、饋還抵抗RfにR4が並列に入り、領域A’−B’
が形成される。飽和電圧値は抵抗R4の記に比べ傾斜し
、従って入力電圧がダイオードD゛2をオンさせる点か
ら飽和電圧が変わる。入力電圧Eiが負の電圧のときも
同様でダイオード(発明が解決しようとする問題点) 前記で示した従来のフィードバックリミッタ回路ではダ
イオードがオンしてからのリミッタ特性は入力電圧が正
負に増加するに従って饋還抵抗Rfと抵抗R°2または
抵抗R4の並列抵抗値に比例した傾斜出力になり、平坦
特性をうろことができない欠点があった。
When the input voltage is further increased, diode D°2 is turned on, R4 is connected in parallel to the feedback resistor Rf, and the region A'-B'
is formed. The saturation voltage value is sloped compared to that of resistor R4, and therefore the saturation voltage changes from the point where the input voltage turns on diode D2. The same applies when the input voltage Ei is a negative voltage (a problem to be solved by the invention).In the conventional feedback limiter circuit shown above, the limiter characteristic after the diode is turned on is that the input voltage increases in positive and negative directions. Accordingly, the slope output becomes proportional to the parallel resistance value of the feedback resistor Rf and the resistor R°2 or the resistor R4, and there is a drawback that flat characteristics cannot be achieved.

(問題点を解決するための手段) 上記の点を考慮してこの発明では出力飽和電圧を平坦特
性にできる上、飽和値をもたらすための電源は演算増巾
器の電源を使うことができるとともに飽和値は正負それ
ぞれ独立して設定でき、更に饋還回路に含まれる受動素
子の数を減らしたものである。
(Means for Solving the Problems) In consideration of the above points, in this invention, the output saturation voltage can be made flat, and the power supply for providing the saturation value can be the power supply of the operational amplifier. The saturation values can be set independently for positive and negative values, and the number of passive elements included in the feedback circuit is further reduced.

即ちこの発明は演算増巾器において、その出力側から入
力側にいたる饋還回路に饋還抵抗のほかに抵抗とダイオ
ードからなる受動素子のみを含むもので、前記受動素子
としては第1のダイオードのカソードと第1の抵抗なら
びに第2のダイオードのアノードと第2の抵抗を夫々直
列に接続し、更に前記第1のダイオードのアノードと前
記第2のダイオードのカソードを前記演算増巾器の出力
端子に接続し、又前記第1の抵抗と前記第2の抵抗の他
側を前記饋還抵抗の出力側に接続し、演算回路の出力端
子とすることにより平坦なリミッタ特性をつるとともに
、出力飽和値を正変圧負電圧分それぞれ独立に設定でき
うるようにしたことを特徴とするものである。
That is, the present invention is an operational amplifier in which a feedback circuit from an output side to an input side includes only passive elements consisting of a resistor and a diode in addition to a feedback resistor, and the passive element includes a first diode. The cathode of the first diode and the first resistor, and the anode of the second diode and the second resistor are connected in series, respectively, and the anode of the first diode and the cathode of the second diode are connected to the output of the operational amplifier. By connecting the other side of the first resistor and the second resistor to the output side of the feedback resistor and using it as the output terminal of the arithmetic circuit, flat limiter characteristics can be obtained, and the output The present invention is characterized in that the saturation value can be set independently for the positive and negative voltages.

(作 用) かくてこの発明におけるリミッタ特性は演算増巾器を動
作させるのに必要な電源電圧と饋還回路に含まれた抵抗
とダイオードにより形成されるもので、出力電圧の飽和
値が前記電源電圧を基準として演算増巾器の出力端子か
ら饋還回路に接続される受動素子の値によって決定され
るものとなっている。
(Function) Thus, the limiter characteristic in this invention is formed by the power supply voltage necessary to operate the operational amplifier and the resistor and diode included in the feedback circuit, and the saturation value of the output voltage is It is determined by the value of the passive element connected from the output terminal of the operational amplifier to the feedback circuit with reference to the power supply voltage.

(実施例) 次にこの発明を第1図aの実施例回路構成図と、第1図
すの特性曲線図により説明する。
(Embodiment) Next, the present invention will be explained with reference to an embodiment circuit configuration diagram shown in FIG. 1A and a characteristic curve diagram shown in FIG. 1S.

尚便宜上第2図a 、 +3相当部分は同一符号で゛示
すものとする。
For convenience, the parts corresponding to Figure 2a and +3 are indicated by the same reference numerals.

まず受動素子の接続としては第1の抵抗R1と第1のダ
イオードD1のカソードならびに第2の抵抗R2と第2
のダイオードD2のアノードを直列に接続し、第1のダ
イオードD1のアノードと第2のダイオードD2のカソ
ードは接続点すをもって演算増巾器A1の出力端子に接
続し、第1゜第2の抵抗R,R2のダイオードDID2
に接続しない側の他端を饋還抵抗Rfの出力側e点で接
続し演算増巾器A1の出力回路とする。
First, the connections of the passive elements are the first resistor R1 and the cathode of the first diode D1, and the second resistor R2 and the second diode D1.
The anodes of the diodes D2 are connected in series, the anodes of the first diode D1 and the cathodes of the second diode D2 are connected to the output terminal of the operational amplifier A1 at the connection point, and the first and second resistors are connected in series. R, R2 diode DID2
The other end on the side not connected to is connected at the output side point e of the feedback resistor Rf to form the output circuit of the operational amplifier A1.

又演算増巾器A1の負の入力端子には入力抵抗R;が接
続され併せて饋還回路に饋還抵抗Rfが設けられる。正
の入力端子は接地される。
Further, an input resistor R; is connected to the negative input terminal of the operational amplifier A1, and a feedback resistor Rf is also provided in the feedback circuit. The positive input terminal is grounded.

前記のように構成された演算増巾器に入力電圧Eiを与
えると出力電圧Eoが現れる。入力電圧Eiと出力電圧
Eoの関係はダイオードD1またはD2がそれぞれオン
の状態において逆■増中器であるからEO=−尺1・E
iで現される。この状形i が第1図すの線形領域B−C−Dで、入力電圧Eiが零
の状態では出力電圧Eoも零であるが、入力電圧Eiに
正電圧または負電圧を徐々に加えRf たとき出力電圧Eoは一1Fの傾きで入力電圧Eiに比
例して徐々に負電圧、正電圧が現れる。
When an input voltage Ei is applied to the operational amplifier configured as described above, an output voltage Eo appears. The relationship between the input voltage Ei and the output voltage Eo is that when the diode D1 or D2 is on, it is an inverse multiplier, so EO = -Saku1・E
Represented by i. This shape i is in the linear region B-C-D of Figure 1, and when the input voltage Ei is zero, the output voltage Eo is also zero, but if a positive or negative voltage is gradually added to the input voltage Ei, Rf At this time, the output voltage Eo gradually becomes a negative voltage and a positive voltage in proportion to the input voltage Ei with a slope of -1F.

入力電圧Eiをさらに高くしていくと、出力電圧Eoは
演算増巾器A1の電源電圧上Vcと抵抗R,,R2、饋
還抵抗Rfおよび負荷抵抗R,に依存するある電圧に達
したとき飽和する。
When the input voltage Ei is further increased, the output voltage Eo reaches a certain voltage that depends on the power supply voltage of the operational amplifier A1, Vc, the resistors R,, R2, the feedback resistor Rf, and the load resistor R, saturate.

即ち演算増巾器A1の出力端子に接続される抵抗R,,
R2の抵抗値をR,、R2、ダイオードDI +D2の
順方向電圧をV PDl、 V FD2 、演算増巾器
A1の最大出力電圧振巾を十VONおよび負荷抵抗をR
Lとすると出力端子での飽和電圧±Eosはで現される
That is, the resistors R, , connected to the output terminal of the operational amplifier A1,
The resistance value of R2 is R,, R2, the forward voltage of diode DI + D2 is V PDl, V FD2, the maximum output voltage amplitude of operational amplifier A1 is 10 VON, and the load resistance is R.
When it is L, the saturation voltage ±Eos at the output terminal is expressed as follows.

即ち入力電圧Eiにより徐々に増加した出力電圧Eoは
設定飽和電圧値±F、osに達すると、以後入力電圧E
iが増加しても出力電圧Eoは士EO5の値で飽和する
That is, when the output voltage Eo, which gradually increases due to the input voltage Ei, reaches the set saturation voltage value ±F,os, the input voltage E
Even if i increases, the output voltage Eo is saturated at a value of EO5.

従って饋還回路に設けた抵抗R,R2の値を(1)(2
)式によって選ぶことにより出力電圧EOの飽和値上E
ONを正側、負側それぞれ単独に設定することができる
Therefore, the values of the resistors R and R2 provided in the feedback circuit are (1) (2)
) by selecting the saturation value E of the output voltage EO.
ON can be set independently for the positive side and the negative side.

また上記実施例では本受動素子の動作によるリミッタ機
能、特性について説明したが抵抗R1+R2が出力端子
に直列に含まれることによって演算増巾器の出力電流を
最大定格値以下におさえることができ、演算増巾器の過
負荷電流破壊から保護することができる。
In addition, in the above embodiment, the limiter function and characteristics due to the operation of this passive element were explained, but by including the resistors R1+R2 in series with the output terminal, the output current of the operational amplifier can be suppressed below the maximum rated value, and the operational It can protect the amplifier from overload current damage.

即ち演算増巾器の許容最大負荷電流をIO5とす(発明
の効果) 以上の説明から明らかなようにこの発明によれば饋還回
路に饋還抵抗のほかにダイオードと抵抗のみを用い、演
算増巾器を動作させるのに必要な電源電圧と、饋還増巾
器を動作させるのに必要なこのようなダイオードと抵抗
のみの簡単な回路構成とし、飽和値をもたらすための特
別な電圧源をもつことなく、はぼ理想に近い平坦な特性
をもつリミッタ回路が得られるうえに飽和電圧を正負夫
々に単独に設定可能となしたものである。
In other words, the maximum allowable load current of the operational amplifier is IO5 (effects of the invention). A simple circuit configuration consisting of only the power supply voltage necessary to operate the amplifier and the diodes and resistors necessary to operate the feedback amplifier, and a special voltage source to bring the saturation value. A limiter circuit with nearly ideal flat characteristics can be obtained without having a saturated voltage, and the saturation voltage can be set independently for positive and negative voltages.

【図面の簡単な説明】[Brief explanation of drawings]

第1図aはこの発明の実施例リミッタ回路構成図、第1
図すは第1図aの入出力特性曲線図、第2図aは従来使
用されている代表的なリミッタ回路構成図、第2 (2
I11は第2図aの入出力特性曲線図である。 図でA1は演算増巾器、DID2はダイオード、Riは
入力抵抗、Rfは饋還抵抗、R,R2は飽和値設定抵抗
FIG. 1a is a block diagram of a limiter circuit according to an embodiment of the present invention;
The figures are the input/output characteristic curve diagram of Figure 1a, Figure 2a is the configuration diagram of a typical limiter circuit used conventionally, and Figure 2 (2)
I11 is the input/output characteristic curve diagram of FIG. 2a. In the figure, A1 is an operational amplifier, DID2 is a diode, Ri is an input resistance, Rf is a feedback resistance, and R and R2 are saturation value setting resistances.

Claims (1)

【特許請求の範囲】[Claims] (1)演算増巾器において、その出力側から入力側にい
たる饋還回路に、饋還抵抗のほかに抵抗とダイオードか
らなる受動素子のみを含むもので、前記受動素子として
は第1のダイオードのカソードと第1の抵抗、および第
2のダイオードのアノードと第2の抵抗を夫々直列に接
続し、更に前記第1のダイオードのアノードと前記第2
のダイオードのカソードを前記演算増巾器の出力端子に
接続し、又前記第1の抵抗と前記第2の抵抗の他側を前
記饋還抵抗の出力側に接続し、演算回路の出力端子とす
ることにより出力の正側飽和電圧負側飽和電圧をそれぞ
れ独立に設定できるようにしたことを特徴とするリミッ
タ回路。
(1) In an operational amplifier, the feedback circuit from the output side to the input side includes only a passive element consisting of a resistor and a diode in addition to the feedback resistor, and the passive element is a first diode. The cathode of the first diode and the first resistor are connected in series, and the anode of the second diode and the second resistor are connected in series, and the anode of the first diode and the second resistor are connected in series.
The cathode of the diode is connected to the output terminal of the operational amplifier, and the other sides of the first resistor and the second resistor are connected to the output side of the feedback resistor, and the output terminal of the operational circuit is connected to the output terminal of the operational amplifier. A limiter circuit characterized in that the positive side saturation voltage and the negative side saturation voltage of the output can be independently set by doing so.
JP60257700A 1985-11-19 1985-11-19 Limiter circuit Expired - Lifetime JPH0638570B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60257700A JPH0638570B2 (en) 1985-11-19 1985-11-19 Limiter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60257700A JPH0638570B2 (en) 1985-11-19 1985-11-19 Limiter circuit

Publications (2)

Publication Number Publication Date
JPS62118624A true JPS62118624A (en) 1987-05-30
JPH0638570B2 JPH0638570B2 (en) 1994-05-18

Family

ID=17309896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60257700A Expired - Lifetime JPH0638570B2 (en) 1985-11-19 1985-11-19 Limiter circuit

Country Status (1)

Country Link
JP (1) JPH0638570B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211905A (en) * 1990-01-16 1991-09-17 Fujitsu Denso Ltd Limiter circuit
JP2008200754A (en) * 2008-04-14 2008-09-04 Amada Co Ltd Hemming die

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915407A (en) * 1982-07-16 1984-01-26 Asahi Chem Ind Co Ltd Polymerization of 1-olefin
JPS60109A (en) * 1983-06-15 1985-01-05 Fujitsu Ltd Output amplitude limiting and amplifying circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915407A (en) * 1982-07-16 1984-01-26 Asahi Chem Ind Co Ltd Polymerization of 1-olefin
JPS60109A (en) * 1983-06-15 1985-01-05 Fujitsu Ltd Output amplitude limiting and amplifying circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03211905A (en) * 1990-01-16 1991-09-17 Fujitsu Denso Ltd Limiter circuit
JP2008200754A (en) * 2008-04-14 2008-09-04 Amada Co Ltd Hemming die

Also Published As

Publication number Publication date
JPH0638570B2 (en) 1994-05-18

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