JPS62117198A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent a cycle time from extending even in a DRAM with an ECC circuit by selecting either of the output of a circuit which performs an error detection and correction and that of an encoder adding them, and outputting it to a write amplifier. CONSTITUTION:A parity bit is also corrected with the output of a decoder DEC, and a correct read out output of twelve bits can be obtained. A constitution in such a way makes unnecessary the generation of the parity bit at an encoder ENC, and after a data has been read out, or when a corrected data is written in a refresh operation, the output of an error correction circuit EC can be directly written on a memory cell through as selector SEL and write amplifiers WA1-WA12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor storage bag (8) and a random access memory with an error detection and correction circuit.

[Conventional technology]

Semiconductor memory devices are becoming more and more compact7, but as the capacity increases, that is, the number of memory cells mounted on a chip increases, the probability of defective memory cells occurring also increases6. As a remedy for this problem, it has become common to provide redundant focusing.

On the other hand, soft errors may occur in semiconductor memory devices due to alpha ray irradiation, etc., and error detection and correction (E
CC) The circuit is valid. That is, if this circuit is used, it is usually possible to correct a 1-bit error and detect a 2-bit error.

When an FCC circuit is installed in a semiconductor memory device, it is possible to deal with defective memory cells, and no error appears from the outside without switching using redundant bits. It is not easy to replace defective memory cells with redundant bits. In other words, in order to do this, it is necessary to perform a chip inspection to find a defective cell, register its address in Chisop, and enable switching to a redundant bit line when the address of the defective cell is accessed. However, first of all, it is not easy to register the defective cell address. In other words, if the above-mentioned ROM is a fuse-type memory made of polycrystalline silicon, it is necessary to blow the fuse to register the address, which requires a large current, and the resistance of the switching transistor is high, making it difficult to supply this current sufficiently. If this is not possible, writing (melting) will not be possible. There is also a method that burns out the fuse with a laser beam, but with this method, the tester cannot be directly connected to the laser irradiation device, so defect addresses must be registered after the inspection, which increases the number of steps, and when the degree of integration increases, the laser irradiation position alignment becomes difficult. These problems will disappear if the ECC circuit is installed to eliminate the need for a redundant circuit.

Of course, ECC is not used for hard errors without using redundant bits.
If it is processed by a circuit, it will not be possible to deal with further soft errors that occur. However, the probability that a soft error will overlap with a part of the hard error is low.

[Problems to be Solved by the Invention] Although there are great advantages to mounting an ECC circuit on a memory chip as described above, the problem is that the write cycle becomes complicated. ECC circuits include a Hamming code method, a horizontal-vertical parity method, etc., and the typical Hamming code method will be explained below.

Hamming code is a code that performs error detection and correction by adding redundant bits to n bits of information.
ED (Single Error Correction
on DoubleError Detection
) It is known that in order to realize ECC of the type, it is sufficient if there is a relationship such that 2/1≧n+. From the above equation, it can be seen that the number of redundant additional bits is small compared to kneading when the number of information bits n is large.

For example, for n=32, =6, for n-16, =5. For n=8, n=4. Of course, it is preferable to have a small number of additional bits since this avoids increasing the chip area, and in this respect, it is preferable to increase the number of information bits n as much as possible and add a relatively small number of redundant bits to it. For example, considering a 4M via hDRAM, n=32. If = 6, the cell matrix configuration becomes (32+6) x 64 x 2048, and the area of the cell array is approximately 19%, but n-1
6, if =5, the cell matrix configuration will be (16+5) x 128 x 2048, and the area increase of the cell array will be approximately 31
%.

However, the number of input/output bits of DRAM is l bit, 4 bit, 8 bit/7 bit, etc., n=32°k=6
When the ECC method is adopted, the number of input and output points is extremely small relative to the encoded data bit length n.

If an AM equipped with an ECC circuit is configured in a format where the number of input/output bits is less than the encoded data bit length as shown in the figure, the second
It will look like the figure.

In FIG. 2, the number of input and output data bins is 8, the encoded data bin 1-length n is 32, and k=6. Data of 38 bits (32 data bits + 6 parity bits) is transferred in parallel from a memory cell array (not shown) to the child data base and DB.
l, DBl,... DB38, withdraw with DB38. Each data bus has a data bus amplifier SBI~
5B38 is connected, and amplifies signals from the bit line and sense amplifier appearing on the data bus at high speed. Next, the 38-bit signal is input to the error check circuit EDC.

EDC detects errors by decoding Hamming codes, and in this case it consists of 3 sets of E, -OR (exclusive OR) circuits powered by 19 people, 2 sets of E-ORs powered by 16 people, and 1 set of E-ORs powered by 7 people. be done. The E-OR of the first group of 19 people is 1. Each connection follows the Hamming code construction convention. 3. 5. 7゜9・・・・・・Take E-OR of 37 and odd numbered data, E-OR of the second group
is 2. 3. 6. 7. 10.11.・・・・・・
Take the E-OR of the 38th data and perform the E-OR of the third group.4. 5. 6. 7゜12.13,14,
15.・・・・・・36th, 37th, 38th data E
- Take the OR. The E-OR of the fourth group of 16 people is 9.10.11.12゜13.14.15.16.2
5.26.27. ...For the 32nd data, the E-OR of the 5th group is 1. 2.3. 4
．． 5.6.7,8゜17.18.19.・・・・・・3
For the second data, the E-OR of the 6th group of 7 people is 33°3·t,... Take the E-OR of the 38th data.

The E-OR outputs of these six groups are called syndromes, and the syndromes of 6 bif 1- are input to the decoder DEC. The decoder DEC decodes the syndrome of 6 bits 1- and detects the error address 1 out of 38 bits.
produces output pointing out one thing. Since 32 bits of these are actually related to data output, an error correction circuit EC is provided for 32 data bits, and a decoder D
The output of the EC is input to the circuit EC. The error correction circuit is specifically an E-OR circuit, and if one input is 1, the output is the inversion of the other input.Using this feature, the output of the decoder DEC is 1, and the error correction circuit (E-OR circuit) inverts the other input (data) to make it correct data and outputs it. The corrected 32-bit data is input to the multiplexer MPX, and the 8 bits to be output are selected using the column address CA (0 and 1 are subscripts indicating each bit. The same applies to the others).
It is input to the output sofa OB and output from the Dout terminal.

On the other hand, the inspected 32-bit data is stored in the selector SEL.
is input to the encoder ENC via
8 back to the memory cell. is written (written). This is to correct the error bits stored in the memory and make them correct.

On the other hand, when writing, 8 bits of input data are input to the Din terminal, and the input buffer IB takes in the data using an external clock WE (write enable). Since 8 bits out of 32 data bits are updated by writing, the Hamming code must be newly created. Therefore, in a write operation, it is necessary to first read out the 38-bit encoded data whose group includes the 8 bits to be written. In addition, the remaining 24 bits out of the 32 bits that are not subject to writing must be verified to be correct, otherwise a new Hamming code will be created based on the bits that may contain errors. That's inconvenient.

Therefore, the write operation must first be started by performing exactly the same operation as the read operation to obtain corrected 32-bit data. The selector SEL selects the column addresses CAo and CA out of the 32 bits read out and corrected in this way.
It functions to replace the 8 pins determined by l with the data of the input vanofer IB. Thus, 32-bit data obtained by updating 8 bits is input to the input of the encoder ENC.

The encoder ENC generates the parity pinot I- of the Hamming code and is composed of six E-OR circuit groups. The first group determines the first bit of the 38-bit code, and is the one that determines the first bit of the 38-bit code.
, 5.7.9. ...... Take the E-OR of the th bit. The second group determines the second bit, 3.6, 7, 10.11. E-OR1 third group of . . .th bit determines the 4th bit, 5° 6.7, 12, 13. 14, 15. ...
... E-OR of the th focus, the 4th group is the 8th
The one that determines the th bit is 9.10, 11.12, ・
...The E-OR2 fifth group of the 16th bit is 17.18.19°20.21.・・・・・・E-OR of the th bit, the 6th group determines the 32nd bit, 3
3.34. ...... Take the E-OR of the th bit.

As a result, 1. Second. 4th. 8th. Six parity bits generated by the encoder ENC are stored in the 16th and 32nd pino 1-positions, and 32-bit data that is the output of the selector SEL is stored in the other bit positions. Accounting 38-bit write data is created. This is applied to 38 sets of write amplifiers WAI to WA38 to drive the data bus and write to the memory cells.

As mentioned above, the write operation of memory with ECC consists of: 1. First, reading data at some addresses including the address to be written, 2.
Inspecting and correcting the read data, ■Replacing part of the data with new data to be written, ■Coding based on the new data, and ■Writing to the cell using the Rai-i amplifier. Take steps.

For this reason, in the read operation, there is not only a delay in error detection and correction compared to conventional memory without ECC, but also when data is returned to the memory cell, it is encoded again and sent to the write amplifier. This has the disadvantage that the cycle time becomes longer because the operation of writing to the cell via the memory card is added.

However, it is also possible to simply read and correct the data without encoding by the encoder in the second half and writing the encoded data. In this case, even if an error is discovered and the output is corrected, the memory cell will still hold the erroneous data. However, since the DRAM performs refreshing, the error cannot be detected and corrected during this refresher operation. There is no practical problem even if the memory cell temporarily holds erroneous data for a short period of time.

However, this latter half of the recoding operation is normally performed. The reason is that the write operation takes a long cycle from ■ to ■ as mentioned above, and usually the cycle times for read and write are equal, so the recoding operation is omitted and only the read cycle is faster. This is because words are meaningless.

Since the filling-in operation requires the cycles (1) to (2) described above, the cycle time is inevitably longer than that of the conventional ECC% memory.

The present invention improves these points and improves the ECC circuit.
However, it is intended to prevent the cycle time from becoming too long.

[Means for solving problems]

The present invention provides a semiconductor memory device incorporating a Hamming code error detection and correction circuit, in which read data consisting of the same number of data bits as the number of input/output data bits of the memory device and parity bits of a Hamming code for the same number of data bits is input. 2. a circuit that detects and corrects errors in the data bits and parity bits; an encoder that receives input data and outputs data obtained by adding Hamming code parity bits; and an output of the circuit that detects and corrects errors. and a selector which selects one of the outputs of the encoder and outputs the selected one to the write amplifier.

[Effect]

When the data bit length of the Hamming code and the input/output data pit length are made equal, there is no need to read data during writing, and the write data can be immediately encoded and written, thereby shortening the cycle time. If writing can be speeded up, the re-encoding operation at the time of reading can be omitted and the speed of the memory can be increased. In addition, power consumption can be reduced by writing directly without reading.

〔Example〕

FIG. 1 shows an embodiment of the invention. The input/output data is 8 bits (so-called x8 configuration), and the encoded data in the memory chip is also a Hamming code of 8 data bits + 4 parity bits. In this circuit, the same parts as in FIG. 2 are given the same reference numerals.

In this memory, the cell array and sense amplifier (not shown) are driven during read operation, and the selection of the column decoder drives the cell array and sense amplifier (not shown).
Two sets of data buses DB1. DBI~DB12. DB12
The encoded data appears.

The data bus amplifiers SBI to 5B12 amplify the voltages on the respective data buses at high speed and input them to the error detection circuit EDC. The error check circuit EDC detects errors by decoding the pointing code, and in this case, the six-person E-OR
Consists of 2 sets of E-OR with 2 silk and 4.5 manpower. Each connection follows the Hamming code convention, and the E-OR of the first group of 6 people is 1, 3, 5, 7, 9, and 11th bit E-OR, and the second group is 2. 3.
6. 7°io, take E-OR of it-th bit. The third group of 5 people is the E-OR of the 4th, 5.6th, 7.12th bits, and the fourth group is 8.9°10.
11. Take the E-OR of the 12th bit.

The outputs of these four groups, or syndromes, enter the decoder DEC. The DEC decodes the 4-bit syndrome and produces an output that indicates the location of the error among the 12 data bits plus parity pits. This is input to the error correction circuit EC, and as a result, all of the 12-bit encoded data including the parity bit is corrected to correct data.

In the memory shown in Fig. 2, error correction by the output of the decoder DEC was performed only on the data bits and not on the parity bits, but in the memory shown in Fig. 2, this is encoded by rewriting after reading. This is because the parity bit is generated using the circuit ENC. In the present invention, as shown in the figure, the parity bit is also corrected at the output of the decoder DEC to obtain a correct 12-bit readout output. In this way, there is no need to generate a parity bit again in the encoder ENC, and when writing corrected data after reading data or during a refresh operation, the error correction circuit E
C output to selector SEL, write amplifier WAI~WA
It is possible to directly write to a memory cell using 12 paths. This is why the encoder ENC is included after the selector SEL in FIG. 2, but is not present in the circuit of FIG.

Of this corrected 12 bits I, 8 data bits are 3.5, 6, 7, 9, 10° 11.12 at the focus position.
．． The th bit data is input to the output sofas OBI to OB8 and becomes data outputs Doutl to Dout8.

In addition, the corrected 12-bit code enters the selector SEL, and when it is continuously output or refreshed, the selector SEL supplies the corrected data to the write amplifiers WAI to WA12, and when the write amplifiers WAI to WAI2 are driven, the 12-bit data is transferred to the memory cell. returned inside. Selector SEL is internal clock W generated from write enable clock WE.
It operates according to the EI and serves to select either the corrected 12-bit data or the encoded 12-bit data (output of the encoder ENC) at the time of writing and provide it to the write amplifier.

During a write operation, 8 bits of input data are input to the Din terminal, and the input buffer sofas TBI to IB8 take in the data using the external clock WE. The 8-bit input data is applied to the encoder ENC, which generates the 4 parity bits of the Hamming code into 12 pino 1- encoded data. The encoder ENC consists of 2 sets of 5-man powered E-OR circuits and 2 sets of 4-man powered E-OR circuits, and encodes bit positions 3, 5.6, 7°, 9.10, 11.12 (8 digital storage positions), the first group is bin 1 - position 3, 5, 6° 7.
9.11 E-OR is taken, and this becomes the first parity bit data in the code. The second group takes E-OR of bit positions 3, 6.7, and 10.11, which becomes the parity pit 1-data of the second pit position in the code. Also, the third group includes bit positions 5, 6, 7, and so on.
120E-OR is taken, and this becomes the fourth parity bit data in the code. Furthermore, the fourth group takes E-OR of bit positions 9.10 and 11.12, which becomes parity bit data of the 8th pit position in the code.

The encoded 12 hits are given to the write amplifiers WAI to WA 12 through the select SEL, and stored in the cells through these.

In this way, in the present invention, writing coded data can be created immediately using input data only, so prior to writing, successive outputs are performed, the data is inspected and corrected, and the input data and There is no need to perform compositing or parity generation. Therefore, write cycle time and power consumption can be reduced. Power consumption can be reduced by
During writing, data bus sense amplifier SBI~sss,i
This is because the detection circuit EDC and decoder DEC do not need to be moved.

Further, in the present invention, the selector SEL can be simplified.

To explain with FIG. 3, (a+ is the selector SE in the present invention
It simply switches between the corrected 12-bit data from the error correction circuit EC and the encoded 12-bit data from the encoder ESC, and consists of switches SW+ and SW.
It is simple and consists of only 2 parts. On the other hand, the second
The selector SEL in the figure replaces each of the 8 hints and 4 groups (specified by the column address) of the corrected 32-bit data from the error correction circuit EC with the input 8 bits, as shown in Figure 3 tb+. The switch configuration and control are complicated because the switch must have a function to pass the corrected 32 bits (when writing) and a function to directly pass the corrected 32 bits (when reading or refreshing).

〔Effect of the invention〕

As explained above, in the configuration of the present invention, rewriting after data correction can be omitted when data is continuously written. That is,
In the memory shown in Fig. 2, the sequence was: ■Continuous reading, ■Error detection/correction, ■Data output, ■Rewriting of data after correction by write amplifier drive. You can output only data. As a result, when an error is found in successive data, the correct data is output, but the incorrect data remains in the cell array. Since a "patrol operation" is performed in which the data is sequentially inspected, corrected, and returned, even if an error occurs, the patrol operation will eventually rewrite the data to the correct data and there will be no particular problem. In addition, since correction and rewriting are not performed at the time of reading, there is no need to drive a write amplifier when successive readings are performed, and the effects of shortening cycle time and reducing power consumption can be obtained.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the present invention, and Figure 2 is an E
FIG. 3 is a block diagram showing an example of the configuration of a DRAM with CC, and is an explanatory diagram of the configuration of the selector.

Claims (1)

[Claims] In a semiconductor storage device incorporating a Hamming code error detection and correction circuit, read data consisting of the same number of data bits as the number of input/output data bits of the storage device and parity bits of a Hamming code for the same number of data bits as the number of input/output data bits of the storage device is provided. a circuit that receives input data and performs error detection and correction of the data bits and parity bits; an encoder that receives input data and outputs data obtained by adding Hamming code parity bits to the input data; 1. A semiconductor memory device comprising a selector which adds an output of a correction circuit and an output of the encoder, selects one of them, and outputs the selected one to a write amplifier.