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JPS6198014A - Noise pulse eliminating device - Google Patents

Noise pulse eliminating device

Info

Publication number
JPS6198014A
JPS6198014A JP59219549A JP21954984A JPS6198014A JP S6198014 A JPS6198014 A JP S6198014A JP 59219549 A JP59219549 A JP 59219549A JP 21954984 A JP21954984 A JP 21954984A JP S6198014 A JPS6198014 A JP S6198014A
Authority
JP
Japan
Prior art keywords
pulse
noise
input
flop
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59219549A
Other languages
Japanese (ja)
Inventor
Tsugutada Nakadokoro
中所 嗣忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59219549A priority Critical patent/JPS6198014A/en
Publication of JPS6198014A publication Critical patent/JPS6198014A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125Discriminating pulses
    • H03K5/1252Suppression or limitation of noise or interference

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To eliminate a noise pulse by connecting a delay time which has a delay time a little bit longer than the pulse width of the noise pulse to the clock terminal of a D flip-flop. CONSTITUTION:A pulse signal inputted to a terminal C is delayed by the delay circuit 2 and inputted to the clock terminal CK of the D flip-flop 3, and the other pulse signal is inputted to the terminal D of the D flip-flop 3. The delay time of the delay circuit 2 is set a little bit longer than the pulse width of the noise pulse and the D flip-flop 3 is clocked with input pulses which are delayed by a time a little bit longer than the pulse width of noise pulses, so only pulses having pulse width longer than the delay time appear at the terminal Q of the D flip-flop 3, so that noise pulses having pulse width longer than said time are all removed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はテレビジョン受像機、電話などの電子回路に利
用されているパルス中に含まれるノイズパルス除去装置
に関するものである、 従来の技術 第3図は従来のノイズパルス除去装置のブロック図、第
4図(a)は同装置における入力パルスの波形図、第4
図(b)は同じく出力パルスの波形図であり、1は抵抗
とコンデンサを直列に接続しコンデンサの両端を出力端
子とした積分回路である。第4図(2L)に示すように
入力パルスの前後にノイズパルスがある場合、従来はそ
のパルスを第3図に示す積分回路10入力端子人から入
力し、第4図(b)に示すようなノイズパルスのないパ
ルストシて積分回路1の出力端子Bより取り出していた
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a device for removing noise pulses contained in pulses used in electronic circuits such as television receivers and telephones.Prior art Fig. 3 4(a) is a block diagram of a conventional noise pulse removal device, FIG. 4(a) is a waveform diagram of an input pulse in the device, and FIG.
Figure (b) is also a waveform diagram of the output pulse, and 1 is an integrating circuit in which a resistor and a capacitor are connected in series and both ends of the capacitor are used as output terminals. When there is a noise pulse before and after the input pulse as shown in Fig. 4 (2L), conventionally, the pulse is inputted from the input terminal of the integrating circuit 10 shown in Fig. 3, and as shown in Fig. 4 (b). A pulse with no noise pulses was taken out from the output terminal B of the integrating circuit 1.

発明が解決しようとする問題点 しかし、積分回路1を用いて入力パルスのノイズパルス
除去を行うと、第4図(b)に示すように出力パルスは
入力パルスの入力電圧が立ち上がった時を始点にして、
時間の経過とともに除々に大きくなり、入力パルスの振
幅が0になるとその時点を振幅のピークとして除々に小
さくなっていくという波形を描く。すなわち、従来のノ
イズパルス除去装置では入力パルスと出力パルスの波形
が変化し、また、入力パルスの立ち下り部に対する出力
パルスの立ち下り部の位相がずれてしまった熟め、次段
の回路によってもう一度その出力パルスを整形する必要
があるという不都合を生じていた。
Problems to be Solved by the Invention However, when noise pulses are removed from the input pulse using the integrating circuit 1, the output pulse starts at the time when the input voltage of the input pulse rises, as shown in FIG. 4(b). and then
A waveform is drawn that gradually increases as time passes, and when the amplitude of the input pulse reaches 0, the amplitude peaks at that point and gradually decreases. In other words, in conventional noise pulse removal devices, the waveforms of the input and output pulses change, and the falling part of the output pulse is out of phase with the falling part of the input pulse. This creates an inconvenience in that the output pulse needs to be shaped once again.

本発明は上記欠点に鑑みて為されたものであり、入力パ
ルスと出力パルスの波形を変えずに、かつ立ち下り部の
位相のずれを生じさせないでノイズパルスの除去を行う
ノイズパルス除去装置を提供することを目的とする。
The present invention has been made in view of the above drawbacks, and provides a noise pulse removal device that removes noise pulses without changing the waveforms of input and output pulses and without causing a phase shift in the falling portion. The purpose is to provide.

問題点を解決するだめの手段 本発明は、入力パルスに含まれるノイズパルスの振幅時
間よりも遅延時間が僅かに長く設定されたパルス遅延回
路と、そのパルス遅延回路に入力パルスを入力して出力
された遅延パルスをクロックとするDタイプ−クリップ
・フロップとをノイズパルス除去に用いることによって
上記目的を達成せんとするものである。
Means to Solve the Problem The present invention provides a pulse delay circuit whose delay time is set slightly longer than the amplitude time of the noise pulse included in the input pulse, and a pulse delay circuit that inputs the input pulse to the pulse delay circuit and outputs the pulse. The above object is achieved by using a D-type clip flop using the delayed pulses as a clock for noise pulse removal.

作用 この技術的手段による作用は次のとおりである。action The effects of this technical means are as follows.

たDタイプ−フリップ・フロップにその入力パルスを入
力すると、ノイズパルスが除去されたパルスが出力され
る。また、そのパルスは入力パルスから遅延回路によっ
て遅延された部分を除いたパルスとなり、パルスの立ち
下り部の位相がずれたりしない。
When the input pulse is input to a D-type flip-flop, a pulse with noise pulses removed is output. Further, the pulse is a pulse obtained by removing the portion delayed by the delay circuit from the input pulse, and the phase of the falling portion of the pulse does not shift.

実施例 以下、本発明の一実施例を図面を用いて説明する。第1
図は本実施例におけるノイズパルス除去装置のブロック
図、第2図(&)は同装置における入力パルスの波形図
、第2図(b)は同じく遅延パルスの波形図、第2図(
C)は同じく出力パルスの波形図であり、2は入力パル
スをある設定時間だけ遅らせて出力する遅延回路、3は
クロックに基づいて入力パルスを処理するDタイプ−フ
リップ・フロップである。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of the noise pulse removal device in this embodiment, FIG. 2 (&) is a waveform diagram of the input pulse in the same device, FIG.
C) is a waveform diagram of the output pulse, and 2 is a delay circuit that delays the input pulse by a certain set time and outputs it, and 3 is a D-type flip-flop that processes the input pulse based on the clock.

次に動作について説明する。端子Cより第2図(8L)
のようなパルスの前後にノイズパルスのある入力パルス
を入れると遅延回路2により第2図(b)に示すような
入力パルスが時間Tだけ遅れた遅延パルスとなってその
出力側に出力され、Dタイプ−7リツプ・フロップ3の
クロック入力に入力される。なお、遅延時間Tについて
は入力パルスに含まれているノイズパルスの振幅時間を
僅かに超える時間に設定しておく。上記入力パルスは一
方ではDタイプ−フリップ・フロップ3のD入力に入力
され、遅延回路2より出力された遅延パルスをクロック
として端子りに第2図(C)のような、入力パルスから
遅延された部分である時間Tの振幅を除いた、ノイズパ
ルスのないパルスを出力する。
Next, the operation will be explained. Figure 2 from terminal C (8L)
When an input pulse with noise pulses before and after a pulse like this is input, the input pulse shown in FIG. 2(b) becomes a delayed pulse delayed by a time T and is outputted to its output side by the delay circuit 2. It is input to the clock input of D type-7 lip-flop 3. Note that the delay time T is set to a time that slightly exceeds the amplitude time of the noise pulse included in the input pulse. On the one hand, the above input pulse is input to the D input of the D type flip-flop 3, and is delayed from the input pulse as shown in FIG. A pulse with no noise pulse is output, except for the amplitude at time T, which is the part where the pulse is generated.

発明の効果 本発明は、入力パルスをある時間遅延させた遅延パルス
をクロックとするDタイプ−フリップ・フロップを用い
ることによって、遅延回路によって遅延された時間よシ
も短い時間のノイズパルスを除去するため、次段の回路
でもう一度そのパルスを整形する必要がないという効果
を有する。また、入力パルスと出力パルスの波形が変わ
らず、さらには入力パルスの立ち下り部に対する出力パ
ルスの立下シ部の位相も変わらないという効果も有する
Effects of the Invention The present invention uses a D-type flip-flop whose clock is a delayed pulse obtained by delaying an input pulse by a certain time, thereby eliminating noise pulses having a shorter time than the time delayed by the delay circuit. Therefore, there is an advantage that there is no need to shape the pulse again in the next stage circuit. Further, there is an effect that the waveforms of the input pulse and the output pulse do not change, and furthermore, the phase of the falling edge of the output pulse with respect to the falling edge of the input pulse does not change.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例におけるノイズパル  7ス
除米装置のブロック図、第2図(&) 、 (1)) 
、 (C)は同じくパルスの波形図、第3図は従来のノ
イズパルプ−置のブロック図、第4図e) 、 (b)
は同じくパルスの波形図である。 1・・・・・・積分回路、2・・・・・・遅・延回路、
3・・・・・・Dタイプ−フリップ・フロップ。
Fig. 1 is a block diagram of a noise pulse 7-pulse rice removal device according to an embodiment of the present invention, and Fig. 2 (&), (1))
, (C) is the same pulse waveform diagram, Figure 3 is a block diagram of a conventional noise pulp system, Figure 4 e), (b)
is also a pulse waveform diagram. 1...Integrator circuit, 2...Delay/delay circuit,
3...D type-flip flop.

Claims (1)

【特許請求の範囲】[Claims] 入力パルスに含まれるノイズパルスの振幅時間よりも僅
かに長い時間だけ入力パルスを遅延させる遅延回路と、
前記遅延回路より出力した遅延パルスをクロックとして
入力するDタイプ−フリップ・フロップとを具備し、前
記入力パルスを前記Dタイプ−フリップ・フロップに入
力することによってノイズパルスの除去を行うことを特
徴とするノイズパルス除去装置。
a delay circuit that delays the input pulse by a time slightly longer than the amplitude time of the noise pulse included in the input pulse;
It is characterized by comprising a D-type flip-flop into which the delayed pulse outputted from the delay circuit is input as a clock, and noise pulses are removed by inputting the input pulse to the D-type flip-flop. Noise pulse removal device.
JP59219549A 1984-10-19 1984-10-19 Noise pulse eliminating device Pending JPS6198014A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59219549A JPS6198014A (en) 1984-10-19 1984-10-19 Noise pulse eliminating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59219549A JPS6198014A (en) 1984-10-19 1984-10-19 Noise pulse eliminating device

Publications (1)

Publication Number Publication Date
JPS6198014A true JPS6198014A (en) 1986-05-16

Family

ID=16737239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59219549A Pending JPS6198014A (en) 1984-10-19 1984-10-19 Noise pulse eliminating device

Country Status (1)

Country Link
JP (1) JPS6198014A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572549A (en) * 1994-04-27 1996-11-05 Nec Corporation Noise cancel circuit capable of cancelling noise from a pulse signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572549A (en) * 1994-04-27 1996-11-05 Nec Corporation Noise cancel circuit capable of cancelling noise from a pulse signal

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