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JPS6188636A - Demodulation circuit - Google Patents

Demodulation circuit

Info

Publication number
JPS6188636A
JPS6188636A JP59208188A JP20818884A JPS6188636A JP S6188636 A JPS6188636 A JP S6188636A JP 59208188 A JP59208188 A JP 59208188A JP 20818884 A JP20818884 A JP 20818884A JP S6188636 A JPS6188636 A JP S6188636A
Authority
JP
Japan
Prior art keywords
phase
output
multiplier
intermediate frequency
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59208188A
Other languages
Japanese (ja)
Inventor
Tsutomu Noda
勉 野田
Takao Shinkawa
新川 敬郎
Nobutaka Amada
信孝 尼田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59208188A priority Critical patent/JPS6188636A/en
Priority to KR1019850007082A priority patent/KR900000464B1/en
Priority to CA000492125A priority patent/CA1238952A/en
Priority to US06/783,521 priority patent/US4642573A/en
Publication of JPS6188636A publication Critical patent/JPS6188636A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/02Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
    • H03D3/24Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
    • H03D3/241Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop
    • H03D3/242Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop combined with means for controlling the frequency of a further oscillator, e.g. for negative frequency feedback or AFC
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D3/00Demodulation of angle-, frequency- or phase- modulated oscillations
    • H03D3/02Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
    • H03D3/24Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits
    • H03D3/241Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop
    • H03D3/245Modifications of demodulators to reject or remove amplitude variations by means of locked-in oscillator circuits the oscillator being part of a phase locked loop using at least twophase detectors in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/227Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H04L27/2272Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals using phase locked loops
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001Circuit elements of demodulators
    • H03D2200/0031PLL circuits with quadrature locking, e.g. a Costas loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16Multiple-frequency-changing
    • H03D7/161Multiple-frequency-changing all the frequency changers being connected in cascade

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To secure the stable demodulation with a both-side band wave signal having suppressed carrier wave by providing a reference oscillator equivalent to an intermediate frequency and detecting the difference of phase between the intermediate frequency and an input frequency by a COSTAS loop system to feed said phase difference back to a local oscillator together with a loop filter. CONSTITUTION:The signal applied to an input terminal 1 is converted into the 2nd intermediate frequency and supplied to the 1st and 2nd phase detectors 7 and 8 via a band pass filter 6 for comparison with the output of a reference oscillator 9 and a signal underwent a 90 deg. phase shift through a 90 deg. phase shifter 10 respectively. The output of both detectors 7 and 8 are added to a multiplier 19 for execution of multiplication, and the output of this multiplication is fed back to the 2nd local oscillator 4 via a loop filter 18. As a result, the 2nd intermediate frequency is used to the oscillator 9 to secure the stable characteristics.

Description

【発明の詳細な説明】 〔兄明のオリ用分野〕 本発明は復調回路に係り、特に搬送波抑圧内側帯波信号
の復調に際して安定に中間周波を釦生する回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a demodulation circuit, and particularly to a circuit that stably generates an intermediate frequency when demodulating a carrier-suppressed inner band signal.

〔発明の背景〕[Background of the invention]

従来の装置は、特開昭58−197944号に記載のよ
うに、搬送波の周波数変動の大きい伝送システムにおい
又も同期検波用の搬送波を再生できる。さらに特開昭5
8−156160−55においては同期検波周波数と位
相とを追従させて再生信号の誤り率の劣化を防いでいた
。しかし、ヘテロダイン受信機のように局S発掘器のド
リフトにともなう中間周波数のドリフトに対し℃固定の
中間周波数通過用バンドパスフィルタによる餓帯波の過
不足につい℃配慮され又いなかった。
As described in Japanese Patent Application Laid-Open No. 58-197944, the conventional device can regenerate a carrier wave for coherent detection even in a transmission system in which the carrier wave frequency fluctuates widely. Furthermore, JP-A-5
In No. 8-156160-55, the synchronous detection frequency and phase are tracked to prevent deterioration of the error rate of the reproduced signal. However, with respect to the drift of the intermediate frequency due to the drift of the station S excavator, as in the case of a heterodyne receiver, no consideration has been given to the excess or deficiency of the starvation band wave caused by the bandpass filter for passing the intermediate frequency, which is fixed at 0.degree.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、2相あるいは4相の位相シフトキーイ
ングなどの搬送波抑圧両側帯波信号な安定に復調するヘ
テロダイン受信慎の復調回w5を提供することにある。
An object of the present invention is to provide a demodulation circuit w5 for a heterodyne reception system that stably demodulates carrier-suppressed double-side band signals such as two-phase or four-phase phase shift keying.

〔発明の概要〕[Summary of the invention]

本発明は、中間Jta波数に相当する基準発振器ヲ設ケ
、コスタスループ方式で入力周波数との位相差を検出し
、ループフィルタを何して局部兄振器に′M!遺するこ
とで中間周波数を安定させることによる。
The present invention installs a reference oscillator corresponding to the intermediate Jta wave number, detects the phase difference with the input frequency using the Costas loop method, and uses the loop filter to generate 'M!' to the local oscillator. By stabilizing the intermediate frequency.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第1図により説明する。本図
は中間周波数に2つの周波数をもつ二電ヘテロダイン方
式でキャリアmi数を下げ。
An embodiment of the present invention will be described below with reference to FIG. This figure uses a two-electric heterodyne system with two intermediate frequencies to reduce the number of carriers mi.

4相位相シフトキーインク信号を復調する実施例である
。1は入力端子、2は慕1の局部発振器、3は第1の混
合器、4は第2の局部発振器。
This is an example of demodulating a four-phase phase shift key ink signal. 1 is an input terminal, 2 is a local oscillator of 1, 3 is a first mixer, and 4 is a second local oscillator.

5はN2の混合器、6はバンドパスフィルタ。5 is an N2 mixer, and 6 is a band pass filter.

7は第1の位相検波器、8は第2の位相検波器。7 is a first phase detector, and 8 is a second phase detector.

9は基準発振器、10は90°位相器、11は帛1の!
f4JE回N、  12 tX第2 ノ’14j足回M
、15 k?第I C1)復調出力、14は第2の傷調
出力、15は第1の乗算器、16はN2の乗算器、17
は減算器、18はループフィルタである。入力端子1に
与えられた信号と嵩1のwJ部発嶽器2とを第1の混合
器3を用いてビートダウンし第1の中間周波にする。そ
のホ1の中間局仮と第2の局sg振器4とを第2の混合
器5を用いてビートダウンし:第2の中間局仮にする。
9 is the reference oscillator, 10 is the 90° phase shifter, and 11 is the part 1!
f4JE times N, 12 tX 2nd no'14j foot times M
, 15k? 14 is the second modulation output, 15 is the first multiplier, 16 is the N2 multiplier, 17
is a subtracter, and 18 is a loop filter. A signal applied to an input terminal 1 and a bulky wJ part oscillator 2 are beat down using a first mixer 3 to produce a first intermediate frequency. The temporary intermediate station of E1 and the second station SG shaker 4 are beat down using the second mixer 5: they are made into a second temporary intermediate station.

バンドパスフィルタ6で不gな帯域外雑音、妨害などを
削除するとともに伝送路の特性を最通とするように波形
等化を行なう。その出力を嶌1の位相検波器7および薦
2の位相検波器8に加え、基準発振器9の位相と、その
出力を90°移相発10を通し、て90’位相のずれた
信号で0同期検波してそれぞれ0°の位相と90°の位
相でのベースバント化Jj4fcされる。それらの信号
を纂1の判定回路11および属2の判定回路12で1ま
7°%:は−1に利足され、21直のディジタル信号と
しておのおのN1の復調出力13と第2の復―出力14
に得る。。−万、謳1の位相@1fL器7の出力と継2
′の@足回路12の出力とを第1の乗昇615に加え、
その出力を減算器17の一方の入力とし1尾2の位′相
検&器8の出力と第1の判定回路11の出力どを第2の
乗算器16に加え、その出力をg算器17の他方の入力
とする。減算器17の出力をループフィルタ18をブト
して畠2の局部発振器4に帰還する。丁なわちjI!1
の乗丼器15.患2の乗算器16、減算器17およびル
ープフィルタ18で第1の位相検波器7および縞2の位
相@波番80入力であるN2の中1に8mと基準発振器
9の出力の位相差を検出し、N2のE4部発振器4を制
卸し℃、第2の中rI4J周阪と基$軸振器9の出力の
位相差をある一足値にする負帰還ルー1を構:戟するも
のである。位相差検出動作はtri開咄58−1979
44号に運られているためここでは省略する。基準発振
器9を水晶軸振器など周波数安定度の良い発振器を用い
れば、上記負帰還ルーズのため薦2の中間周波の周波数
が安定した値となり、第1の局部発振器2の周波数か温
度変動などによりドリフトしたとしても、褐2の中間局
波の周波数カ一定であり、バンドパスフィルタ6の中心
周波数とのずれか生じなく、安定した特性を得ることが
できる。
A bandpass filter 6 removes undesirable out-of-band noise, interference, etc., and performs waveform equalization to make the characteristics of the transmission path transparent. The output is added to the phase detector 7 of Shima 1 and the phase detector 8 of Shima 2, and the phase of the reference oscillator 9 and its output are passed through a 90° phase shifted oscillator 10, and a signal with a phase shift of 90' is 0. The signals are synchronously detected and converted to base band Jj4fc at a phase of 0° and a phase of 90°, respectively. These signals are added to 1 or 7% by -1 by the group 1 judgment circuit 11 and the group 2 judgment circuit 12, and are outputted as 21-digit digital signals to the N1 demodulation output 13 and the second demodulation output 13, respectively. Output 14
get to. . - 10,000, phase 1 @ output of 1fL device 7 and joint 2
′ and the output of the foot circuit 12 to the first multiplication 615,
The output is used as one input of the subtracter 17, the output of the 1-tail 2 phase detector & 17 is the other input. The output of the subtracter 17 is passed through a loop filter 18 and fed back to the local oscillator 4 of Hatake 2. Ding nawachijI! 1
Nooridon bowl 15. Multiplier 16, subtracter 17 and loop filter 18 of patient 2 calculate the phase difference between 8m and the output of reference oscillator 9 in N2 which is the first phase detector 7 and the phase of fringe 2 @ wave number 80 input. A negative feedback loop 1 is constructed to detect and control the E4 part oscillator 4 of N2 and make the phase difference between the output of the second intermediate rI4J oscillator and the base oscillator 9 a certain value. be. Phase difference detection operation is tri-opening 58-1979
Since it is carried by No. 44, it will be omitted here. If an oscillator with good frequency stability, such as a crystal shaft oscillator, is used as the reference oscillator 9, the frequency of the intermediate frequency of Recommendation 2 will be a stable value due to the negative feedback looseness described above, and the frequency of the first local oscillator 2 will change due to temperature fluctuations. Even if it drifts, the frequency of the brown 2 intermediate station wave remains constant, and only a deviation from the center frequency of the bandpass filter 6 occurs, making it possible to obtain stable characteristics.

なお、ルーの乗算器15および藁2め乗X器16の一方
の入力に十分なgミッタ効来かあれは萬1の判別回路1
1の出力および第2の判別回路12の出゛力からの信号
は第1の位相検波回路および;第2の位相検波回路出力
でも同一の動作を行なう。
Furthermore, whether the g-mitter effect is sufficient for one of the inputs of the Roux multiplier 15 and the Straw 2nd multiplier 16 is determined by the judgment circuit 1
The signals from the output of the first phase detection circuit 1 and the output of the second discrimination circuit 12 perform the same operation on the outputs of the first phase detection circuit and the second phase detection circuit.

本発明の他の実施例とL℃、2相位相シフトキーインク
信号を復調する実施物を慕2図に示す。第1図と同一符
号のものは同−一舵を示す。
Another embodiment of the present invention and an implementation for demodulating a L° C., two-phase phase shift key ink signal are shown in FIG. 2. The same reference numerals as in FIG. 1 indicate the same rudders.

19は乗算器である。入力端子1[与えられた信号は爲
2の中間周波に変換され、バッドパスフィルタ6を介し
て、諷1の位相検波器7および第2の位相検波#8に加
え、基準発振器9の出力および90°移相番10で90
°移相した信号と位相比較し、これら第1の位相検敦器
8および第2の位相@成語9の出力を乗算器19に加え
て栄算し、この出力をループフィルタ18を介1、″′
C第2の局部軸振器4に帰還する。その精来第2の中間
周波の周波数は基準軸振器90周波数になるため、安定
した特性が得られる。
19 is a multiplier. The signal given to input terminal 1 is converted to an intermediate frequency of 2, and is passed through a bad pass filter 6 to the output of the reference oscillator 9 and 90° phase shift number 10 is 90
The phase is compared with the phase-shifted signal, and the outputs of the first phase detector 8 and the second phase detector 9 are added to the multiplier 19 for multiplication, and this output is passed through the loop filter 18 to the ″′
C is fed back to the second local oscillator 4. Since the frequency of the second intermediate frequency is essentially the frequency of the reference shaft vibrator 90, stable characteristics can be obtained.

なお乗算器19の入力の一方はmlの位相慣波器7の出
力であるが、そのかわり[第1の判建@略11の出力で
も同僚な動作および効果を得る。
Note that one of the inputs of the multiplier 19 is the output of the phase incubator 7 of ml, but the same operation and effect can also be obtained with the output of the first phase incubator 7 instead.

〔発朋の動床〕[Hatsuho's moving bed]

本発明Kjれは、ヘテロダイン受信俄の中間jriJ阪
の周波数を安定にできるので、バンドパスフィルタによ
る側帯波の過不足を生じなく安だLベースバンド復調を
可能にする幼果がある。
The present invention has the advantage of making it possible to stabilize the intermediate frequency up to heterodyne reception, thereby enabling inexpensive L baseband demodulation without causing excess or deficiency of sidebands due to the bandpass filter.

さらに中間周波の周波数を安定にできるので。Furthermore, the intermediate frequency can be stabilized.

喘;屍餡58−136160号に記載されるようIL9
0゜移相器の8波数変化に対する補償も不要になる効果
もある。
Asthma; IL9 as described in Shianan No. 58-136160
This also has the effect of eliminating the need for compensation for the 8 wave number changes of the 0° phase shifter.

4 図面の?IJf単な読切 h−!、1図は本発明の一笑り例の10ツク図、絹2図
を工水発明の他の実施例のブロック図である。
4. Drawings? IJf simple one-shot h-! , Figure 1 is a 10 block diagram of a simple example of the present invention, and Figure 2 is a block diagram of another embodiment of the invention.

4・・・第2の局部づム振器 7.8・・・位相検Vt器 15 、16 、19・・・乗算器 手続補正書(自発) 事件の表示 昭和59 年特許願第 208188号発明の名称 復
調回路 補正をする者 事件との関係   特許  出 願 人名 称  (5
101株式会社 日 立 製作所式   理   人 1、 明細書第3頁第10行の「付して」を「介して」
に訂正する。
4...Second local vibration oscillator 7.8...Phase detector Vt device 15, 16, 19...Multiplier procedure amendment (spontaneous) Incident indication Patent application No. 208188 invention of 1982 Name Relationship to the case of person who corrects the demodulation circuit Patent applicant Name (5
101 Hitachi, Ltd. Style Person 1, “With” in line 10, page 3 of the specification, “through”
Correct.

2・ 明細書第4頁第16行の「移相器10」を「移相
器10」に訂正する。
2. Correct "phase shifter 10" on page 4, line 16 of the specification to "phase shifter 10."

& 明細書第7頁第9行と第10行の間に下記文章を加
入する。
& Add the following sentence between lines 9 and 10 on page 7 of the specification.

[ここで、本発明を中間周波数が少なく、選局用の局部
発振器に帰還をする場合の詳細な説明を加える。第5図
はそのプルツク図である。
[Here, a detailed explanation will be given of the case where the present invention has a small intermediate frequency and feeds back to a local oscillator for tuning. FIG. 5 is the pull diagram.

101は加算器、102は選局用に局部発振器を制御す
る選局用電圧発生器、103はスイッチ。
101 is an adder, 102 is a tuning voltage generator that controls a local oscillator for tuning, and 103 is a switch.

104は制御回路、105は制御電圧入力端子、106
は制御電圧出力端子である。
104 is a control circuit, 105 is a control voltage input terminal, 106
is the control voltage output terminal.

選局に際して制御回路104によりスイッチ103を開
き、′さらに選局用電圧発生器102の出力電圧を変化
させ、選局用電圧を加算器101を介してローカル発振
器2を制御して選局する。その後ループフィルタ1B出
力の位相誤差による制御電圧をスイッチ103を閉じて
加算器101を用いて選局用電圧に加えてローカル発振
器2を制御することで安定に選局および復調ができる。
At the time of channel selection, the control circuit 104 opens the switch 103, 'further changes the output voltage of the channel selection voltage generator 102, and controls the local oscillator 2 via the adder 101 to select the channel. Thereafter, by closing the switch 103 and adding the control voltage due to the phase error of the output of the loop filter 1B to the tuning voltage using the adder 101 to control the local oscillator 2, stable tuning and demodulation can be achieved.

」4. 明細書第8頁第1行の「ブロック図である。」
を、「ブロック図、第3図は本発明のさらに他の実施例
の一部のブロック図である。」に訂正する。
"4. "This is a block diagram" in the first line of page 8 of the specification.
is corrected to "Block diagram. FIG. 3 is a block diagram of a part of still another embodiment of the present invention."

5、 図面第3図を別紙の通り加入する。5. Add Figure 3 of the drawing as attached.

以上 第 3 図that's all Figure 3

Claims (1)

【特許請求の範囲】 1、混合器および局部発振器からなるヘテロダイン受信
機において、中間周波数に相当する基準発振器、90°
位相器、第1および第2の位相検波器、およびループフ
ィルタを設け、該基準発振滲出力を該第1の位相検波器
に加えるとともに該90°移相器を介して該第2の位相
検波器に加え、該第1および第2の位相検波器出力を該
乗算器に加え、該乗算器出力を該ループフィルタを介し
て該局部発振器に加えることを特徴とする復調回路。 2、特許請求の範囲第1項において、第1および第2の
判定回路、第1および第2の乗算器、減算器を設け、該
第1および第2の位相検波器出力をおのおの該第1およ
び第2の判定回路に加えるとともに、該第1の位相検波
器出力と該第2の判定回路出力とを該第1の乗算器に加
えかつ該第2の位相検波器出力と該第1の判定回路出力
とを該第2の乗算器に加え該第1および第2の乗算器の
一方の乗算値から他方の乗算値を該減算器にて減算し、
該ループフィルタを介して該局部発振器に加えることを
特徴とする復調回路。
[Claims] 1. In a heterodyne receiver consisting of a mixer and a local oscillator, a reference oscillator corresponding to an intermediate frequency, 90°
A phase shifter, first and second phase detectors, and a loop filter are provided, and the reference oscillation leakage output is applied to the first phase detector and the second phase detector is applied via the 90° phase shifter. a demodulation circuit, further comprising applying the first and second phase detector outputs to the multiplier, and applying the multiplier output to the local oscillator via the loop filter. 2. In claim 1, first and second determination circuits, first and second multipliers, and subtracters are provided, and the outputs of the first and second phase detectors are used to convert the outputs of the first and second phase detectors to the first and second determination circuits, respectively. and a second judgment circuit, and also adds the first phase detector output and the second judgment circuit output to the first multiplier, and adds the second phase detector output and the first judgment circuit output to the first multiplier. adding the determination circuit output to the second multiplier, and subtracting the other multiplication value from the multiplication value of one of the first and second multipliers in the subtracter;
A demodulation circuit characterized in that the demodulation circuit is applied to the local oscillator via the loop filter.
JP59208188A 1984-10-05 1984-10-05 Demodulation circuit Pending JPS6188636A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP59208188A JPS6188636A (en) 1984-10-05 1984-10-05 Demodulation circuit
KR1019850007082A KR900000464B1 (en) 1984-10-05 1985-09-26 A demodulation circuit
CA000492125A CA1238952A (en) 1984-10-05 1985-10-03 Demodulation circuit
US06/783,521 US4642573A (en) 1984-10-05 1985-10-03 Phase locked loop circuit for demodulating suppressed carrier signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59208188A JPS6188636A (en) 1984-10-05 1984-10-05 Demodulation circuit

Publications (1)

Publication Number Publication Date
JPS6188636A true JPS6188636A (en) 1986-05-06

Family

ID=16552117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59208188A Pending JPS6188636A (en) 1984-10-05 1984-10-05 Demodulation circuit

Country Status (1)

Country Link
JP (1) JPS6188636A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330049A (en) * 1986-07-23 1988-02-08 Hitachi Ltd Msk demodulation circuit
JPH01208942A (en) * 1988-02-16 1989-08-22 Matsushita Electric Ind Co Ltd Receiver

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4048566A (en) * 1976-01-05 1977-09-13 Motorola Inc. Suppressed carrier automatic gain control circuitry

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4048566A (en) * 1976-01-05 1977-09-13 Motorola Inc. Suppressed carrier automatic gain control circuitry

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6330049A (en) * 1986-07-23 1988-02-08 Hitachi Ltd Msk demodulation circuit
JPH01208942A (en) * 1988-02-16 1989-08-22 Matsushita Electric Ind Co Ltd Receiver

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