JPS6181664A - Mos field effect transistor - Google Patents

Abstract

PURPOSE:To prevent deterioration of Tr characteristic even when overetching is carried out to RIE by providing an insulating film which shows very low dry etching rate than that of oxide film to the upper surface and side surface of gate electrode and the source drain regions. CONSTITUTION:A field oxide film 8, a polycrystalline silicon layer 3, an n<-> layer 5 are formed on a silicon substrate 1. A silicon-added silicon nitride film 2 which is an insulating film showing very low dry etching rate than that of oxide film is formed on the upper surface and side surface of such polycrystalline silicon layer 3 (gate electrode) and the source drain region. Next, after forming a CVD oxide film, side wall 4 is formed by etching of entire part at RIE, an n<+> layer 6 is formed by the ion implantation and a contact through hole is formed by dry etching after forming an interlayer film 7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a MOS integrated circuit device.

[Conventional technology]

As the channel of the 1viO8 field effect transistor becomes shorter, the drain electric field increases, and carriers are injected into the gate oxide film, causing characteristic deterioration over time.

In particular, changes in characteristics such as the open-direction voltage of 2 gm of N-channel transistors due to hot electron injection are significant.This is a typical method for reducing the injection of hot carriers by relaxing the drain electric field in the device structure.
LDD (Lightly Doped D) as shown in
rain) structure.

gE2 diagrams (a) and (b) are MOS with LDD structure.
2A and 2B are cross-sectional views illustrating the structure of a type field effect transistor and a method for manufacturing the same.

First, as shown in FIG. 2(a), field oxidation 1x8.
A gate oxide film, a 6th and n layer 5 for forming a polycrystalline silicon layer 3 serving as a gate, is formed.

After that, CVD (Chemical Vapor De
pos-1tion) and RIE (Reactive
Leave a gold layer (such as an oxide film 5 or a polycrystalline silicon layer) on the side surface of the gate electrode using
(This is usually called a sidewall).

Next, as shown in FIG. 2(b), an n+ layer 6 is formed. In this case, a conventional MOa field effect transistor with an LDD structure can be obtained in which the n-layer lowers the substantial source-drain voltage and suppresses the injection of photocarriers into the gate oxide film.

[Problem that the invention seeks to solve]

In the above-mentioned LDD structure MOS field effect transistor, the formation of sidewalls takes into account variations in the thickness of the CVD oxide film during mass production, in-wafer processing of R and IE, variations in chipping, etc., and it is necessary to use extra BIE gold. must be done. However, during this over-etching, the silicon substrate in the source/drain regions is etched, causing source/drain junctions and leaks. There has been a problem in that as the channel length of MOS type field effect transistors becomes further shortened and the junction depth becomes shallower, jumps and leakage become more likely to occur.

In the present invention, when forming the entire sidewall on the gate electrode,
An object of the present invention is to provide a MOS type field effect transistor whose transistor characteristics do not deteriorate even when subjected to RIEi over-etching.

[Means for solving problems]

The MOS type field effect transistor of the present invention is characterized in that it has an insulating film on at least the upper surface and side surfaces of the gate electrode and the source/drain regions as well as the oxide film layer and the dry layer, which has a very high etching rate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are t-sectional views shown in order of steps to explain the structure and manufacturing method of one embodiment of the present invention.

First, as shown in FIG. 1Fa), the conventional example shown in FIG.
), the gate electrode formed by the same method as in (b), for example, the polycrystalline silicon layer 3 and the source/drain region n.
An oxide film or a silicon nitride film 2 is formed on the layer 5 by adding an insulating film, such as silicon, which has an extremely slow etching rate.Next, after forming a CVD film, such as a CVD oxide film, the entire surface is etched using a dry etching method. and side wall 4
t-form.

When forming this sidewall, even if dry etching gold is overetched, the dry etching speed of the insulating film 2 is extremely slower than that of the oxide film, so the silicon substrate surface 1
is never exposed.

Next, as shown in FIG. 2(b), n
After forming layer 6 by ion implantation, 7 cases of glabellar membrane, tbP
SGg is formed, and then a contact through hole is formed using a photoresist mask by dry etching and etching.

In this case as well, even if over-etching occurs, the silicon substrate surface will not be etched because of the presence of the insulating film 2, and therefore will not cause any defects or leaks. Next, the insulating film 2t'' of the contact portion is removed by wet etching to expose the silicon substrate surface, and then electrodes are formed.

As described above, the LLD has an insulating film 2 whose dry etching rate is extremely slow, and the oxide film F is formed on at least the top and side surfaces of the gate electrode 3 and the source/drain regions 5.6.
A goldstone MOS type field effect transistor is obtained.

[Effects of the Invention] 1. As explained above, the present invention is a very promising semiconductor device that has an LLD structure, does not generate junk or leakage, has a high yield, and has high reliability.

[Brief explanation of drawings]

13), [b) Fi A sectional view showing an embodiment of the present invention and its manufacturing method in order of steps, and FIGS. 2(a) and 2(b) show a conventional MOS field effect 1A and 1B are cross-sectional views shown in the order of steps to fully explain the structure of a transistor and its manufacturing method. 1... Silicon substrate, 2... Insulating film,
3...Polycrystalline silicon layer, 4...Side wall, 5...n single layer, 6...n
Layer 7...PEG interlayer film, 8...Field oxide film. Kyu l prison hair 2 figure

Claims (1)

[Claims] 1. A MOS field effect transistor comprising an insulating film whose dry etching rate is much slower than that of an oxide film on at least the upper and side surfaces of the gate electrode and the source/drain regions.