JPS6180860A - Power mosfet - Google Patents
Power mosfetInfo
- Publication number
- JPS6180860A JPS6180860A JP59201764A JP20176484A JPS6180860A JP S6180860 A JPS6180860 A JP S6180860A JP 59201764 A JP59201764 A JP 59201764A JP 20176484 A JP20176484 A JP 20176484A JP S6180860 A JPS6180860 A JP S6180860A
- Authority
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- Prior art keywords
- cell
- substrate
- gate
- source
- type layer
- Prior art date
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- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000003071 parasitic effect Effects 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 4
- 230000007423 decrease Effects 0.000 abstract description 3
- 101100447171 Arabidopsis thaliana FRO2 gene Proteins 0.000 abstract description 2
- 101100386221 Danio rerio dact1 gene Proteins 0.000 abstract description 2
- 101100120627 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FRD1 gene Proteins 0.000 abstract description 2
- 101150056585 DACT2 gene Proteins 0.000 abstract 1
- 101150042015 frd.2 gene Proteins 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000001172 regenerating effect Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
- H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はパワーＭＯＳＦＥＴにおける寄生バイポーラト
ランジスタ防止技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for preventing parasitic bipolar transistors in power MOSFETs.
パフ −Ｍ ＯＳ Ｆ Ｅ Ｔ Ｋは、横形オフセット
構造と、縦形Ｄ Ｓ Ａ （Ｄｉｆｆｕｓｉｏｎ ５ｅ
ｌｆ Ａｌｉｇｎｍｅｎｔ ）構造とがあり、このうち
、後者は多数の素子を平面上に縦横に等間隔にならべる
ことにより高耐圧化と大電流化が図られ、高電圧スイッ
チング用として使用されていることが知られている。（
工業調査会電子材料１９８１年９月号ｐ２２−２３）こ
の縦形ＤＳＡ構造のパワーＭＯＳＦＥＴは第３図に示す
ように、底部に高濃度ｎ 型層２を有するｎ−型シリコ
ン基板１をドレインとし℃、その表面上の一部に絶縁膜
４を介して設けたゲート（ポリＳ１ゲート）５をマスク
にセル７アライン拡散したｐ型層３及びｎ 型層（ソー
ス）６を形成したもので、ゲートへの電圧印加によって
ゲート下のｐ型層（チャネル部）３ａを通るソース・ド
レイン電流ＩＳＤを制御するようにＭ ＯＳ Ｆ Ｅ
Ｔを動作させるものである。Puff-MOSFETK has a horizontal offset structure and a vertical DSA (Diffusion 5e
lf alignment) structure, of which the latter has a high withstand voltage and a large current by arranging a large number of elements on a plane at equal intervals vertically and horizontally, and is used for high voltage switching. Are known. (
Industrial Research Group Electronic Materials, September 1981 issue, p. 22-23) As shown in Fig. 3, this vertical DSA structure power MOSFET uses an n-type silicon substrate 1 having a high concentration n-type layer 2 at the bottom as a drain. , a p-type layer 3 and an n-type layer (source) 6 are formed by aligning and diffusing the cell 7 using a gate (poly S1 gate) 5 provided on a part of the surface via an insulating film 4 as a mask. The source/drain current ISD passing through the p-type layer (channel part) 3a under the gate is controlled by applying a voltage to the MOS F E
This is what makes T operate.
この縦形ＤＳＡ構造のパワーＭＯ３ＦＥＴに内蔵されて
いるダイオード（ｐ型層５とｎ型基体１との間の接合ダ
イオード）をフライホイールダイオードＦＲＤ、として
積極的に利用するＤＣ／ＡＣインバータプリンジ回路に
おいては第５図に示すように対偶のＭＯＳＦＥＴである
Ｑ、、’Ｑ。In a DC/AC inverter spring circuit that actively utilizes the diode (junction diode between the p-type layer 5 and n-type substrate 1) built in the power MO3FET with this vertical DSA structure as a flywheel diode FRD, As shown in FIG. 5, the pair MOSFETs Q, ,'Q.
とＱ、、Ｑ、とが交互にス・ｆノチング動作するように
構成されるが、その場合ＦＲＤ、の他にバイポーラトラ
ンジスタに、、に、（第３図）が寄生しやす（、Ｆ Ｒ
Ｄ ｔに大電流を流すと、オン、オフの非定常時にバイ
ポーラトランジスタに１ 、Ｋ。and Q, ,Q, are configured to perform an alternating S-f notching operation, but in that case, in addition to the FRD, the bipolar transistor (Fig. 3) is likely to be parasitic (,F R
When a large current is passed through Dt, 1,K flows through the bipolar transistor during unsteady on and off states.
がオンしてセル周辺部に電流集中し素子の破壊が生じる
。turns on, current concentrates around the cell, and the device is destroyed.
このような寄生バイポーラトランジスタをオンさせない
手段とし℃、回路上において、ＭＯ３ＦＥＴ自身のＦＲ
Ｄｔの他に、並列に外付けのＦＲＤを挿入することが考
えられるが、これには高耐圧で電流容量の犬ざいものが
必要であり、接続加工が加わり構造的にも複雑になるな
どの問題がある。As a means to prevent such parasitic bipolar transistors from turning on, the MO3FET's own FR is
In addition to Dt, it is possible to insert an external FRD in parallel, but this requires a device with a high withstand voltage and current capacity, and requires connection processing, making the structure complicated. There's a problem.
不発明は上記の問題を克服するためになされたものであ
り、その目的とするところは、パワーＭＯＳＦＥＴにお
ける寄生バイポーラトランジスタによる電流集中をなく
シ、破壊耐量を向上することにある。The invention was made to overcome the above problems, and its purpose is to eliminate current concentration caused by the parasitic bipolar transistor in the power MOSFET and to improve breakdown resistance.
本願におい又開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基体表面に複数のＭＯＳセルを有し、
基体表面上にソース用及びゲート用のポンディングパツ
ドが設けられたパワーＭＯ３ＦＥＴであって、上記ソー
ス用又は及びゲート用ポンディングパッド直下の基体表
面に比較的に太ぎいダイオードを形成することにより、
ＭＯＳＦＥＴに寄生する内部ダイオードに流れる電流を
減少させ、破壊耐量を向上させて発明の目的を達成でき
る。That is, it has a plurality of MOS cells on the surface of the semiconductor substrate,
A power MO3FET in which source and gate bonding pads are provided on the surface of the substrate, and by forming a relatively thick diode on the substrate surface directly below the source and gate bonding pads. ,
The object of the invention can be achieved by reducing the current flowing through the internal diode parasitic to the MOSFET and improving breakdown resistance.
第１図及５第２１１発ｑ′）一実施例′示すも
１のであって、第１図はｎチャネルパワーＭＯ３ＦＥ
Ｔチップの全体平面図、第２図は第１図における人−Ａ
′視断面図である。同図において、１はドレイン部とな
るｎ−型シリコン基板、（チップ）２ ｋｉ ｎ＋型拡
散シリコン層でこの裏面にドレイン電極が形成される。Figures 1 and 5 No. 211 q') An embodiment' is shown.
1, and FIG. 1 shows an n-channel power MO3FE.
The overall plan view of the T-chip, Figure 2 is the person-A in Figure 1.
FIG. In the figure, reference numeral 1 denotes an n-type silicon substrate serving as a drain portion, and (chip) 2 denotes an n+-type diffusion silicon layer on the back surface of which a drain electrode is formed.
４はゲート絶縁膜、たとえばうすいＳｉｎ、膜でこの上
にポリシリコンゲート電極５が形成される。３はチャネ
ル部となるｐ型層。Reference numeral 4 denotes a gate insulating film, for example a thin Si film, on which a polysilicon gate electrode 5 is formed. 3 is a p-type layer that becomes a channel portion.
６はソースとなるｎ１型層でこれらｐ型層３及びｎ＋型
層６はゲート５をマスクとして不純物２重拡散を行うこ
とによりセル７アライン（自己整合的）にチャネル長を
規定することができる。これらｐ型層及びンースｎ＋型
層６を１つのセルフとして第１図に示すように複数のセ
ルを縦横に配列したＭ ＯＳセル部が形成される。Reference numeral 6 denotes an n1 type layer which serves as a source, and the channel length of the p type layer 3 and n+ type layer 6 can be defined in the cell 7 alignment (self-aligned manner) by performing double impurity diffusion using the gate 5 as a mask. . A MOS cell section is formed in which a plurality of cells are arranged vertically and horizontally as shown in FIG. 1, with these p-type layer and n+-type layer 6 as one cell.
８はアルミニウムソース電極であって、各セルフのコン
タクト部に接続され、その一部はソース用ポンディング
パッド８Ａとしてその上に金ワイヤ１２がポンディング
される。Reference numeral 8 denotes an aluminum source electrode, which is connected to the contact portion of each self, and a part of which serves as a source bonding pad 8A, on which a gold wire 12 is bonded.
９はアルミニウムゲート電極（配線）でポリシリコンゲ
ート５にスルーホール部’ａ’Ａ シテ：Ｉ ンタクト
され、その一部はゲート用ポンディングパッド９Ａとし
てその上に金ワイヤ１２がポンディングされる。Reference numeral 9 denotes an aluminum gate electrode (wiring) which is in contact with the polysilicon gate 5 through the through-hole section 'a'A', and a part of it is used as a gate bonding pad 9A and a gold wire 12 is bonded thereon.
１０はポンディングパッド８Ａ、９Ａの直下の基板表面
に形成したｐ型層、１１はｐ型層１０の表面の一部に形
成したｎ＋型層でこのｐ型層１０とｎ−型基板１この間
のｐｎ接合がフライホイルドダイオードＦＲＤ１ とし
て構成される。１３はＦＲＤ、とアルミニウム配ｍ（電
極）とのコンタクト部である。10 is a p-type layer formed on the surface of the substrate directly under the bonding pads 8A and 9A, and 11 is an n+-type layer formed on a part of the surface of the p-type layer 10 between this p-type layer 10 and the n-type substrate 1. The pn junction of is configured as a flywheel diode FRD1. 13 is a contact portion between the FRD and the aluminum wiring (electrode).
このＦＲＤ、は通常のＭＯ３ＦＥＴプロセスで各セルの
ｐ型層５ｎ＋型層６を形成するのと同じ拡散工程により
形成する。このＦＲＤ、はセル自体のもつＦＲＤ、と同
じレベルのスピードヲモつように設計され、このＦＲＤ
、の耐圧はセルとセルとの間のピンチオフを利用し、セ
ルと同等以上の耐圧を有する。This FRD is formed by the same diffusion process as that used to form the p-type layer 5n+-type layer 6 of each cell in a normal MO3FET process. This FRD is designed to have the same level of speed as the FRD of the cell itself, and this FRD
, utilizes pinch-off between cells, and has a breakdown voltage equal to or higher than that of cells.
以上実施例で述べた本発明によれば下記の理由により発
明の効果が得られる。According to the present invention described in the embodiments above, the effects of the invention can be obtained for the following reasons.
第６図は第２図で示される一つのセルに対応する等価回
路図である。ＦＲＤ、はドレインｎ−型基板とソース電
極との間に設けられたｐ型磨１０による共通のフライホ
イルダイオードである。FIG. 6 is an equivalent circuit diagram corresponding to one cell shown in FIG. 2. FRD is a common flywheel diode with a p-type layer 10 placed between the drain n-type substrate and the source electrode.
第７図は一つのセルに対応する部分での電流の状態を示
す断面図である。FIG. 7 is a cross-sectional view showing the state of current in a portion corresponding to one cell.
同図に示すようにソースからドレインへ流ス順方向電流
（ＩＦ） のＭＯＳセル部に流れる絶対分をＦＲＤ、
からＦＲＤ、に流すことでＭＯ３ＦＥＴ全体に流れるＩ
Ｆを低減する。これにより、回生電流ＩＤＲを減少して
破壊耐量を向上する。すなわち、ＭＯＳＦＥＴの破壊は
工、によって決定されるから、第４図を参照し、■、が
減少した分だけＩＤＲも減少し破壊耐量を向上すること
ができる。As shown in the figure, the absolute portion of the forward current (IF) flowing from the source to the drain in the MOS cell is expressed as FRD.
I flows through the entire MO3FET by flowing from FRD to FRD.
Reduce F. This reduces the regenerative current IDR and improves breakdown resistance. In other words, since the breakdown of the MOSFET is determined by the factor , as shown in FIG. 4, the IDR decreases by the amount of decrease in , and the breakdown resistance can be improved.
本発明者の実験圧よれば、ＭＯＳＦＥＴ（素子）の破壊
耐量はＦＲＤｌを形成しない場合に比して２〜３倍向上
させることが確認された。According to the experimental pressure of the present inventor, it was confirmed that the breakdown strength of the MOSFET (device) is improved by 2 to 3 times compared to the case where FRDl is not formed.
なお、ソース用及びゲート用のボンディングパッド直下
には通常ＭＯＳセルが形成されないから、この領域にダ
イオードＦＲＤ、を形成することは可能であり、その場
合、各セルの拡散プロセスをそのまま利用すればよく新
たな工程が加えられることがない。Note that since MOS cells are not normally formed directly under the source and gate bonding pads, it is possible to form a diode FRD in this region, and in that case, the diffusion process for each cell can be used as is. No new processes are added.
以上本発明によってなされた発明を実施例にもとづぎ具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもなＸ、１゜
たとえばＦＲＤｌをチップの中央に配置すれば一層効果
がある。ただし、その場合、ソースやゲートなどのポン
ディングパッドを中央位置に集めて配置しておく必要が
ある。Although the invention made by the present invention has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say, if X is 1°, for example, FRDl is placed in the center of the chip, it will be more effective. However, in this case, it is necessary to place the bonding pads such as the source and gate in a central location.
本発明は主としてモータコントロール用パワーＭＯ３Ｆ
ＥＴに適用する場合に有効である。The present invention mainly focuses on power MO3F for motor control.
This is effective when applied to ET.
第１図は本発明の一実施例を示す縦形ＤＮＡ構造０″ワ
−ＭＯＳＦＥＴＯチ″全体平面図・第 １
２図は第１図におけるＡ−Ａ’視折断面図ある。
第３図はこれまでの縦形ＤＳＡ！造パワーＭＯＳＦＥＴ
の縦断面図である。
第４図はパワーＭ ＯＳ Ｆ Ｅ Ｔの順方向電流ＩＦ
と回生電流ＩＤＲの形態を示す曲線図である。
第５図はＤＣ／八Ｃへンバータプリクジ回路の例を示す
回路図である。
第６図は第２図に示すパワーＭ ＯＳ Ｆ Ｅ Ｔの等
価回路図である。
第７図は一つのセルに対応する部分での電流状態を示す
断面図である。
１・・・ｎ−型ンリコン基板（ドレイン）、３・・・ｐ
型層（チャネル部）、４・・・ゲート絶縁膜、５・・・
ポリシリコンゲート、６・・・ｎ＋型層（ソース）、７
・・・セル、８・・・アルミニウム’７ｔＣ極（ソース
） 、９・・・アルミニウム電極（ゲー１−）、１０・
・・ｐ型層（ＦＲＤ、）。
第 １ 図
第 ３ 図
第 ４ 図
第 ５ 図FIG. 1 is an overall plan view of a vertical DNA structure 0"W-MOSFETO CH" showing one embodiment of the present invention.
FIG. 2 is a sectional view taken along the line AA' in FIG. Figure 3 shows the conventional vertical DSA! manufactured power MOSFET
FIG. Figure 4 shows the forward current IF of the power MOSFET.
FIG. 3 is a curve diagram showing the form of regenerative current IDR. FIG. 5 is a circuit diagram showing an example of a DC/8C converter converter circuit. FIG. 6 is an equivalent circuit diagram of the power MOSFET shown in FIG. 2. FIG. 7 is a cross-sectional view showing the current state in a portion corresponding to one cell. 1...n-type silicon substrate (drain), 3...p
Type layer (channel part), 4... gate insulating film, 5...
Polysilicon gate, 6... n+ type layer (source), 7
... Cell, 8... Aluminum '7tC electrode (source), 9... Aluminum electrode (Ge 1-), 10.
...p-type layer (FRD, ). Figure 1 Figure 3 Figure 4 Figure 5
Claims (1)
面上にソース用及びゲート用ボンディングパッドが設け
られたパワーＭＯＳＦＥＴであって、上記ソース用又は
及びゲート用ボンディングパッド直下の基体表面にＭＯ
ＳＦＥＴに寄生する内部ダイオードに流れる電流を減少
するようにダイオードが形成されていることを特徴とす
るパワーＭＯＳＦＥＴ。 ２、上記ダイオードはＭＯＳＦＥＴの各セルを形成する
拡散層と同じ拡散工程により形成されたものである特許
請求の範囲第１項に記載のパワーＭＯＳＦＥＴ。[Claims] 1. A power MOSFET having a plurality of MOS cells on the surface of a semiconductor substrate and having bonding pads for a source and a gate on the surface of the substrate, wherein the bonding pad for the source or the bonding pad for the gate is provided on the surface of the substrate. MO on the substrate surface directly below
A power MOSFET characterized in that a diode is formed so as to reduce the current flowing through an internal diode parasitic to the SFET. 2. The power MOSFET according to claim 1, wherein the diode is formed by the same diffusion process as the diffusion layer forming each cell of the MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201764A JPS6180860A (en) | 1984-09-28 | 1984-09-28 | Power mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201764A JPS6180860A (en) | 1984-09-28 | 1984-09-28 | Power mosfet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6180860A true JPS6180860A (en) | 1986-04-24 |
Family
ID=16446544
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59201764A Pending JPS6180860A (en) | 1984-09-28 | 1984-09-28 | Power mosfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6180860A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164474A (en) * | 1986-12-26 | 1988-07-07 | Matsushita Electronics Corp | Vertical mos field-effect transistor |
| JPH02283074A (en) * | 1989-04-25 | 1990-11-20 | Fuji Electric Co Ltd | Semiconductor integrated circuit device |
| JPH0521804A (en) * | 1991-07-12 | 1993-01-29 | Matsushita Electric Works Ltd | Insulated gate type field effect semiconductor device |
| EP0567341A1 (en) * | 1992-04-23 | 1993-10-27 | Siliconix Incorporated | Power device with isolated gate pad region |
| US5304831A (en) * | 1990-12-21 | 1994-04-19 | Siliconix Incorporated | Low on-resistance power MOS technology |
| US5404040A (en) * | 1990-12-21 | 1995-04-04 | Siliconix Incorporated | Structure and fabrication of power MOSFETs, including termination structures |
| JP2006253636A (en) * | 2005-02-10 | 2006-09-21 | Sanken Electric Co Ltd | Semiconductor element |
| WO2010061244A1 (en) * | 2008-11-27 | 2010-06-03 | Freescale Semiconductor, Inc. | Power mos transistor device and switch apparatus comprising the same |
| WO2010061245A1 (en) | 2008-11-27 | 2010-06-03 | Freescale Semiconductor, Inc. | Power mos transistor device |
| US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
| US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
| US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
-
1984
- 1984-09-28 JP JP59201764A patent/JPS6180860A/en active Pending
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164474A (en) * | 1986-12-26 | 1988-07-07 | Matsushita Electronics Corp | Vertical mos field-effect transistor |
| JPH02283074A (en) * | 1989-04-25 | 1990-11-20 | Fuji Electric Co Ltd | Semiconductor integrated circuit device |
| US5304831A (en) * | 1990-12-21 | 1994-04-19 | Siliconix Incorporated | Low on-resistance power MOS technology |
| US5404040A (en) * | 1990-12-21 | 1995-04-04 | Siliconix Incorporated | Structure and fabrication of power MOSFETs, including termination structures |
| US5429964A (en) * | 1990-12-21 | 1995-07-04 | Siliconix Incorporated | Low on-resistance power MOS technology |
| US5521409A (en) * | 1990-12-21 | 1996-05-28 | Siliconix Incorporated | Structure of power mosfets, including termination structures |
| JPH0521804A (en) * | 1991-07-12 | 1993-01-29 | Matsushita Electric Works Ltd | Insulated gate type field effect semiconductor device |
| EP0567341A1 (en) * | 1992-04-23 | 1993-10-27 | Siliconix Incorporated | Power device with isolated gate pad region |
| US5430314A (en) * | 1992-04-23 | 1995-07-04 | Siliconix Incorporated | Power device with buffered gate shield region |
| US5445978A (en) * | 1992-04-23 | 1995-08-29 | Siliconix Incorporated | Method of making power device with buffered gate shield region |
| JP2006253636A (en) * | 2005-02-10 | 2006-09-21 | Sanken Electric Co Ltd | Semiconductor element |
| JP4572795B2 (en) * | 2005-02-10 | 2010-11-04 | サンケン電気株式会社 | Insulated gate bipolar transistor |
| WO2010061244A1 (en) * | 2008-11-27 | 2010-06-03 | Freescale Semiconductor, Inc. | Power mos transistor device and switch apparatus comprising the same |
| WO2010061245A1 (en) | 2008-11-27 | 2010-06-03 | Freescale Semiconductor, Inc. | Power mos transistor device |
| US8530953B2 (en) | 2008-11-27 | 2013-09-10 | Freescale Semiconductor, Inc. | Power MOS transistor device and switch apparatus comprising the same |
| US8604560B2 (en) | 2008-11-27 | 2013-12-10 | Freescale Semiconductor, Inc. | Power MOS transistor device |
| US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
| US9935193B2 (en) | 2012-02-09 | 2018-04-03 | Siliconix Technology C. V. | MOSFET termination trench |
| US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
| US10229988B2 (en) | 2012-05-30 | 2019-03-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
| US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
| US10340377B2 (en) | 2014-08-19 | 2019-07-02 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
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