JPS617970A - Data transfer control method - Google Patents

Abstract

PURPOSE:To reduce the generation of an ineffective polling by sending an address equipment number to a host device by following a status of a low order device, and setting a command change time to a time zone which precedes sending-out of a command by the host device. CONSTITUTION:When a host device 1 selects an optional device of plural low order devices 2, the host device 1 sends out a selecting signal onto a line 12 from its address equipment number transmitting part 4, and simultaneously, sends out a device DV address equipment number onto a bus-out 19. The low order device 2 receiving the selecting signal sends back a stack status being a device status and subsequently the DV address equipment number to the bus line 20. In parallel to this sending, a logical coupling signal SLACI on a line 14 is returned to the host device 1, and also an address equipment number of the low order device is answered together with a status signal TGREP through a line 15. The time extending from the time for decoding this signal TGREP to the time when an READ command and a read tag are sent out to the bus-out 19 and a tag line 13, respectively is a command change time for the host device 1.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a data transfer control system, and particularly to a data transfer control system that reduces invalid polling of lower-level devices and uses the same logic as when selecting a lower-level device to determine the end of a command. The present invention relates to a data transfer control method that enables confirmation.

(0) Technical background In a system that transfers data, if the configuration is such that multiple lower-level devices can be connected to the higher-level device through or without intermediate devices, one It will be connected only to lower-level devices and data will be transferred. Prior to such data transfer, a connection relationship must be established between the higher-level device and the lower-level device.

In this case, since the lower-level device that the higher-level device attempts to select is not always in a connectable state, invalid connection processing (polling) may occur.

Also, if the connection relationship as described above is successfully established, point 9.
It is also necessary to accurately confirm the completion of a command after execution of the command in order to ensure the reliability of data transfer.

There is a desire to easily realize such requirements.

(c) Prior art and problems In the conventional interface between a central processing unit and multiple input/output devices connected to it, data must be sent from the input/output device to the central processing unit before the two devices are connected. The address machine number and device status information are sent with the address machine number first. The status sent in this way can only be known for a short period of time from when the selection signal is sent until the address machine number is returned, and since there is no time to take countermeasures against this, the above-mentioned method is used. In this case, invalid polling occurs more frequently.

Furthermore, since only the device status is sent to the central processing unit at the end of command execution in such an interface, there is a lack of confirmation of the end.

Object of the Invention The present invention has been made in view of the above-mentioned drawbacks of the conventional techniques, and its purpose is to reduce the occurrence of invalid polling, perform high-speed and efficient polling, and ensure command completion. The object of the present invention is to provide a data transfer control method that allows easy confirmation.

(→Structure of the InventionAnd, in order to achieve this objective, the inventive method of Invention Box 1 is to Following the status, the address machine number is sent to the higher-level device, while the command change time is set in a time period preceding the sending of the command by the higher-level device.The second method of the invention is as follows. Subsequently, at the end of command execution, the address machine number is returned to the higher-level device following the status of the lower-level device in the same order as at the time of selection.

(F) Embodiments of the Invention The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. This embodiment is a technique that has already been proposed by the applicant under the name "logical connection method" (patent application No. 1), in which a higher-level device (channel) and a lower-level device (input/output control device) are logically connected. This is what is being carried out inside. In FIG. 1, the upper device 1 is on the left side of the dashed line shown in the center, and the lower device 2 is on the right side. The host device 1 includes a connection signal transmitting section 3, an address machine number transmitting section 4, a command transmitting section 5, and a transfer sequence section 6, which constitute the main parts of the present invention. The lower device 2 includes an address machine number selection section 7, an instruction decoding section 8, a transfer sequence section 9, and a status signal return section IO, which constitute the main parts of the present invention. Between these devices there are control signal lines and bus out and bus in, which will be described below. A 5TART signal line 11 is connected from the connection signal transmitter 3 to the required parts of the lower-order device. Further, a selection signal (SLCTI) line 12 from the address machine number transmitter 4 and a tag (TAG) line 13 from the command sender 5 are connected to the address machine number selector 7, and from there to the command sender 6. A logical combination signal (SLACI) line 14 is connected.

A status signal (TGREP) line 15 is also connected to the command sending unit 5 from the status signal return unit 1o. The instruction sending section 5 is also connected to the transfer sequence section 6 via a line 16, and its tag line 13 is connected to the instruction decoding section 8 and the status signal returning section 10. The instruction decoding section 8 is connected to the transfer sequence section 9 via a line 17. The transfer sequence section 9 is connected via a line 18 to a status signal return section 10.

The bus out 19 from the transfer sequence section 6 to the transfer sequence section 9 is transferred from the transfer sequence section 9 to the transfer sequence section 6.
Hebusin 20 is connected.

These bus out 19 and bus in 2o are 21°22
It is also used to transfer various information for data transfer in synchronization with the control signal line signal.

Next, how the features of the present invention are exhibited under the above configuration will be explained with reference to FIGS. 2 and 3.

When a higher-level device 1 attempts to select an arbitrary lower-level device from a plurality of lower-level devices 2 connected to the higher-level device 1, the higher-level device 1
sends out a selection signal from its address machine number transmitter 4 onto the line 12 (see (1) in Figure 3), and also sends out a selection signal to the bus out 1
The device address machine number (DV address machine number) is sent to the device address number 9 (see (3) in FIG. 3). The lower device that has received the above-mentioned selection signal returns the stack status, which is the device status, and subsequently the DV address machine number to the bus-in 20, as shown in (6) in FIG. By adopting such a device status return method, conventionally only the lower device status from the time of sending the selection signal to the time of returning the DV address machine number could be returned to the upper device, but now it is possible to return more statuses than necessary. can be returned.

In parallel with the return of such lower-level status, when an arbitrary lower-level device is selected by the "logical combination method" already proposed by the applicant as described above, the line 14
The logical combination signal 5LACI is returned to the host device (see (5) in FIG. 3), and the status signal TGR is sent via line 15.
It responds with the lower device address machine number along with the EP (see (7) in FIG. 3). The time from the time when this status signal TGREP is decoded to the time when a READ command and read tag are sent to the bus out 19 and tag line 13, which will be described later, is the command change time (program margin) for the host device. This makes it possible to provide the system with functions such as those described below.

When the above-described status signal TGREP is received by the higher-level device 1, the higher-level device 1 sends a connection signal 5TART to the lower-level device 2 via the line 11 (see (8) in FIG. 3).

After a time period determined by the processing has elapsed from the time when the connection signal 5TART reaches the amplifier level, commands such as a READ command and a read tag are sent to the bus out 19 and the tag line 13, respectively, and the required reading begins.

As mentioned above, one of the characteristics of the present invention is that the lower status is returned before the DV address machine number is returned, and that the above-mentioned program margin is provided. By doing this, the receiver can change the command that it was about to send to the lower-level device to another appropriate command depending on the lower-level status it has acquired. This results in
The number of invalid polls can be reduced, and polling can be performed quickly and efficiently.

The above reading is shown in FIG. 3 001. As shown in (9), the process is performed while the response signal 5YINI from the lower device 2 and the request signal 5OUTI from the higher device 1 are alternately transmitted. And once the reading is complete,
The command on bus out 19 is a 5kip command and a 5kip tag is generated on tag line 13. This 5
The lower device 2 responding to the kip tag returns a status signal TGREP indicating DVEND to the upper device, and also returns the end status (device status) and DV address machine number to the higher device 1 via the bus-in 20 during that time. By returning this lower status and the DV address machine number, the completion of the command can be reliably confirmed with a simple configuration (same logic).

In response to the rise of the above-mentioned DVEND display, the host device l
A connection signal 5TART and a request signal 5YOUT are sent from the terminal, and these high levels and a status signal TGRE
In response to the fall of P, the logical combination signal 5LACI is dropped to complete the series of controls.

Here, when the higher-level device continues the command in the command chain, the lower-level device jumps to a specific address while keeping the connection signal 5TART raised. After editing the status, the device is started up again. Once again, the connection signal 5TART is activated when the logical combination is completed.
and wait until the DV address machine number is responded.

The following is the same as when a command is issued. This is another feature of the invention.

The features of the present invention as described above include a disconnection sequence during connection (Figure 4), a disconnection sequence during non-connection (Figure 5), a busy sequence (Figure 6), and a system clear sequence (Figure 7). It has also been utilized in the past, except for its characteristic part, which is different from the conventional method in that it performs time-division 4-byte transfer, and its operation mode will become clear if you observe it according to Figure 3, which shows the normal sequence. The detailed explanation will not be repeated.

In addition, the features described above can be applied in exactly the same way between the upper device and the intermediate device and between the intermediate device and the lower device when an intermediate device is provided between the upper device and the lower device. It is something. Further, the upper device and the lower device may be selected from, for example, a CPU, a channel, an input/output control device, and an input/output device in a computer system, and any pair between these orders.

(G) Effects of the Invention As described above, according to the present invention, ■ it is possible to prevent the occurrence of invalid polling and perform high-speed and efficient polling, and ■ in addition to this, it is easy to finish command execution. Effects such as being able to reliably confirm the information with a simple configuration can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part configuration of an embodiment of the present invention, FIG. 2 is a diagram showing a signal system between a higher-level device and a lower-level device, and FIG.
The figure is a timing chart of a normal sequence, Figure 4 is a timing chart of a disconnect sequence during connection, Figure 5 is a timing chart of a disconnect sequence during non-combination, Figure 6 is a timing chart of a busy sequence, and Figure 7 is a timing chart of a disconnect sequence during connection. is a timing chart of the system reset sequence. In the figure, 1 is a higher-level device, 2 is a lower-level device, 3 is a connection signal transmitter, 4 is an address machine number transmitter, 5 is a command transmitter, 6.9
8 is a transfer sequence section, 8 is an instruction decoding section, and lO is a status signal reply section.

Claims (2)

[Claims] (1) When selecting an arbitrary lower-level device from among multiple lower-level devices from a higher-level device in a system that performs data transfer, the address machine number is sent to the higher-level device following the status of the lower-level device; 1. A data transfer control method characterized in that a command change time is set in a time period preceding command sending by. (2) When a higher-level device in a system that performs data transfer selects an arbitrary lower-level device among a plurality of lower-level devices, the address machine number is sent to the higher-level device following the status of the lower-level device; The command change time is set in the time period preceding the command transmission, and at the end of command execution, the address machine number is returned to the upper device following the status of the lower device in the same order as when it was selected. Characteristic data transfer control method.