JPS6164129A - Resinous sealing type semiconductor device - Google Patents
Resinous sealing type semiconductor deviceInfo
- Publication number
- JPS6164129A JPS6164129A JP18593684A JP18593684A JPS6164129A JP S6164129 A JPS6164129 A JP S6164129A JP 18593684 A JP18593684 A JP 18593684A JP 18593684 A JP18593684 A JP 18593684A JP S6164129 A JPS6164129 A JP S6164129A
- Authority
- JP
- Japan
- Prior art keywords
- memory array
- eprom
- chip
- passivation film
- eprom chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000007789 sealing Methods 0.000 title abstract description 3
- 239000011347 resin Substances 0.000 claims abstract description 29
- 229920005989 resin Polymers 0.000 claims abstract description 29
- 238000002161 passivation Methods 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 16
- 239000011241 protective layer Substances 0.000 claims description 4
- 230000014759 maintenance of location Effects 0.000 abstract description 7
- 230000001681 protective effect Effects 0.000 abstract description 6
- 230000005055 memory storage Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 239000012466 permeate Substances 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 9
- 238000000465 moulding Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011796 hollow space material Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000010137 moulding (plastic) Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、樹脂封止型半導体装置、特に紫外線消去形Ｅ
ＰＲＯＭのプラスチックモールド樹脂パッケージ構造に
関するものである０
〔従来の技術〕
従来の紫外線消去形ＥＰＲＯＭのパッケージ構造に訃い
ては、ＥＰＲＯＭチップに書き込まれたメモリ情報を消
去てきるようにするために、紫外線透過窓付きパッケー
ジが用いられている。このパッケージの場合、紫外線透
過窓付きという特殊性のため、通常、セラミックパッケ
ージが使用され、その構造を第３図および第４図にそれ
ぞれ示す。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to resin-sealed semiconductor devices, particularly ultraviolet erasable type E
This relates to the plastic mold resin package structure of PROM. [Prior art] The conventional ultraviolet erasable EPROM package structure has been modified to use ultraviolet rays to erase the memory information written on the EPROM chip. A package with a transparent window is used. In the case of this package, a ceramic package is usually used because of its special feature of having an ultraviolet-transparent window, and its structure is shown in FIGS. 3 and 4, respectively.
第３図は、ＥＰＲＯＭチップ１０をセラミック容器１内
に固着し、そのチップ１０の各パッドとセラミック容器
１に装着されたり−ドピン２をボンディングワイヤ３に
よシ接続したうえ、このセラミック容器１の上面にセラ
ミック板４を接着ガラス５で接着することによシ、この
セラミック板４上の紫外線透過窓７を有する蓋６とＥＰ
ＲＯＭ １０との間を中空にしたもので、紫外線透過窓
付き蓋６を含む三層パッケージ構造が採られている。第
４図は、セラミック容器１上に紫外線透過窓９を有する
セラミック蓋８を接着ガラス５にて接着した二層パッケ
ージ構造を有し、第３図と同様に、セラミック蓋８とＥ
ＰＲＯＭ １０との間を中空にするものとなっている。In FIG. 3, an EPROM chip 10 is fixed in a ceramic container 1, each pad of the chip 10 and the pins 2 attached to the ceramic container 1 are connected by bonding wires 3, and the ceramic container 1 is By bonding the ceramic plate 4 to the top surface with adhesive glass 5, a lid 6 and an EP having an ultraviolet transmitting window 7 on the ceramic plate 4 are formed.
It has a hollow space between it and the ROM 10, and has a three-layer package structure including a lid 6 with an ultraviolet-transmitting window. FIG. 4 shows a two-layer package structure in which a ceramic lid 8 having an ultraviolet-transmitting window 9 is bonded to a ceramic container 1 using an adhesive glass 5. Similarly to FIG.
A hollow space is formed between the PROM 10 and the PROM 10.
また、他の従来例として、ここ数年注目されつつある紫
外線消去形ＥＰＲＯＭのプラスチック封止パッケージが
ある。この場合、紫外線透過窓がないため、書き込まれ
たメモリ情報を消去することができず、メモリ情報書き
込みは１回のみを想定している。このプラスチック封止
の紫外線消去形ＥＰＲＯＭは、リード７ンーム上にＥＰ
ＲＯＭチップを装着するとともにワイヤボンディングを
行った後、これらの全体をモールド樹脂にて封止したも
ので、このモールド樹脂はＥＰＲＯＭチップ上のメモリ
アレイ部および周辺回路部を有する側表面と直接接触す
るものとなっている。このプラスチック封止パッケージ
の紫外線消去形ＥＰＲＯＭは、紫外線透過窓付きパッケ
ージのものに比べてそのコストが安価になるため、メモ
ｌ情報の書き込みが１回のみに限る用途ではコスト的に
有利となる０〔発明が解決しようとする問題点〕
ところが、紫外線消去形ＥＰＲＯＭのメモリ保持特性、
耐温性等の長期信頼性特性は、ＥＰＲＯＭチップ表面の
パッシベーション膜特性トそのパッシベーション膜上に
位置するモールド樹脂の材質およびパッケージ形成時の
鋳型に流し込むモールド樹脂のＥＰＲＯＭチップ上ハツ
シベーション膜上への圧迫の度合い等によシ影響される
。そのため、従来の紫外線透過窓付きパッケージでＥＰ
ＲＯＭチップ上が中空になっている場合には問題になら
なかったＥＰ ＲＯＭのメモリ保持特性、書き込み特性
が、ＥＰＲＯＭチップとモールド樹脂とが接触するよう
なプラスチック封止パッケージにすると悪く々るという
問題点があった〇
本発明は、かかる問題点を解決するためになされたもの
で、モールド樹脂のＥＰＲＯＭチップへの悪影響を防止
してメモリ記憶保持特性の向上を図った樹脂封止型半導
体装置を得ることを目的とする０
〔問題点を解決するための手段〕
このような目的を達成するに、本発明は、ＥＰＲＯＭチ
ップ上のメモリアレイ部を除く周辺回路部分に、該周辺
回路を保護するパッシベーション膜と重ねて前記メモ＋
７７レイ部を包囲すべくパッシベーション膜な形成する
とともに、該周辺回路部分のパッシベーション膜上に前
記メモリアレイ部に対して中空を形成すべく保護層を重
ねて形成し、このＥＰＲＯＭ チップをプラスチックモ
ールド樹脂内に樹脂封止したものである。Further, as another conventional example, there is a plastic sealed package for an ultraviolet erasable EPROM, which has been attracting attention in recent years. In this case, since there is no ultraviolet transmitting window, the written memory information cannot be erased, and it is assumed that the memory information is written only once. This plastic-sealed UV-erasable EPROM has an EP on the 7 nm lead.
After mounting the ROM chip and performing wire bonding, the whole is sealed with molding resin, and this molding resin is in direct contact with the side surface of the EPROM chip that has the memory array section and peripheral circuit section. It has become a thing. This UV-erasable EPROM in a plastic sealed package is cheaper than one in a package with a UV-transparent window, so it is advantageous in terms of cost in applications where memory information can only be written once. [Problem to be solved by the invention] However, the memory retention characteristics of ultraviolet erasable EPROM,
Long-term reliability characteristics such as temperature resistance are determined by the characteristics of the passivation film on the surface of the EPROM chip, the material of the molding resin placed on the passivation film, and the amount of molding resin poured into the mold during package formation onto the passivation film on the EPROM chip. It is affected by the degree of pressure, etc. Therefore, it is possible to use EP in a conventional package with a UV-transparent window.
The problem is that the memory retention characteristics and write characteristics of EP ROM, which would not be a problem if the top of the ROM chip was hollow, become worse if the EPROM chip is packaged in a plastic seal where the mold resin comes into contact with it. The present invention has been made to solve these problems, and provides a resin-sealed semiconductor device that prevents the adverse effects of mold resin on EPROM chips and improves memory retention characteristics. [Means for Solving the Problems] To achieve such an object, the present invention provides a method for protecting the peripheral circuitry in the peripheral circuitry portion excluding the memory array portion on the EPROM chip. Add the above memo + with the passivation film
A passivation film is formed to surround the 77 array area, and a protective layer is formed on the passivation film of the peripheral circuit area to form a hollow space for the memory array area, and this EPROM chip is molded with plastic mold resin. The inside is sealed with resin.
本発明においては、ＥＰＲＯＭチップ上の周辺回路部分
のみにパッシベーション膜を積み重゛ね、さらにその上
に保護層を積み重ねることによシ、メモリアレイ部の上
部だけは中空となる。そのため、とのＥＰＲＯＭチップ
をプラスチックモールド樹脂に°よって封止する際にそ
のモールド樹脂はＥＰＲＯＭチップの少なくともメモリ
アレイ部分には直接接触することがなくなる。以下、本
発明の実施例を図面について説明する。In the present invention, by stacking a passivation film only on the peripheral circuit portion of the EPROM chip and further stacking a protective layer thereon, only the upper portion of the memory array portion becomes hollow. Therefore, when the EPROM chip is sealed with plastic molding resin, the molding resin does not come into direct contact with at least the memory array portion of the EPROM chip. Embodiments of the present invention will be described below with reference to the drawings.
第１図（、）および（ｂ）は本発明の一実施例を示す概
略断面図およびそのｇＦＲＯＭチップ部分の側面断面図
である０第１図に訃いて、ＥＰＲＯＭチップ１０は、第
２図に示すように、メモリアレイ部１１．１２と、周辺
回路１３と、ポンディングパッド１４から構成され、こ
のパッド１４の部分を除く各メモリアレイ部１１および
１２７周辺回路部１３の表面は通常のパッシベーション
膜（図示せず）で保直されている。そして、前記ＥＰＲ
ＯＭ １０上のポンディングパッド１４を除く周辺回路
部１３の表面には、そのパッシベーション膜に重ねてメ
モリアレイ部１１，１２を包囲すべくパッシベーション
ｉｔ、ｓが該メモリアレイ部分と高さの差を設けて形成
されている。また、この周辺回路部１３のパッシベーシ
ョン膜１５が厚くなった部分にはそれと同様の膜からな
る保護膜１６が被覆され、これらパンシベーション膜１
５．保誦膜１６によってＥＰ ＲＯＭチップ１０上の少
なくともメモリアレイ部１１．１２の上部に中空部１７
．１８がそれぞれ形成されている。1(a) and (b) are a schematic cross-sectional view showing one embodiment of the present invention and a side cross-sectional view of the gFROM chip portion of the same. As shown, it is composed of a memory array section 11, 12, a peripheral circuit 13, and a bonding pad 14, and the surface of each memory array section 11, 127 and peripheral circuit section 13, excluding the pad 14, is covered with a normal passivation film. (not shown). And the EPR
On the surface of the peripheral circuit section 13 excluding the bonding pads 14 on the OM 10, a passivation layer is formed so as to overlap the passivation film and surround the memory array sections 11 and 12 so as to have a height difference with the memory array section. It is provided and formed. Further, the thickened portion of the passivation film 15 of the peripheral circuit section 13 is covered with a protective film 16 made of a similar film.
5. A hollow portion 17 is formed at least above the memory array portion 11.12 on the EP ROM chip 10 by the protection film 16.
．． 18 are formed respectively.
このような構造のＥＰＲＯＭテップ１０は、その固定面
をＩｌ−ドフレーム２１上ＫＲ着して固定し、このチッ
プ１０の各ポンディングパッド１４とリードビン２２と
をボンディングワイヤ２３によシ接続したうえ、プラス
チックモールド樹脂２４で樹脂封止することＫよって、
第４図（＆）に示すパッケージ措造の紫外線消去形ＥＰ
ＲＯＭが得られる。The EPROM chip 10 having such a structure is fixed by bonding its fixed surface onto the Ild frame 21, and each bonding pad 14 of this chip 10 and the lead bin 22 are connected by bonding wires 23. , by resin sealing with plastic mold resin 24,
Ultraviolet erasable EP with package structure shown in Figure 4 (&)
A ROM is obtained.
このように、ＥＰＲＯＭチップ１０上の周辺回路部分１
３の上のみにパッシベーション膜１５を積み重ね、さら
にその上に保護膜１６を積み重ねることによシ、メモリ
アレイ部１１．１２の上部だけは中空部１７．１８とな
っておシ、このＥＰ ＲＯＭチップ１０をプラスチック
モールド樹脂２４で樹脂封止する際、このモールド樹脂
２４は、直接ＥＰＲＯＭチップ１０の少なくともメモリ
アレイ部１１．１２には接触しない。そのため、モール
ド樹脂の成分で、ＥＰＲＯＭのメモリ記憶保持特性に影
響を及ぼす汚染物がＥＰＲＯＭチップ１０のメモリアレ
イ部１１．１２に浸透することを防ぐことができる０−
！！た、前記モールド樹脂２４のＥＰ ＲＯＭチップ１
０のメモリアレイ部１１．１２への圧迫がなくなるため
、従来のＥＰＲＯＭチップ接触モールド樹脂パッケージ
で、不良原因のひとつ罠なっていたチップ表面上の異物
、またはパッシベーション膜のピンホールまたは欠陥に
よるチップ表面の凹凸のため、モールド樹脂形成時、モ
ールド樹脂のＥＰＲＯＭチップのメモリアレイ部表面へ
の圧迫によるメモリアレイ部の押しつぶし不良、ある’
Ａ ｔｒｉ ハｙ シヘーション膜欠陥を通してのモー
ルド樹脂の入シ込みＫよる汚染物不良をも防ぐことがで
きる。In this way, the peripheral circuit portion 1 on the EPROM chip 10
By stacking the passivation film 15 only on top of the passivation film 15 and further stacking the protective film 16 on top of the passivation film 15, only the upper part of the memory array part 11.12 becomes a hollow part 17.18, and this EP ROM chip When the EPROM chip 10 is sealed with a plastic molding resin 24, the molding resin 24 does not directly contact at least the memory array portion 11.12 of the EPROM chip 10. Therefore, the components of the molding resin can prevent contaminants that affect the memory storage characteristics of the EPROM from penetrating into the memory array portion 11.12 of the EPROM chip 10.
! ! In addition, the EP ROM chip 1 of the mold resin 24
This eliminates pressure on the memory array portions 11 and 12 of 0, which eliminates pressure on the chip surface due to foreign matter on the chip surface or pinholes or defects in the passivation film, which are one of the causes of failure in conventional EPROM chip contact mold resin packages. Due to the unevenness of the mold resin, when the mold resin is formed, the mold resin may press against the surface of the memory array part of the EPROM chip, causing a crushing failure of the memory array part.
It is also possible to prevent contaminant defects due to mold resin ingress through defects in the A tri high shearing film.
なお、上述の実施例ではＥＰＲＯＭチップ上のメモリア
レイ部に中空を形成すべく保獲層としてパッシベーショ
ン膜と同一材からなる保護膜を用いたが、これに限らず
フィルム状のものを付着して用いることもできる。In the above embodiment, a protective film made of the same material as the passivation film was used as the retention layer to form a hollow in the memory array section on the EPROM chip, but the present invention is not limited to this. It can also be used.
以上のように、本発明によれば紫外線ＥＰＲＯＭ −
チップの少なくともメモリアレイ部上が中空となるよう
にパッシベーション膜、保護層を構成したので、モール
ド樹脂のＥＰＲＯＭチップへの悪影響を防止するととが
できるとともに、メモリ記憶保持特性の向上をはかるこ
とができる効果がある。As described above, according to the present invention, ultraviolet EPROM -
Since the passivation film and the protective layer are configured so that at least the top of the memory array part of the chip is hollow, it is possible to prevent the bad influence of the molding resin on the EPROM chip, and it is also possible to improve the memory storage retention characteristics. effective.
第１図（＆）および（ｂ）は本発明の一実施例を示す概
略断面図およびそのＥＰＲＯＭチップの側面断面図、第
２図は前記ＥＰＲＯＭチップ上のメモリアレイ部と周辺
回路部分の概略構成図、第３図（＆）および（ｂ）、第
４図（、）および（ｂ）はそれぞれ従来の紫外線消去形
ＥＰＲＯＭの紫外線透過窓付きセラミックパッケージの
平面図およびその側面断面図である０１０＠・・・ＥＰ
ＲＯＭ、 １１ 、１２・−・Φメモリアレイ部、１３
・・鳴・周辺回路部、１４ψ９・・ポンディングパッド
、１５・・・φパッシベーションＬ１６・・・・保護膜
、１７ 、１８・・・・中空部、２１・Φ・・リードフ
レーム２２ｍ−−・リードピン、２３−−−−ボンディ
ングワイヤ、２４・・Φ・プラスチックモールド樹脂。FIGS. 1(&) and (b) are a schematic sectional view showing an embodiment of the present invention and a side sectional view of an EPROM chip thereof, and FIG. 2 is a schematic configuration of a memory array section and a peripheral circuit section on the EPROM chip. Figures 3 (&) and (b), and Figures 4 (, ) and (b) are a plan view and a side sectional view, respectively, of a conventional ultraviolet erasable EPROM ceramic package with an ultraviolet transmission window. ...EP
ROM, 11, 12...Φ memory array section, 13
・・Sound・Peripheral circuit section, 14φ9・・Ponding pad, 15・φ Passivation L16・・Protective film, 17, 18・・Hollow part, 21・φ・・Lead frame 22m --・Lead pin, 23---bonding wire, 24...Φ plastic mold resin.
Claims (1)
パッケージにおいて、ＥＰＲＯＭチップ上のメモリアレ
イ部を除く周辺回路部分に、該周辺回路部を保護するパ
ッシベーション膜と重ねて前記メモリアレイ部を包囲す
べくパッシベーション膜を形成するとともに、該周辺回
路部分のパッシベーション膜上に前記メモリアレイ部に
対して中空を形成すべく保護層を重ねて形成し、このＥ
ＰＲＯＭチップをプラスチップモールド樹脂内に樹脂封
止するようにしたことを特徴とする樹脂封止型半導体装
置。In a plastic mold resin package for an ultraviolet erasable EPROM, a passivation film is formed on a peripheral circuit portion of the EPROM chip other than a memory array portion so as to overlap with a passivation film that protects the peripheral circuit portion and surround the memory array portion. At the same time, a protective layer is overlaid on the passivation film of the peripheral circuit portion to form a hollow with respect to the memory array portion, and this E
A resin-sealed semiconductor device characterized in that a PROM chip is resin-sealed within a plastic chip mold resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18593684A JPS6164129A (en) | 1984-09-05 | 1984-09-05 | Resinous sealing type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18593684A JPS6164129A (en) | 1984-09-05 | 1984-09-05 | Resinous sealing type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6164129A true JPS6164129A (en) | 1986-04-02 |
Family
ID=16179471
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18593684A Pending JPS6164129A (en) | 1984-09-05 | 1984-09-05 | Resinous sealing type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6164129A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115265999A (en) * | 2022-09-28 | 2022-11-01 | 中国空气动力研究与发展中心高速空气动力研究所 | Horizontal double-engine layout air inlet duct wind tunnel test device |
-
1984
- 1984-09-05 JP JP18593684A patent/JPS6164129A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115265999A (en) * | 2022-09-28 | 2022-11-01 | 中国空气动力研究与发展中心高速空气动力研究所 | Horizontal double-engine layout air inlet duct wind tunnel test device |
| CN115265999B (en) * | 2022-09-28 | 2022-12-06 | 中国空气动力研究与发展中心高速空气动力研究所 | Horizontal double-engine layout air inlet duct wind tunnel test device |
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