JPS6162150A - Data processor - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a data processor by providing the second array, which is a copy of the address array in the CPU of own system to each CPU by multi processor method. CONSTITUTION:Firstly, when another system CPU carry out the store operation, the store address 200 is set to another system CPU store address register RMTA 100, and from the other system CPU, an invalidation start signal 201 is sent to a control circuit 101. The content of the RMTA 100 to be compared presently is set to a back up register RMTBU 102 as it is. The register RMTA 100 can prepare a plural entries. When the next store operation is carried out by another CPU while invalidation processing to another system store address 200 is not completed, the result is set to the store register 100 in turn where another store address 200 is prepared.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor type data processing device having seven buffers, particularly a backup memory invalidation process that can improve the processing efficiency of the data processing device. It is related to.

[Conventional technology]

In order to improve system reliability, there is a multiprocessor type data processing device in which a plurality of CPUs (Central Processing Units) each having a backup memory (buffer storage device) are tightly coupled. In this type of data processing device, communication processing is performed between each CPt7 to guarantee the validity of the data in the backup memory so that the backup memory in multiple CPUs always does not conflict with the data in the main storage device. Is required. In other words, when a certain CPU changes the storage contents of the main memory, a copy of the main memory data to be changed is already stored in another CPU.
If it is stored in the PIJ backup memory,
The data in the backup memory of that CPH is changed in the same way as the main memory data, or is invalidated (i.e.
A process called invalidation is required. Therefore, invalidation processing is generally employed.

Conventionally, a multiprocessor type data processing apparatus as shown in FIG. 2 has been proposed, which is equipped with communication processing means for guaranteeing the validity of data in a buffer memory. Figure 2 is a main configuration diagram of a multiprocessor type data processing device equipped with two CPUs. When the CPUA starts a store operation (accumulation operation) to move the data to a new memory, the store address is stored in the logical address register ARa (1
a). (2a) is an address array A A a that holds the real address of data in the buffer memory using the in-page address part of the logical address register A Ra (1a), (3a) is the page of the logical address register A Ra (1a) A real address register that holds the real address obtained by converting the address, (4a)
is a comparator CMPa, and (5a) is a memory address register MARa to which the real address of the real address register RA a (3a) is set, and from this address register MARa (5a) the real address and store data (not shown) are is output and transferred to the main storage device via the memory bus (6). Also address register MARa
The store address output from (5a) is sent to the CPUB side via the dedicated data line (7a)'e.

(8a) is an invalid address stack BIASa, which is a memory that can only be read in the order in which it is read or vice versa, and is used for processing such as storing the order and rearranging data. (9a).

(10a) is a selector, and (11a) is an address array write control unit AAWCa.

The same components as those on the CPUk side are
It is also provided on the PUB side. That is, CPUB is
Logical address register A Rb (1b), A1.
) Address array 8Ab (2b), real address register (
3bλ comparator CMPb (4b), memory address register MARb (5b), memory bus (6), dedicated data line (7b), invalid address stack pxAsb (5b)
, selector (9b), (10b and address array write control N5 AAWCI) (11b).

Since the conventional data processing device is configured as described above, it operates as follows. That is, when the CPUA starts a store operation, the store address is first set in the logical address register input R,a (1a). The in-page address part of the logical address register A Ra (ia) is used to read the real address of the data in the buffer memory held in the address array A A a (2a), and this real address and the real address register RA a (
3a) (that is, the address obtained by converting the page address of logical address register ARa (1a)),
a (4a) compares 0 If there is a match in this comparison, the address array write control unit AAWCa
(11a) Store the store data in the corresponding block (data storage unit of the backup memory) of the buffer memory via f (detailed explanation will be omitted since the four principles in this part are not directly related to the present invention). Next, the real address is set to the memory address register MARa (5a), and this address and store data (not shown) are transferred to the main memory device via the memory bus (6), and all stores to the main memory are executed. At the same time, the invalid address stack BIASa (8) in CPUB is connected from memory address register MARa (5a) to dedicated data line (7a).
b) Send the Hess door address.

Invalid address stack BIASI) (8b) is a buffer memory of several words in which store addresses of other systems are registered, and if an address is registered in this buffer memory, it is sent via the selector (9b). The data is read to the address array A A b (2'b) and a comparison request is issued. Therefore, two CPUs
, “Since B operates essentially asynchronously, CP
When the UA performs the next store operation, the new store address is registered in the invalid address stack B ASb (8b) through the steps described above, regardless of whether the above request is accepted or not. It has become.

When the above request is accepted by the CPUB, the address array column address specification part of the store address in the invalid address stack BIASb (8b) is sent to the address array A Ab (2b) via the selector (9b) Q, and the address comparison part is sent to the address array A Ab (2b). is sent to the comparator CMPb (4b) via the selector (1'ob). Comparator cMp
As a result of the comparison between the address array AAb read address and the store address in the invalid address stack BrAsb (8b) in b (4b), if there is no match, the process ends there. On the other hand, if there is a match as a result of the comparison, the address array write control unit AAwcb (11b) sends the address array A to
Perform a write operation that invalidates the block with the matching address in A b (2b).

Through the series of operations described above, the same data as the main memory is stored in the backup memory of CPUk.
The validity of the data in the buffer memory is maintained by invalidating the block having the same address as the store address.

By the way, in this type of data processing device, a store address is sent every time there is a store operation (debt storage operation) in a CPU of another system, and a request to read and compare the address array is issued each time. Only some of them match. That is, - actually own address array AAa (2a), AA b (2b)
Only a small number of other-system store operations require invalidation processing. Considering this, the above request is unnecessarily similar to a normal request in the own system, such as a store,
This interferes with fetching (instruction retrieval), etc., and therefore causes a decrease in processing efficiency of the data processing device.

Therefore, in order to eliminate such a decrease in processing efficiency, a method as shown in FIG. 3 has been proposed.

FIG. 3 is a circuit diagram of the input side of the address stack, and in the figure (8) is the invalid address stack Br in FIG.
Invalid address same as Asa (8a), nrAsb (8b) 2.11 Stack BIAS, and register (i.e. filter memory) provided on the input side of invalid address stack BrAS FM (to), filter The memory F'M ((2) stores a copy of the other system store address most recently registered in the invalid address stack BrAS (8). α3) is a comparator, which stores the copy of the other CPU store address and the filter memory FM (12). The transmission of other cPσ store addresses, which are input to the invalid address stack BIxs(s), is controlled on/off by comparing the output with the output of the cPσ store address.

The circuit in Figure 3 re-initiates the self-address array (eight a (2) in Figure 1) for addresses that have already been invalidated.
a), see A A b (2b)) (D reading 1.,
It is configured based on the idea that unnecessary interference will not be caused by not issuing a comparison request.

In other words, if a foreign system CPσ store address that is the same as the stored content of filter memo ')FM<12> is sent,
This is compared by a comparator (19) and the comparison output turns off the input side of the invalid address stack BI input 5 (8), so that it is not registered in the invalid address stack BI input 5 (8). Therefore, data processing efficiency is prevented from decreasing by not issuing unnecessary read and comparison requests to the own address array. On the other hand, if another system C'P U store address different from the memory contents of filter memory yy (g) is sent, the input side of the invalid address stack BrAs (8) is turned on by the comparator (function) and the corresponding invalid address is turned on. At the same time as registering the address in the address stack 5rAs (sl), the stored contents of the filter memory FM (LE) are also rewritten to the address, and as described above, requests for reading and comparison are issued to the self-system address array and invalidation processing is performed. The contents of the filter memory pu(J) are invalidated when the same address is loaded (moved and stored) in the address array.

[Problem that the invention seeks to solve]

Conventional data processing devices prevent unnecessary interference by not issuing read/comparison requests for addresses that have already been invalidated or invalidated as described above. Although there is an invalid address stack BI
Since not all addresses registered in AS(8) match the addresses in the local address array, unnecessary interference should be removed from the normal request processing of the local CP'σ. The problem was that it was not possible.

The present invention was made to solve these problems, and only when it is actually necessary to invalidate an address during buffer memory invalidation processing, an address play readout and comparison request is issued and installed. By performing validation, by issuing a request to read and compare the address array and invalidating the address only when it is actually necessary to invalidate the address when processing a normal request of the local CPσ, System CP
It is an object of the present invention to obtain a data processing device that can completely eliminate the interference necessary in winter to the processing of normal requests of σ and improve data processing efficiency.

[Means for solving problems]

The data processing device according to the present invention is a multiprocessor type data processing device in which a plurality of CPrJs each having a buffer memory are tightly coupled.
A second address array that is a copy of the address array of the second address array, a receiving means for receiving a store address and a store operation activation signal from the CPU of another system to the main memory, and a comparison between the contents of the second address array and the store address. Comparing means compares the second address array with the store address in response to the store operation start signal of the other system cpσ, and if there is no matching address, ends the process there;
If a matching address exists, the store address is transferred to the first address array and the matching address is invalidated in the first address array. [Operation] In the present invention, the CPU has a second address array which is a copy of the first address array having address information of the data in the own system's buffer memory, and
When executes a store operation ), backup memory invalidation processing is performed, which generally consists of the following two stages.

■By the invalidation process activation signal accompanying the store operation of the other system cpσ, the other system store address is compared with the second address array, and if there is a match, the request control unit of the own system cpσ is sent. to issue an invalidation request. If there are no matches, the invalidation process ends at that point.

(2) The request control unit accepts the invalidation request and actually invalidates the first address array and the second address array.

As a result, unnecessary requests for reading and comparing address arrays are not issued, so that it is possible to prevent a decrease in processing efficiency of the data processing device.

〔Example〕

FIG. 1 is a main configuration diagram of an embodiment of a data processing apparatus according to the present invention. In the figure, (100) is a CPU of another system that is installed in the CPU of its own system and sequentially stores store addresses of other systems.
Store address register RMTA.

(101) is a control circuit for prohibiting the store operation in the other system's CPσ or starting invalidation of the own system's CPσ, and (102) is a control circuit for prohibiting the store operation in the other system's CPσ, and (102) is the control circuit for controlling the storage contents of the other system's CPσ store address register RMTA (11)0). The backup register RMTEU of the other system store address register RMTA, which is stored as is, (103) is the other system CP
The column address selector (104) connected to the output side of the σ store address register RMTA (100) reads out the other system store address given via the column address selector (103). A, (105) is the second address array B
Address comparator 80MP connected to the output side of AA,
Other system CPσ store address register RMTA (100
) in the other system store address using the address comparator SCMP.
Comparison address selector given to (105) and (10
Reference numeral 7) is a request control circuit that performs privacy control (that is, determines the program to be executed next based on priorities, etc.) of the request related to the program based on the output signal of the control circuit (101). Request control circuit (
107) by column address register OA (10
8), the respective input sides of the column address register s CA (109) and the address register s AR (110) are controlled. (111) is column address register c A
(108) is the first address array A A connected to the output side, (112) is the first address array A A
A real address register RA connected to the input side of (111), and (113) ? i real address register RA
(112) and the second address array S A A (104
) is the real address register SRA connected to the real address register SRA. (1
14) fd Address comparator CMP connected to the output side of the first address array A & (111).

and (115) is the address comparator CM P (114)
The first address array input A (1
11) is the write control circuit input ATC (115) o(
116) is the second address array 8A (1) connected to the output side of the address comparator SCMP (105).
04) is the write control circuit 5AAWC. (200)
is the other system CPσ store address register RMTA (10
A store address consisting of a column address specification part and a comparison address part of the other system CPσ given to 0), (20
1) is an invalidation activation signal given from the other system CPU to the control circuit (101), and (202) is the control circuit (
A busy signal (101) is applied to the other system CPσ, and (203) is an address array match signal output from the address comparator SCMP (105). The address array match signal (203) is sent to the address comparator SCMP.
(105), the comparison address part of the other system store address (200) and the second address array S A A (1
This is a signal that is output from the address comparator 80MP (105) when the address read in the address array write control circuit 8AAWC (116) is compared with the address read out in the address array write control circuit 8AAWC (116). ) and the control circuit (101). (204) is the control circuit (
101) Invalidation request signal given to the Karaquest control circuit (107), (205) is the other system store address backup register RMTBσ(1
Address sending signal (206) is output from the request control circuit (107) to regulate on/off of the output signal of column address register CA (108).
), S CA l', , (109), an address register set signal output from the request control circuit (107) to set the address register S A R (110), and (207) a comparator CM P
This is an address array match signal output from (114). The address array match signal (207) is the comparator CM
According to P (114), the first address array A A
This is a signal that is output from the comparator CMP (114) when the data (address) read in (111) and the contents of the real address register RA (112) are compared and they match. 207) is applied to the address array write control circuit AAWC (115). (
208) is an address bus that transfers the store address set in the other system store address backup register RMTBσ (102) to the column address register CA.
(1oa), sCA (109) and address register 8AR (110).

Next, the operation of the above embodiment will be explained. First, when the other system CPσ executes a store operation, its store address (200) is stored in the other system CPσ store address register RM.
TA (100), and the invalidation start signal (201) is set to the control circuit (10) from the other system CPσ.
1). The contents of the other system cpσ store address register RMT A (100), which is currently the target of comparison, are set as is in the backup register RMTBσ (102). Here the store address register RMTA
(100) can prepare multiple entries (waiting inputs). - If the next store operation is executed on the other system CPσ before the invalidation processing for the other system store address (200) is completed, the store address register prepared with the other system store address (200) RMTA (100) and each store address (200) waits for invalidation processing to be performed in the fl store address register RMTA (100). When the store address (200) is set in the prepared all store address register RMTA (100), the control circuit (
The busy signal (202) output from 101) is sent to another system c
pσ and prohibits store operations in other systems CPσ to prevent overruns from occurring.

An invalidation activation signal (201) is sent to the second address array S A (104)' via the active address selector (103), and reading of this second address array S A (104) is performed. . If there are multiple entries for the - column address in the second address array S AA (100), they are all read out at the same time. Second address array SA
The data (ie address) read from (104) is sent to one input of address comparator SCMP (105). Here, if there are multiple entries for the -〇 column address, the comparator SCMP (1[
] 5) are also provided in the same number.

On the other hand, store address register RMTA (100)
The comparison address part, which is the remaining part of the other-system store address (200) stored in Device SCMP (105
) to the second address array S A A (104
) is compared with the read address. The result of the comparison is sent to the control circuit (ioi) via the control line.

If there is no match as a result of the above comparison, the control circuit (101)
The invalidation process regarding the store address (200) ends. Store address register RMTA
If the next other-system store address (200) is set in (100), invalidation processing for that address is started. On the other hand, the comparator sqMp (105
), if there is a rare match, the comparison rrS
In response to the address array match signal (203) given from the CMP (105) to the control circuit (101), the control circuit (101) issues an invalidation request (204) to the request control circuit (107).

When the request control circuit (107) receives the t-invalidation request (204)', the backup register RMTB is activated by the address sending signal (205).
Store address (2) set in U (102)
00) on the address bus (208). Furthermore, by the address register set signal output from the request control circuit (107), the column address specified portion of the address array is set to the first address array A A ( 111)
Set the column address register CA (108) of the column address register CA (108) and the column address register 808 (109) of the second address array s AA (104), and also set the entire store address (200) on the address nox (208). Set in address register SAR (110).

Of the store address (200) set in the address register S A R (110), the comparison address part is the real address register RA (112) of the first address array A A (111) and the second address array S
Input A (ioi5 real address register 8R input (113
) and prepared for comparison.

Column at of first address array A A (111).

The data (ie) read from the column of the address array A A (111) specified by the address register C input (io8) is supplied to one input terminal of the address comparator CM P (114). Also, the column address register 5CA (1
The contents stored in 09) are sent to the second address array S input A (104) via the selector (103), and the specified column of the second address array S input A (104) is read out. . The read data (ie address) is supplied to one input terminal of address comparator SCMP (105).

On the other hand, the contents stored in the real address register RA (112) of the first address array A A (111) are supplied to the other input terminal of the comparator CMP (114), and the contents stored in the real address register RA (112) of the first address array A The contents stored in the real address register SRA (113) of (104) are supplied to the other input terminal of the comparator SCMP (105), and the contents stored in the real address register SRA (113) of the comparator SCMP (105) are supplied to the respective comparators CM P (114), SCMP
Address comparison is performed at (105). In this case, i.e. invalidation rifnis) (204)
is accepted, the addresses will definitely match, so the comparators CM P (114) and SCMP (105)
are address array match signals (207), (203)
0 first atto, which outputs the answer array A A (111
) is the match signal (207) of the comparison result of the first address array input A (111).
s) to the second address array 8 A A (104)
The match signal (203) of the comparison result is sent to the second address array S by the write control circuit 5AAWC (11) of the person (104).
6), and each address array A A (1
11) Perform invalidation write processing for the matched entry of S A A (IC+4), for example, write a logic '0' to the valid bit in the address array entry.

As a result of the above, the first address array A A (111)
Invalidation processing for is completed. Also the second
Since the invalidation for the address array S A (f04) is also performed in parallel, the first and second address array S A (111), 8 A A (t
The consistency of o4) is completely preserved.

Note that in the above embodiment, the explanation was made for the case where there is - backup memory in the CPU, but even if a plurality of backup memories are provided in the CPU, the 7'C second Address array S A A (10
4) Invalidation processing for all buffer memories is possible by preparing as many k buffer memories and performing similar control.

Therefore, it goes without saying that even if a plurality of backup memories are provided in the CPU, it falls within the scope of the present invention. Leave the data processing equipment behind.
Since each CPU is provided with the address array of Houki 2, which is a copy of the address array within the Shiraito CPU, the following effects are achieved.

In other words, in conventional data processing devices, when a store operation by a CPU of another system is executed, it is necessary to read the address array, that is, to occupy the address array, regardless of whether or not the own system's backup memory is actually invalidated. However, since the present invention has a group 2 address array that is a copy of the address array, the CPU In parallel with the normal request processing, the second address array can be used to determine whether or not invalidation is actually required. Therefore, it is only necessary to read the address array, that is, to occupy the address array, only when invalidation is actually required.
Interference with H's normal request processing can also be suppressed to the necessary minimum, and the processing efficiency of the data processing device can be improved.

[Brief explanation of drawings]

FIG. 1 is a main configuration diagram of an embodiment of a data processing device according to the present invention, FIG. 2 is a main configuration diagram of a conventional data processing device,
FIG. 3 is a circuit explanatory diagram of a conventional data processing device that is an improvement on the device shown in FIG. (100)--Other system CPU store address register MT
A (101)...Control circuit (104)...Second address array 5AA (105)
--Address comparator SCMP (107)...Request control circuit (N1)...First address array eight people (114)...
Address comparator CMP (115)/1 address array write control circuit AAWC
(116) Address array write control circuit 5AAW
C (200) - store address of other system CPσ (201
)... Invalidation activation signal In addition, are the same symbols in each figure the same or contrasting parts? show.

Claims (1)

[Claims] In a multiprocessor type data processing device in which a plurality of CPUs having buffer memories are tightly coupled, each CPU has a second address array that is a copy of the first address array that holds address information of data in its own buffer memory. an address array, a receiving means for receiving a store address from a CPU of another system to the main memory and a store operation activation signal, and a comparing means for comparing the contents of the second address array and the store address, the receiving means The comparison means compares the contents of the second address array with the store address based on the store operation activation signal of the other system CPU received by the CPU, and if there is no matching address based on this comparison signal, the process is performed. and, if a matching address exists, transferring the store address to the first address array and invalidating the matching address in the first address array. Device.