JPS6162138A - Data processing device - Google Patents

Abstract

PURPOSE:To obtain a universal-purpose data processing device which can perform various relation computation very efficiently by specifying computation- specifying information and command data. CONSTITUTION:Assuming that in the RESRICT-system computation, the relation as the condition data is S1 and the object relation is S2, a CPU11 first specifies S1 UB20U with respect to a merger 10 using a LOAD(U) command and actuates an engine core 15, which includes the merger 10, using an ENG.GO command. As a result, S1 is sequentially written in prescribed byte-units starting from the 0 address of UB20U. When writing of data by the amount of RSUXTRN is completed, a borrow signal is outputted from the STC counter, an FUWED flag is set, and the merger 10 applies an interruption to the CPU 11. Next, the CPU11 specifies S2 LB20L by the REST-EQ(L) command, and indicates REST-EQ. Then the CPU11 actuates the merger 10 by the ENG.GO command.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing device particularly suitable for relational operations required in relational database processing.

[Technical background of the invention and its problems] One of the main processes in a relational database is a relational operation between two relations. As a relational operation,
join LJoin ), constraint (RestrictiOn
), projection, etc. are known.

This type of relational calculation has generally been handled by software. Therefore, a large amount of processing time is required for relational calculations. Therefore, there has been a demand for a dedicated hardware device that can speed up the above-mentioned relational calculations.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its object is to provide a data processing device as dedicated hardware that can efficiently perform relational calculations.

[Summary of the Invention] In the present invention, a first buffer that stores a first relation and a second buffer that stores a second relation are provided. Further, in the present invention, there is provided a first register that holds an operation code indicating the operation type and a buffer 1 designation bit that designates either the first or second buffer; a second register that holds record number information indicating the number of records of the relation; a third register that also holds record length information indicating the record length; and a third register that holds key field length information indicating the key field length of the relation. 4 registers are provided.

゛Furthermore, in the present invention, the number of records specified by the second register and the number of records specified by the third register are stored in the buffer specified by the buffer 7 specification bit in the first register among the held aa in the first register. The relation of the data date indicated by the record length is written. Also, if a relational operation is specified by the operation code held in the first register, the first or second buffer? Of these, the buffer specified by the buffer specification bit in the first register is
A relation of the amount of data indicated by the number of records specified in the second register and the record length specified in the third register is written. In parallel with this writing, a record read operation is performed to read data one record from each of the first and second buffers. By this record read operation, data for one record read from the first and second buffers is read from the third and fourth buffers.
Temporarily stored in a buffer.

Further, in the present invention, a comparison circuit is provided for comparing data for one record each read from the first and second buffers 1 between the key fields designated by the fourth register. Then, according to the comparison result of the comparison circuit and the operation code held in the first register,
Update control of read addresses for the first and second buffers and further output control of records temporarily stored in the third and fourth buffers to the outside are performed.

[Embodiment of the Invention] FIG. 1 shows the configuration of a marsher 10 according to an embodiment of the present invention, and FIG. 2 shows the configuration of a relational database engine (hereinafter referred to as RDBE) to which the marsher 10 of FIG. 1 is applied. shows. In the RDBE in Figure 2, 11 is the RDBE
A CPU 12 which controls the entire system is a sorter (sort processing device) which applies a two-way merge sort method. The sorter 12 consists of 12 stages of sort cells 12-0 to 12-11, and is capable of sorting records into a maximum of four.

13 is an IN aligner (sort pre-processing device) provided on the input side of the sorter 12 and performs pre-sort processing such as moving key fields to be compared to the beginning of records in sort processing; 14 is an IN aligner 3; This is a sort checker that monitors whether the sort results are correct.

Marsha 10 is connected to sort checker 4 and is configured to perform relational operations at high speed between one or two relations that are being sorted by sorter 12 .

IN aligner 3, sorter 12, sort checker 4
, and marsha 10 constitute an engine core 15, which is dedicated hardware that performs pipeline processing synchronized with input data by interlocking sorting processing and relational calculation processing. 16.17 is an HM adapter (hereinafter referred to as HMA) that controls the interface between the RDBE and a hierarchical memory subsystem (hereinafter referred to as HM) not shown.
It is. HMA 1B operates as an input port for data to the engine core 15, and HMA 17 operates as an output port for data from the engine core 15. 18 is CPU
There are 11 input/output buses, one of which is a DMA bus. The input/output bus 18 includes each of the engine cores 15 (14 components, including the merge 710, the CPU 11, and the
VIA16.17 is connected, and DMA bus 19 has C
PU11 and HMA16.17 are connected.

As shown in FIG.
, an output selection section O8P, and a control section 0NTP that controls these calculation section OPP and output selection section O8P.

In the arithmetic unit PP, 20U is a U (tJpper) buffer (hereinafter referred to as an input register (INU register)) that stores the first relation, and 21L is an input register (INL register) that holds data to be written to L820L. .22U is a register (tJPR register) that holds the read data from UB20U, and 11.22L is a register (L) that holds the read data from LB20L.
OW register). 23 is a comparator (
(hereinafter referred to as CMP), 24U is the UPR register 22
An output register (OTU register) transmits the contents of U to the output selection unit O19 side, and an output register (OTU register) transmits the contents of the OW register 22 to the output selection unit O19 side.
TL register). 251J is a write address register (WA) as a write pointer for UB20U.
tJ register), 2SL is a write address register (WAL register) as a write pointer to LB2OL. 26U is a read address register (RAtJ register) as a read pointer for UB20U
, 26L is a read address register ('RAL register) as a read pointer for LB2OL.

WAU register 25tJ% WAL register 25L1 (B
tJU register), 271 is a backup register (BUL register) that holds the contents of the RAL register 26L. 28tJ is WAU register 25U and RA
A comparator (CMP
), 28L is a comparator (CMP) that compares the contents of the WAL register 25L and the RAL register 26L.

29U is WAU register 25U or RAU register 2
A multiplexer 29m selects the contents of 6LI as the memory address for 1J8201J, and 29m selects the contents of WAL register 25L or RAL register 26L as LB2O.
This is a multiplexer that selects the memory address for L.

In the output selection section O8P in FIG. 1, 30U is UB2(
Record buffer (LIRB30) stores data for one record from HJ, 30L is LB2OL
This is a record buffer (LRB 30) that stores data for one record from . Input register (INUR register) that holds the contents of register 24U as write data to LIR830U, 3
1L is an input register (IN) that holds the contents of OTL register 24L as write data for LR and 830L.
LR register). 32 is URB301J or L
The multiplexer 33 returns the read data from the RB3oL, and the reference numeral 33 is an output register (800 register) that latches the selected output data from the multiplexer 32.

34U G,t IJ RB Write address register (WAUR register) as a write pointer for 30U, 34Llt L RB Write address register (WALR) as a write pointer for 3OL
register). 35U is a read address register (RA) as a read pointer for LJRB30tJ.
UR register), 35L is a read address register (RALR register) as a read pointer for LR830L. WAUR register 34USwALR
Register 34L1RAtJR Register 35U1 and R
ALR register 35L has a counter function. 36
U is WAUR register 34U or RAUR register 3
Multiplexer 0.361 which selects one content of 5U as the memory address for IJ RB 30U is WAL
This is a multiplexer that selects the contents of the R register 34L or the RALR register 35L as the memory address for the LRB 30L.

(MOP register). As shown in FIG. 3, the MOP register 39 contains a 5-bit merge operation designation code (MRG-;':.,
1), two F, □ designation t8 two, order designation bit (AS1
0S bit) and a buffer designation bit (U/L bit) that designates UB20tJ or LB20L. In this example, AS/D
Ascending order is specified by S-0, and descending order is specified by AS/DS-1.

Also, U/L-〇 is LJB201. I is U/L-1 and LB20L is specified.

40 is an input/output interface which is an interface to c p u ii, 41 is an input/output interface 4
This is a command register (CMD register) provided at 0. 8-bit command data is set in the CMD register 41 according to a designation from the CPU 11.

The 0th bit of this command data is a register designation bit (REG, INO bit), as shown in FIG. The REG and IND bits are the 0th to IND bits of the command data.
The 7th bit is used as data that specifies (the register number of) the register in marsher 10 (REG, I
ND=...: 1. (in the case of REG, IND-0-) or used as the original operation instruction data of the command data (in the case of REG, IND-0-). In the case of REG, lN0-○, as shown in Figure 4, the second pit of the command data is the engine
Reset designation bit (R
3T bit), the third bit is an engine start designation bit (ENG, Go bit) that specifies startup of the engine core 15, and the fourth bit is a marshaller startup designation bit (MRG, Go bit) that designates startup of only the marsher 10. bit), 6th
The bit is the RAU register 26U and the FUEM described later.
U retry specification bit that specifies clearing of P52LI (
LIRTRY bit), the 7th bit is RAL register 2
61 and is used as a last try designation bit (LRTRY pit) that designates clearing of FLEMP52L, which will be described later. Note that the operation designation of each bit described above is valid at logic "1''.

Referring to FIG. 1 again, 42 is UB20U or LB
The total record number register (T
RN register), 43U is a record size register (R3U register) indicating the record length R8U of the relation stored in UB20U, ・°Cibrexa, 45 loads the selected output data from multiplexer 44 as an initial value, and loads it to UB20U or LB2OL. A write counter (WRC counter) 46, which counts down when writing WR, loads the contents of the TRN register 42 as an initial value, and loads the contents of the TRN register 42 as an initial value.

This is a record number counter (STC counter) that counts down in response to a borrow signal from the C counter 45. 47 is a valid data length register (VDL register) indicating the key field length (effective data length VDL) in the record, which is to be compared in the merge operation; 48 is a register that loads the contents of the VDL register 47 as an initial value;
Valid data length counter (VCT counter) that counts down when reading data from (and LB207)
It is.

MOP register 39, CMD register 41, TRN register 42, RSU register 43U, R8L register 43
The LS and V'DL registers 47 are the CPU 1 in FIG.
1, it can be set up in advance.

49U is a read counter (RCL counter) that counts down by initializing the contents of the R8U register 43U.
It is. 50U is set in response to a borrow signal from RCU counter 49U, and is a record end flag (FUE flag) indicating that the data read from U320LI is the last data of one record. The record end flag (FLE flag) 651U indicates that writing to UB20U has been completed (FUWED flag), and 51L is a write completion flag (FUWED flag) indicating that writing to LB2OL has been completed. FLW
ED flag). 52U is an empty flag (FUEMP flag) indicating that UB20U is empty.
, 52L is an empty flag (FLEMP flag) indicating that LB20L is in an empty state. 53U is U
320LI is an output instruction flag (FUo flag) that instructs external output of data, 53L is a register (O3UA register) as an output instruction flag (PLO flag) that instructs external output of data from LB20L, 54L is from LRB3OL. Register i neta (oSLA register) as an extraction pointer that specifies the first extraction position for the read record of
55L is a register (O8: UB register) as a cutout pointer that specifies the second cutout position for one record read from LRB 30L. register). 56 is U
Counter (CTR counter) that counts up when reading data from RB30LI or LRB30L
, 57U is a comparator (CMP) that compares the contents of the CTR counter 56 and the SUA register 54U, 57L
is a comparator (CMP) that compares the contents of the CTR counter 56 and the 08LA register 541. 58LJ is a comparator (CMP) that compares the contents of the CTR counter 56 and the osus register 55U, 58L is a comparator (CMP) that compares the contents of the CTR counter 56 and the 08LB register 55L, and 59U is the CTR counter 56.
and a comparator that compares the contents of the R8U register 43tJ (CMP, 59 is the CTR counter 56 and R3
Comparator (CMP) that compares each content of the L register 43L
Teal. oSUA register 54U1 oSUB register 5
5LI, 08LA register 54L, 031B register 5
5L is set in advance by the CPU 11 in FIG.
Flag 50U and FLE flag 50S, as well as CMl
, 61 are MOP register 39 and CMD register 41
This is a clearing circuit that clears each section at the timing of a start instruction from the control timing generation circuit 60 according to the contents of. 62 is the comparison result of CMP23 and VCTCTR
By the output from the counter, LIB20U and LB2O
A comparison control section 63 determines the comparison result of the key field of each record from L. Reference numeral 63 is an interrupt control section that generates an interrupt to the CPU 11 in FIG. 64 is an output iti! that controls the output of data to the outside. I'10
A control timing generation circuit 65 operates according to the content of the MOP register 39 and the comparison result of the comparison control unit 62.
This is a control signal generation circuit that generates various control signals for UB20U readout control, LB20L readout control, interrupt control, output control, etc. at timings according to instructions from 0.

Next, the configuration around the interrupt control section 63 in FIG. 5 will be explained with reference to FIG. 6. In FIG. 6, 66 indicates the U/L bit from the MOP register 39 is input.
This is an AND gate (A) into which the bit and the BORO i';- signal from the STC counter 46 are input.

The FUWED flag 51U corresponds to the output signal from A671J, and the FLWED flag 51L corresponds to the output signal from A67L.
be done. 68U is an AND gate (A) into which the comparison result (coincidence detection signal) of CMP28 (J and the output signal from the FUWED flag 51U is input), 68m is CMP28L
AND gate (A) into which the comparison result (coincidence detection signal) and the output signal from the F LWED flag 51L are input.
It is. 691J is a gate that gates the output signal from A68U at a specified timing from the control timing generation circuit 60, and 69L is a gate that gates the output signal from A68L at a specified timing from the control timing generation circuit 60. FUEMP flag 52U is gate 69U,
FLEMP flag 52L is set in response to the output signal from gate 69L. A decoder 70 decodes the contents of the MOP register 39 (merge operation designation information). The decoder 70 has merge operation specification information UB20U.
AND gate (A) to which the output signal from the WED flag 51U is input when the O-mode of the first relation is specified, and the output signal from the WED flag 51U is input. This is an AND gate (A) into which the output signal from the flag 51L is input. 73U receives the interrupt enable signal 741J from the control signal generation circuit 65 and the output signal from the FLJEMP flag 521J.
The AND gate (A) 73L is the interrupt enable signal 74L from the control signal generation circuit 65 and the FLEMP gate:
? This is an antogenide (A) to which the output signal from the plug 52L is input. The interrupt permission signals 74U and 74L are M
Control signal generation circuit 65 according to the contents of OP register 39
generated from. For example, if 5ORT (sort) type operations or RESTRICT (constraint) type operations are specified, interrupt permission signals 74U and 74L are output,
If a JOIN type operation is specified, only the interrupt permission signal 74U is specified. Also, PASS
(Path) If system operation is specified, U/L=O
(i.e. tJB20tJ specified), interrupt enable signal 7
If 4U is U/L=1 (that is, LB20L is specified), the interrupt enable signal 74L is output.

Output. 75 is an OR gate (OR) into which each output signal from A72U, A72L, A73U, and A73L is input, and 76 is an interrupt generation circuit that generates an interrupt in response to the output signal from 0R75.

Next, the configuration around the clear circuit 61 in FIG. 5 will be explained with reference to FIG. 7. In FIG. 7, 77 is a gate (A
), 78L is the U/L pin I from the MoP register 39.
This is an AND gate (A) to which the above ENG and Go bits are input. 79U is the output signal from A78U and CM
An OR gate (OR) 79L receives the R3T bit from the D register 41 and an OR gate (OR) receives the output signal from the A78L and the R8T bit. 80U is an OR gate (OR) into which the output signal from 0R79U and the URTRY bit from the CMD register 41 are input, and 80L is the output signal from 0R79L and the CM
This is an OR gate (OR) into which the LRTRY pit from the D register 41 is input. 81U is from 0R79U.

A gate 81L gates the output signal as a clear signal for the WAU register 25U and the FUWED flag 51tJ at a specified timing from the control timing generation circuit 60, and uses the output signal from the 0R79L as a clear signal for the WAL register 251 and the FLWED flag 51L. This is a gate that is gated at a specified timing from the control timing generation circuit 60. 82U is 0
Gate 82L gates the output signal from R80U as a clear signal for the RAU register 26U and FUEMP flag 52U at the specified timing from the control timing generation circuit 60.゛Eiyu 2Gl and FLEMP
1j for flag 52L;
This is a gate that gates at the specified timing of .

Next, the configuration around the output control section 64 in FIG. 5 will be explained with reference to FIG. 8. In FIG. 8, 83 indicates U RB 30U, 3 according to the states of FUO flags 53U, 53L.
841J is an output sequence control unit that controls the output order of data from 0L, 841J is a URB read control unit that controls data read from URB 30tJ, and 84L is LRB 30.
This is an LRB read control unit that controls data read from L. The URB readout control units 84U and 84L start record readout control operations in response to a readout start instruction from the output sequence control unit 83, and the CMPs 59U and 5 in FIG.
The read control operation is stopped according to the comparison result (coincidence detection signal) of 9m. Further, the FUO flags 53U and 53L are output instruction signals 85U and 85 from the control signal generation circuit 65.
Set according to 5L. 86 is a strobe signal 87U (for the ROUT register 33) from the tJRB read control units 84U and 84L.

871 is an input OR gate, 88 is a gate that gates the 1+ output signal from OR8B and outputs it to the ROLIT register 33, and 89 is an extraction control section. According to instructions from the output sequence control section 83, the cutting control component 89 selects CMP57U, 58U or CMP57L, 58L.
gate 88 according to the monitoring result.
control.

Next, the operation of the above configuration will be explained using the sorter 12 shown in FIG.
Sorting processing that exceeds the capacity of (this is an external sort, □8),
). □、9、□9゜□ ′□” This will be explained with reference to FIG.

First, the concept of external sorting will be explained. R in Figure 2
In DBE, relations exceeding the capacity of the sorter 12 (
Streams, files) are sorted using an external sort function. At this time, the relations to be sorted are read from the HM (not shown), and the relations to be sorted are read from the HM (not shown).
, are guided to the sorter 12 via the IN aligner 13. After being sorted by the sorter 12 into buffer size units, the data are led to the marsher 10 via the sort checker 14, where they are sorted into larger units. FIG. 9 shows an outline of the above-described external sorting procedure. That is, assuming that the original relation to be sorted is A1, the outline of the external sort procedure is divided as follows to obtain A11 to A1n (n-4 in this example).

(2) Sort A11 to A14 by the sorter 12 to obtain A21 to A24.

■A21. Sort A22 by Marsha 10, and
Obtain 31 and 32. Similarly, A23. A24 to A3
3. Get A34.

■ (A31. A32) and (A33. A34) are 2
Sorted by Marcia 10 as a pair relation,
Finally, a relation A4 obtained by sorting the original relation A1 is obtained.

In this way, when sorting relations that exceed the capacity of the sorter 12, first the relations to be sorted are
The process starts by dividing the data into units of capacity, and using the marsher 10 to perform external sorting for each of the two sets of divided relations. When this operation is repeated, finally sub-relations 811. The first consisting of S12゜...31n
relation S1' (in the example in Figure 9, A31.A
relation consisting of 32) and sub-relation S21
．． 822. . . . A second relation S consisting of the second relation S1 and the second relation S2 consisting of 32 m
Taking as an example the case of external sorting for 2, a description will be given with reference to FIGS. 11 to 13. In addition, Figure 1.1 shows the sequence of commands for executing the above-mentioned external sort, and the FUW at startup and termination by each of these commands.
ED flag 51U, WAU register 25U, RAU
The correspondence relationship with each content (state) of the raster 26U, FLWED flag 51L, WAL register 25L, and RAL register 26L is shown. In FIG. 11, ``■'' to ``1'' indicate the order of execution of commands. Furthermore, FIG. 12 is a diagram explaining changes in the write position (solid line) and output position (broken line) to UB20U and LB20L at the end of execution of each command shown in FIG. 11, and FIG. -EX operation) is specified, the input/output logic of the control signal generation circuit 65 is shown. First, the setup for 811 is held in the CMD register 41 provided in the input/output interface 40 in the marsher 10. In this case, the command data has its 0th bit, ie, the REG and IND bits, set to logic It 111, and specifies a register (register number) within the marsher 10. When the CPU 11 specifies a register using the above-mentioned command data, it sends data to be set in the corresponding register (setup data) onto the input/output bus 18 along with a write signal. Thus, the data on the input/output bus 18 is set in the corresponding register in the marsher 10 specified by the command data held in the CMD register 41 in response to the write signal.

In this example, the CMD register 41 is configured to count up in response to a write signal from the CPU 11 when the REG and IND bits are logic +1111. Therefore, if the register numbers of the registers to be set up are consecutive,
After specifying the device and transferring the command data,
Just the desired data (U/L of logic “0” specifying 7U)
Merge operation specification information (LOAD (U) command) including bits is set, information indicating the first field position of the record is set in the 03tJA register 54U,
Information indicating the last field position of the record (ie, record length RSU)' is set in the 08UB register 551J. In addition, the record length R8U (record length of each record in the first relation S1) is set in the R8U register 43U, the effective data length VDL indicating the key field length in the record is set in the VDL register 47, and the TRN register 42 is set in the R8U register 43U. Total number of records T of 811
RN is set. In addition, R8LI, VDL, TRN
, (true value - 1) is actually adopted.

Next, c p u ii specifies the marsher 10 as a device again, and this time sets command data with the REG and IND bits being logic "OII" to the CMD register 41 in the input/output interface 40 of the marsher 10. The command data has its third bit, ENG, Go.
This is a GO command with the bit set to logic ``1'' and the relation (stream data) from HMA 16 to IN aligner 13.

Merger 1 via sorter 12 and sort checker 14
It is used when inputting 0, performing a merge operation, and outputting to HMA 17. In this case, Marsha 10 is L
Data processing will be performed using data newly stored in JB20U or LB20L. In contrast,
As a Go command for Marsha 10 only, MRG
, Go commands are provided.

In this MRG, GO command, UB20U or LB
Processing is performed on significant data already stored in 20L.

Marsha 10 receives the E set in CMD register 41.
It is activated by the NG and Go commands. At this time, the clear circuit 61 causes the WAtJ register 25tJ, RAI
The J register 261J, FUWED flag 51U1, and FUEMP flag 52tJ are cleared (reset). That is, it is set in the MOP register 39.

U/L bit of merge operation specification information is logic “O”, CM
Command data set in D register 41 (however, R
ENG, Go bit in EG, IND-0) is logic “1”
'', the AND condition of A78U in the clear circuit 61 is satisfied, and the logic 111 II signal is output from A78U. The logic II 1 IT signal from A78U is O
It is guided to the gate 81U via R79tJ, and 0
R79U and 80U are connected to 82U.

Gates 81tJ and 82U are 1. The logic "1" signal is gated at the clear timing by the start timing pre-occurrence function of the control timing generation circuit 60. Gate 8
The logic 11111 signal from 1tJ is led to the WAIJ register 25U and the FUWED flag 51U, and the logic "1" signal from the gate 82U is routed to the RAU register 26U.
and is guided by the FUEMP flag 52U. As a result, WAU register 25U1 RAU register 26U, FL
IWED flag 51U1 and FIJEMP flag 52
U is cleared. In this state, Marsha 10
Data processing specified by the LOAD (U) command in the P register 39 is performed at a speed synchronized with the input to the engine core 15.
~・ In II +1 Marcia 10, LOAD
(U) In response to the command, U
An operation is performed to store data (511 in this example) into B20U.

It is supplied at regular intervals in units of predetermined bytes. The data from the sort checker 14 is held in the INU register 21U in synchronization with the output cycle from the sort checker 14,
Guided by U B 20tJ. In the case of the LOAD (Ll) command, the main control unit 38 outputs the WAU register 25LI
Data is written to U B 20U using. That is, a write control section (not shown) in the main control section 38 controls the I
Writes the data held in the NU register 21U to the address of the UB 20U specified by the WAU register 25U selected by the multiplexer 29tJ,
Write control to increment the WALJ register 25tJ by 1 is repeatedly performed. The WAU register 25U is reset at startup as described above (No.

11), therefore, S11 is written in order from address 0 of the UB 20U.

When writing data to the U320U, the main control unit 38 sets the contents of the R8U register 43U (record length R3U) to the WRC counter 45 via the multiplexer 44 at the start of its operation, and writes the contents of the TRN register 42 (total number of records) to the WRC counter 45 via the multiplexer 44. TRN) becomes an underflow state by 1° when writing the final data of the STC counter, and outputs a borrow signal. The borrow signal from the WRC counter 45 is led to the STC counter 46,
As a result, the STC counter 46 is decremented by one. Therefore, the STC counter 46 enters an underflow state when writing the final data of the final record in S11, and outputs a borrow signal. The borrow signal from the STC counter 46 is commonly led to one end of A67U and 87L. The U/L bit in the MOP register 39 is led to the other end of A67U via the inverter 66, and the U/L bit is led as is to the other end of A67L. Therefore, U/L
In this example where =O, the AND condition of A 137U is satisfied, and from A 67U to the FUWED flag siu,
A logic “1” signal is output. This causes the FUWE
The D flag 51U is set (■LOAD in Fig. 11).
(See the columns for the (U), ENG, and Go commands). The write control section in the main control section 38 stops the write control operation in response to the borrow signal from the STC counter 46. As a result, the contents of the WAU register 25U (311) become the storage address of the final data of the sub-relation (last - koi'', V code).1-+, t2. The matter is indicated by "endJ".

"7The set output signal from the FUWED flag 51U is
You will be guided to one end of A72U. A load signal 71U from the decoder 70 is guided to the other end of A72U. The decoder 70 decodes the contents of the MOP register 39M0P register 39, and in the case of a LOAD (U) command as in this example, the load signal 711 of logic II 1 II
Output J. Therefore, in this example, by setting the FUWED flag 51U, the AND condition of A72U is satisfied, and from A72U (indicating completion of writing to UB20U by executing the LOAD (U) command) logic u 1
The IT signal is output. Logic “1°° from A72U
The signal is led to the interrupt generation circuit 7G via the OR 75, thereby causing the interrupt generation circuit 76 to
Generates an interrupt. The CPU 11 is Marsha 1
When an interrupt from 0 (internal interrupt generation circuit 76) is accepted, the contents of a status register (not shown) in marsha 10 (this register consists of FUWED flag 51U, FLWED flag, IL1FUEMP flag 52U, FLEMP flag 52, etc.) is read and the cause of the interrupt is determined.

When the CPU 11 determines that writing of the sub-relation (S11) to the UB 20U is completed by reading the status from the Marsha 10, it performs setup regarding the next sub-relation, that is, 821 in the second relation. The setup in this case is S11 described above.
This is almost the same as the setup for Note that since the effective data length VDL is common to each record of the first relation $1 and the second relation S2,
No setup is required except in the case of S11. Therefore, in the case of 321, the registers to be set up are:
MoP register 39, oSLA register 54L10SL
B register 55L, R3L register 43, and TR
This becomes the N register 42. However, the MOP register 39 contains merge operation specification information (
SORT-EX (L) command) is set. Then, 3ii
Similarly to the above case, the Marsha 10 is started again by setting the ENG and Go commands. At this time, the clear circuit 61 clears the WAL register 25L, RA
L register 26L, FLWED flag 51L1 and F
The LEMP flag 52 is cleared (reset). That is, the U/L bit of the merge operation designation information set in the MOP register 39 is logic "1", and the CMD register 41
Command data set in (REG).

ENG, Go bit in IND-0) is logic 11111
In this case, the AND condition of A78L in the clear circuit 61 is satisfied, and a logic 111 II signal is output from A78L. The logic “1” signal from A78L is 0R79L.
It is led to the gate 81L through 0R791°80L, and to the gate 821 through 0R791°80L. Gate 81L
.

82L gates the logic II 1 II signal at the clear timing by the start timing generation 1m function of the control timing generation circuit 60. The logic “1” signal from gate 81L is sent to WAL register 25L and FL.
The logic "1" signal from the gate 82L is guided by the WED flag 51m and is sent to the RAL register 26 and FLEMP.
It is guided by flag 52L. Due to this.

WAL register 25L1 RAL register 26L, FLW
The ED flag 51L and FLEMP flag 52L are cleared. In this state, marsha 10 performs data processing specified by the 5ORT-EX (L) command in M0P register 39. An operation is performed to store this data V-data (521 in this example). , At this time, the corresponding data (321) is sorted from the sorter 12.
A predetermined byte unit is supplied to the marsher 10 at a constant cycle via the checker 14, and IN is synchronized with this supply cycle.
It is held in the L register 21L. 5ORT-EX (L
) command, a write control unit (not shown) in the main control unit 38 of the merge t10 writes data to the IJ B 20LI using the WAL register 25L. That is, the write control unit in the main control unit 38 writes the data held in the INU register 21L to the address of LB2OL specified by the WAL register 2SL, and
Write control to increment the register 25L by 1 is repeatedly performed.

The WAL register 25L is reset at startup (■5ORT-EX, εNG, G in FIG. 11).

(See command column), therefore 321 is written to the class from address O of LB20L.

In the case of writing data to LB2OL, the main control unit 38 enters an underflow state when writing the final data of the contents of the R3L register 43 at the start of its operation, and outputs a borrow signal. The borrow signal from the WRC counter 45 is guided to the STC counter 46, and the STC counter 46 is thereby decremented by -1. For this reason, the STC counter 46
becomes an underflow state when writing the final data of the final record of 321, and outputs a borrow signal. STC
The borrow signal from the counter 46 is commonly led to one end of A67U and 67L. At the other end of A67U, the U/L bit in the MOP register 39 (lt) is connected to the inverter 6
The U/L bit is directly connected to the other end of A67L. Therefore, in this example, which is U/L-1, the AND condition of A67L is satisfied, and A67
L to FLWED flag 51L, logic 111 I
I signal is output. As a result, the FLWED flag 51 is set (■5ORT-EX in Fig. 11).
L'), ENG, see the Go command column). The count-up operation will be stopped when the main control is indicated (end).

In this example, read/write operations for tJ B20LI (L 820L) are performed in a time-division manner. That is, one operation cycle in marsha 10 is divided into a read cycle and a write cycle.5
In the case of the ORT-EX (L) command, a read control unit (not shown) in the main control unit 38 executes a CMP 28L that compares the content WAL of the WAL register 25L and the content RAL of the RAL register 26L, and the content WALI of the WAU register 25LI, 8 and the contents RALJ of the RALI register 26tJ are monitored. And RAL<WAL.

If RAU<WAU, the read control unit determines that data can be read from L82OL, and in the read cycle, reads data from L82OL using RAL register 26L.
Data read from OL and RAU register 26U
Data is read from the UB20LJ using the RAU register 26U and RAL register 2 simultaneously.
Add 1 to the contents of 6L. Data is loaded into this -20L. Then, the above operation is repeated. RAU
As described above, the register 26U and the RAL register 2GL are reset at startup (see FIG. 11), so data is read from the UB20USLB20L starting from address ○.

When reading data from UB20U and LB2OL, when reading the first data of one record, the contents of RAU register 26U and RAL register 26L are stored in BUU register 27U and BUL register 27L, and the contents of R8LI register 431J1R8L register 43L are stored in RCU counter 49U, The contents of the VDL register 47 are sent to the RCL counter 49L, and the contents of the VDL register 47 are sent to the VCT counter 48.
The data is loaded at the specified timing from the control timing generation circuit 60 in 8 to start processing one record. RCtJ counter 49LJ1 RCL counter 49L1 and VCT counter 48 are decremented by 1 every time data is read from UB20U and L820L. In this example, the records supplied to the marsher 10 are preprocessed by the IN aligner 13 so that the key field to be compared is at the beginning, and a signal is output. A borrow signal from the VCT counter 48 is guided to a comparison control section 62. Also, R.C.U.
The counter 49U and RCL counter 49L go into an underflow state when reading the final data of the U-side code with a record length of R3U and the L-side code with a record length of R8L, and the borrow 5:! indicates the end of the record. Output a signal. Borrow signals from the RCU counter 49U and RCL power counter 49L are guided to the FUE flag 50U and 'jFc+=flag 50L. As a result, the same flag 50U, 50
L is let, indicating that the final data of one record is to be read.

The data read from UB20U and LB20L is
It is held in the R register 22U and the LOW register 22S. The data held in the IJPR register 22U and LOW register 22L is led to the CMP 23. In addition, the data held in the UPR register 22U and LOW register 22L is OTU
I N via register 24U and oTL register 24L
It is also guided to the UR register 31U and INLR register 31L, and held in the same registers 31U and 31L.

The CMP 23 compares the magnitude of both data from the UPR register 22U and the LOW register 22L. The comparison result of CMP 23 is led to comparison control section 62 within main control section 38 . The comparison control unit 62 determines the comparison result between the specified key fields with the borrow signal 2 indicating the end of the key field from the CT counter 48, and sends the comparison result of the CMP 23 to the control signal generation circuit 65. tell to. On the other hand, in the case of tJ-L, since the comparison result cannot be determined, the determination of the comparison result is refrained from being determined until the comparison result for the next data is given. However, if the end of the key field (key field end) is detected by the borrow signal from the VCT counter 48, the U
=L, and transmits the match detection result from the CMP 23 to the control signal generation circuit 65. In addition, in the above explanation, U is U
Indicates read data from B20U, and L indicates read data from LB2OL.

On the other hand, INUR register 31tJ, INLR register 3
The read data from UB20U and LB20L held in 1L is transferred to IJ in parallel with the comparison operation by CMP23.
R830U, LRB30L1. : Written. This U
RB50U SL The write address for RB50L is set to 1 by the RAUR registers 35U and 35m. RAUR register 35 USRALR register 35
is cleared when one record is written, so the data read from UB20U and LB20L is URB30USLRB~, 301. L
is written from address O.

;The control timing generation circuit 60 in the main control section 38 is
The states of the tJE flag 50U and FLE flag 50L are monitored. When the control timing generation circuit 60 detects that both the FUE flag 50U and the FLE flag 50L are set, that is, the final data of the record with the longer record length of the U-side code and the L-side code is detected. When detecting the reading of (U RB 30
(assuming that reading and outputting one record from the U or LRB 30L is possible) gives timing instructions for outputting various control signals to the control signal generating circuit 65. The control signal generation circuit 65 generates the MRG-OP code and As/DS in the merge operation specification information held in the MOP register 39 at the specified timing from the control timing generation circuit 60.
Depending on the bit and the comparison result from the comparison control section 62, various control signals are generated to control the read address for the UB201J1LB20L, the interrupt control section 63, the output control section 64, and the like. In a preferred embodiment,
Control signal generation circuit 65 is a ROM.

The control signal generation circuit 65 is set to 1 when external sorting is specified by the MRG-OP code (that is, assuming that ascending order sorting is specified), the control signal generation circuit 65 is set to 1.
5, if the comparison result is U=L or Uj<L,
The next record is read from the UB 20U, and a control signal is output from the LB 20L instructing the current record to be read again. This control signal is, for example, a load signal to the RAU register 26U1RAL register 26L,
In this case, a load signal to the RAL register 26L is output.

When the load signal to the RAL register 26L is output (from the RAL register 26L at the start of record processing)
The start address of the current record loaded into the BUL register 27L is loaded into the RAL register 26L.

This makes it possible to read out the current record again in order from the first data in the same way as reading data from the LI 820L described above.

On the other hand, the RAtJ register 26U indicates the address of the next data (in this case, the start address of the next record), and there is no equivalent change. In this case, the next record can be sequentially read from the first data in the same manner as the data reading from the UB 20U described above.

Further, the control signal generation circuit 65 outputs a valid (logical 1'') output instruction signal 85U that instructs the output of the record written in the URB 301J.On the other hand, if the comparison result is u > L l' , in the case of +□1, tJ
The current record is output from B20U again, the next record is read from LB20L, and a valid (logical 1) signal is output that instructs the output of the record written to LRB301. Output instruction signal 85m
Output.

Further, the control signal generation circuit 65 outputs the comparison result and the AS/
Interrupt enable signal 7 valid regardless of state on DSS/
Outputs 4U and 74L.

Now, by the control signal from the control signal generation circuit 65, LJ
Read next record from B20U and La2O2
reading of the current record from the logical I
It is assumed that the output instruction signal 85LI of I I IT is output. Logic from control signal generation circuit 65 +11 II
The output instruction signal 85U is guided to the FUO flag 53U, thereby setting the FLIO flag 53LI.

The output sequence control unit 83 monitors the states of the FU○ flag 53U and the FLO flag 53L, and when the FUO flag 53U is set as in this example, the output sequence control unit 83 instructs the URB readout control unit 84U to read the record from the URB 30U. Instruct read output. URB read control unit 84U
RA according to instructions from the output sequence control section 83
UR register 35U and UCTRCTR counter 56, and corresponding IURAUR register 35U
B Read data from 30U. URB 3
The read data from 0Ll is sent to the ROUT register 33 via the multiplexer 32 (which selects the URB30U side when reading from the IJR830U is specified).
guided by. The URBI output control unit 211 section 84LI is
Every time a predetermined byte of data is read from RB 30U,
The contents of the RAIJR register 35U and CTR counter 56 are incremented by 1, and an output strobe signal 87U is output. This output strobe signal 87U is guided to gate 88 via OR86.

Gate 88 outputs the output signal from OR 86 (output strobe signal 87U in this example) to ROtJT register 33 in response to output permission from extraction control section 89.

Regarding the tile production of this cutting control section 89, please refer to the JO
We are planning to explain in detail using an IN-type performance as an example, and here it is assumed that output permission is given to the gate 88 during the reading period from the first data to the last data of one record written in the U RB 30U. omitted. Upon output permission from the extraction control section 89, the data latched in the output castrope signal UT register 33, which is the output signal from the gate 88, is transferred to an HM (not shown) via the HMA 17. In addition, during the period of reading data from URB30U, the next record is read from UB20U and LB20L, and the same record is read in units of hides URB301J, L.
It is also possible to write from address 0 (RB30Lf7).

In this case, read/write operations for URB50LJ, LRB50L are performed by tJ820LI, L820
Similar to that for L, it is necessary to perform this in a time-sharing manner.

The above operation is repeated and the CMP 28L compares the contents of the WAL register 25L and the RAL register 26L.
It is assumed that a match has been detected. In this case, the CMP 28L outputs a match detection signal of logic 11111. This coincidence detection signal is led to one end of A68L. The other end of A68L has a logic II 1 IJ with FLWED flag 51m.
The output signal of is guided. This is F L w E
This is because the D flag 51L is in the set state as described above. In this case, the AND condition of A68L is satisfied, and A
A signal of logic 11111 is output from 68L. This A
A logic "1'' signal from 68L indicates that B20L is empty. Logic II 1 T from A68L
The + signal is guided to Genit 69L. Genit 69L is
The logic at 1 T1 signal from A68L is gated at the specified timing (record end detection timing) from the control timing generation circuit 60.

As a result, the logic ii 1 n signal from A68L is F
It is output to the LEMP flag 52L, and the flag 52L is set. Logic +11 from FLEMP flag 52L
The IJ output signal is routed to one end of A73L.

An interrupt enable signal 74L from the control signal generation circuit 65 is led to the other end of A73L. In this case, the interrupt enable signal 741 is at logic "1" (see FIG. 13) as described above, and therefore A73L outputs a signal at logic 111IJ. The logic "1" signal from A73L is O
It is led to the interrupt generation circuit 76 via R75, and thereby the interrupt generation circuit 76 generates an interrupt to CP LJ 11. When cpu ii receives an interrupt from the marsher 10 (interrupt generation circuit 76 therein), it performs setup regarding relation 322 in the status register (not shown) in the marsher 10. The setup in this case is almost the same as the setup for S21 described above, and the MOP register 39 contains the MRG-OP code that specifies external sorting, the As/D8 bit that specifies sorting, and the logic that specifies L820L. II
Merge operation specification information (S
ORT-EX (L) command) is set. Then, set 1.52 to CMD register 41 within merge 171°.
As in case 1, marsha 10 is started again by setting the ENG and Go commands. At this time, the clear circuit 61 causes the WA
L register 25L, RAL register 26L, FLWED
The flag 51L (and FLEMP flag 52L) is cleared (reset) (■5ORT-EX in Figure 11).
(L), ENG, GO co-7nd (see DllllII)
. On the other hand, WAU register 25U, RAU register 26U
, FUWED flag 51U (and FUEMP flag 5
2U) holds the state at the time of interruption to the CP IJ 11 (ie, at the end of the operation). Therefore, the register 26U indicates the start address of the next record. This state, i.e. the sub-relation (51 in this example)
1) is indicated by "any" in FIG. 11.

When the clear circuit G1 performs a clear operation, the marsher 10 clears 5ORT-EX(
L) Data processing specified by command 1! ! (The first record among the unprocessed records of the sub-relation (511 in this example) remaining in the outer 20U, and on the L side (since the RAL register 26L is cleared) the sub-relation newly written to the LB 201 ( In this example 522
) External sorting is performed from the first record. As a result of this external sort, when LB2OL becomes empty again,
CPU 11 again uses 5ORT-Ex(L), ENG,
Using the GO command, specify 823→UB20U and instruct external sort. As a result, external sorting is started from the first record of the remaining portion of 811 and the first record of S23. Then, when UB20U becomes empty this time, CPU 11 uses 5ORT-EX (U),
Using ENG, Go command (■ in Figure 11), S12
→Specify UB20U and instruct external sort.

In this case, the clear circuit 61 clears the logic 111 II of U/
5ORT- according to L bit and ENG, Go bit
Contrary to the EX (L), ENG, and GO commands, the U
External sorting is started from the first record of the remaining registers and flags related to B20U, ie, WAU register 25U, RAU registers 26U, F, and 323.

In this way, the merge sort is performed in the marsha 10, and all the final relations 323 of the first relation S1 are output to the outside.

do. In this case, since LB20L is empty, the FLEMP flag 52L is set, and Marsha 10(
An interrupt is applied to the CPU 11 from an interrupt generating circuit 76) in the CPU 11. When the CP tJ 11 receives an interrupt from the Marsha 10, it determines the cause of the interrupt. and,
When the CPU 11 determines that the LB 20L is empty and all relation S2 of the 1st and 2nd has been output, the CPU 11 issues a PASS-1 (U) that instructs the LI 820U to output the remaining data (remaining part of S12). , M.R.G., G.
Give the o command to Marsha 10. MRG in this case
, Go command is MRG, G.

-1, REG, IND=R8T-ENG, GO-tJR
TRY=LRTRY-0. Marsha 10 is MRG
, the process started by the Go command and specified by the PASS-1 (U) command, that is, RRY-LRTRY-0
Therefore, the clear operation by the clear circuit 61 is prohibited. Therefore, the register related to tJB20U,
The flags, namely, the WAU register 25U, the RAU register 26U, and the FUWED register 51U (and the FUEMP flag 52U) are in the previous state, that is, 5 shown in (■) in FIG.
ORT-EX (U), ENG, holds the state at the end of execution of the Go command. As is clear, the RAU register 26U specifies the first record of the record group left in the UB 20U. Therefore, the read control section (not shown) in the main control section 38 of the marsha 10 can sequentially read out the remaining portion of S12 in predetermined byte units. Then, when the remaining portion of 312 is discharged, that is, UB20U
When tlo becomes empty, the FUEMP flag 52U is set and an interrupt is placed on merge tlo.

c p u 1i receives an interrupt from Merge-rPlo and determines that LB20L is empty and all the remaining 812 has been ejected, and then inputs the uninput data to Marsha 10 (in this example, the end of the first relation S1). REG
, IND-R3T=MRG, GO=URTRY-LRT
It is RY-0. Marsha 10 is activated by ENG and GO commands, and HM A 16, IN aligner 13,
Writing S13 input via the sorter 12 and sort checker 14 to the UB 20U and reading and outputting S13 written to the UB 20U are performed. These read and write operations are carried out by the above-mentioned 5ORT-EX (L), ENG
, is basically the same as the Go command. Also, when starting with the ENG and Go commands above, the ENG
, GO=1 (and U by PASS-1(U) command
5ORT-EX (L), E
As in the case of the NG and Go commands, only the registers and flags related to UB20U are cleared by the clear circuit G1. Therefore, S1 input to marsha 10
3 is written from address O of U320LI and read from address O as well.

The above is the external sorting process performed by marsha 10.

FIG. 16 corresponds to FIG. 13. , RESTRI CT-based operations are operations that output only records that meet the conditions from one target relation. In the RESTRICT type calculation by the martja 10, the item data of item -1 is stored in advance in the UB20U as the first stream, and the target relation is stored in the LB20U as the second stream.
While storing in L, calculation is started and - is performed. This point is similar to the case of the external sort (SORT type operation) described above. Then, the specified key field of the condition data is compared with that of the target relation, and when the calculation condition is satisfied, the L side record is selected as the output target in the output selection section O.
Sent to 8P. Note that it is also possible to set the U-side record as an output target together with the side-side record.

Now, assuming that the first relation as condition data is 81 and the target relation (second relation) is 82, the CPU 11 first sends LOAD to Marsha 10.
(Ll) command specifies S1→US20U, and ENG and GO commands start Marsha 10 (including engine core 15).

This causes Sl to be UB2, similar to the case of external sorting.
The data is sequentially written in predetermined byte units starting from address O of 0U. Then, by writing data only to R3UxTRN, S
A borrow signal is output from the TC counter 46, and FUW
When the ED flag 511J is set, an interrupt is generated from the marsher 10 to the CP IJ 11.

Next, the CPU 11 specifies S2→LB20L from the REST-EQ (L) command knee, and executes the REST-EQ (L) command.
- Indicate EQ. This REST-EQ indicates that the target relation is output when the key field of the condition data is equal to that of the target relation. Then, the CPU 11 starts up the Marsha 10 (including the engine core 15) using the ENG and Go commands. The subsequent operation is substantially the same as in the case of the above-mentioned external sort (ie, 5ORT-EX command). That is, in marsha 10, the registers and flags related to LB2OL are first cleared, and then the operation of writing S21 to the area starting from address 0 of LB20L is started. When data writing to LB20L is started, data reading from U3201J and LB20L is started. UB20U and LB2
The read data from 0L is led to CMP23,
23 and the comparison control unit 62, the VDL register 47
The comparison of the key field specified by is confirmed, and the same URB3 is guided by URB30U and LRB30L.
01J, written to LRB30L. However, UB2
When the data read from 0U1LB20L becomes the final data of the corresponding record, the FUE flag 50U and FLE flag 50L are set as described in the external sort operation (Which one is set first depends on the record length), control timing The generation circuit 60 generates both flags 50
When both U and 50j are set, timing instructions for outputting various control signals are given to the control signal generation circuit 65. As a result, the control signal generation circuit 65 controls the MOP
MRG in the merge operation designation information held in the register 39.

In response to the Go command, AS/DSS/up, and the comparison confirmation result from the comparison control unit 62, u s 20U 1
LB20L record update control, UB20U, LB2
Instructs to output records written to the OL.

Then, the FUE flag 50U and FLE flag 50L are reset, and the next record process is performed.

Note that when the REST-EQ operation is specified as in this example, the input/output logic of the control signal generation circuit 65 is the first one.
As shown in Figure 6. However, the input/output logic in FIG. 16 is based on the assumption that the input relations to the marsher 10 are sorted in ascending order (AS/DS=O).

In this way, REST-EQ (L), ENG, G
The operation specified by the o command is executed, for example, the 15th
As shown in the figure, the contents of the RAL register 26 are ~
It is assumed that the value matches that of the VAL register 25L and a match detection signal is output from the CMP 281. In this case, as in the case of the external sort described above, the FLEMP flag 5
2L is set and an interrupt is issued to the CPU 11. Thereby, the CPU 11 determines whether or not the marshaller 10 has completed the calculation. This is because a coincidence detection signal is output from CMP281J, and F.

The same applies when the UEMP flag 52U is set.

In such a state, there may be cases where it is desired to perform another calculation on the data stored in UB20U and LB2OL. In this case, only the Marsha 10 is activated, so basically the MRG and Go commands are used. However, the MRG and Go commands shown so far do not clear the registers and flags related to 1J320U or 1B2OL, as described above. In this case, UB20
It is not possible to perform a desired operation from the beginning of the data in U and LB20L. Therefore, in this embodiment, as shown in (■) in FIG. 14, the URTR
MRG with Y and LRTRY specified.

Go command, i.e. MRG, Go-URTRY=LRT
RY=1, REG, IND-R8T=ENG, Go-0
MRG and Go commands are applied. As shown in the clear circuit 81 in FIG. 7, the URTRY bit is set to 0R80.
The LRTRY bit is led to one end of 0R80L. Therefore, URTRY−LRTRY=
In this example of 1, i EFOR80tJ, 80L
The output level of is logic "1".

Therefore, at the start timing from the control timing generation circuit 60, the RAU register 26U and FUEMP flag 520 are cleared in response to the URTRY pit, and the RAL register 26L and FLEMP flag 52L are cleared in response to the LRTRY bit. On the other hand, W
'AtJ register 25tJ1WAL register 25L, F
Regarding the UWED flag 51U and the FLWED flag 51L, the previous state, that is, the REST-E shown in ■ in FIG.
Holds the state at the end of execution of the Q (L), ENG, and Go commands. Therefore, a desired operation (REST-NE (L) operation in this example) can be performed on the data stored in the UB20USLB20L starting from the first data. In addition, in the REST-NE command,
When the key field of the condition data is not equal to that of the target relation and a record update for LB2OL is performed, the forward side data (record) becomes the output target.

Next, RESTRICT operations (REST-EQ operations) for target relations exceeding the capacity of LB2OL will be explained with reference to FIGS. 17 and 18.

Note that the 17th factor corresponds to FIG. 11, and FIG. 18 corresponds to FIG. 12. Now, the first relation as condition data is 81, and the target relation (second relation) is 82.
shall be. Further, it is assumed that S2 is divided into 321 to S23 according to the capacity unit of the RAL register 28L. Note that the condition data Sl is the RAtJ register 2GU
It is assumed that the capacity will not be exceeded. In this case, C.P.
First, from U 11 to Marsha 10, LOAD (U
), ENG, and Go commands are given. As a result, the registers and flags related to the CMP28U are cleared (OAD (LJ) and ENG in Figure 17).

(See Go command column), Sl is written in predetermined byte units from address 0 of UB, 20U. When the writing of Sl is completed, the CPU 11 sends RE, 5 to the Marsha 10.
T-EQ (L), ENG, and Go commands are given. As a result, the registers and flags related to LB20L are cleared (■REST-EQ (L) in Figure 17).
, ENG, Go command), 321 to L820
The operation of writing to the area starting from address 0 of L is started.

When data writing to LB2OL is started, data reading from U B 20U and LB20L is started as described above, and the key field portions specified by the DL register 47 are compared. And FUE7
When both the lag 50U city and the FLE flag 50L are set, the U B 20U
.

Output instructions and record updates for the record written to L82OL are controlled, and processing proceeds to the next record.

In this way, REST-EQ (L), ENG, G
The operation specified by the o command is executed, for example, the 17th
As shown in the figure and ■ in Fig. 18, the RAL register 2
The contents of 6L match that of WAL register 25L, and C
It is assumed that a coincidence detection signal is output from the MP28L.

In this case, as in the case of the external sort described above, FLE
The MP flag 52 is set and an interrupt is issued to CPU. As a result, c p u il becomes Sl
The end of the calculation between and S21 is determined. CP Ll 1
1 is the RES between the next 822 and Sl in UB2OU
For T-EQ operation, REST
-EQ (L), ENG.

Give the G○ command. However, as for Sl, it is necessary to read from the first record again, so as shown in ■ in FIG.
IND=R8T=MRG.

MRG and Go commands with GO=LRTRY=O are applied. The ENG and Go commands specified by URTRY are applied. In this case, when starting up the marsha 10, the RAU register 26U and the FUEMP flag 52U are cleared by the clear circuit 61 in FIG. 7 according to the IJRTRY bit of logic "1", and the ENG, G
o pit (and LB2OL specification by U/L bit)
WAL register 25L, FLWED flag 51 according to
L, RAL register 26L, and FLEMP flag 52 are cleared. In addition, WAU register 25USFUWE
The D flag 51U retains its previous state. Therefore, it becomes possible to read Sl already written in the UB 20U from its first record. In addition, correct detection is also possible when all of Sl is read and tJB20tJ becomes empty. On the other hand, it is clear that S22 is written to LB20L from the first record and read from the same first record.

In this way, REST-EQ (L) as well as U
The operation specified by the ENG and Go commands specified by RTRY is executed, and the contents of the RAU register 26U match those of the WAtJ register 25U, for example, as shown in Figures 17 and 18, and a match detection signal is sent from the CMP 28LI. Assume that is output.

In this case, the FUEMP flag 52U is set and the CPU
11 is interrupted. As a result, CPLlll determines that the calculation between $1 and 822 has ended.

The CPU 11 provides REST-EQ (L) and ENG and Go commands specified by URTRY to the marsher 10 for the next REST-EQ operation between 823 and 81 in the UB 20U. This allows UB2
The REST-EQ operation between Sl already written in 0U and S23 newly written in LB20L is performed from the first record.

Next, regarding relational calculation processing by merge w10, JO
The case of IN type calculation will be explained as an example. A JOIN type operation is a so-called two-stream input synthesis output type operation in which specified key fields of two relations are compared and a new relation is created using a set where a condition is met. For example, JOIN-E, which is one of the JOIN-based operations,
In the Q operation, two records whose specified key fields match are combined and output as one record. In JOIN operations using merge tlo, after storing the first stream in UB20U by specifying the LOAD (U) operation,
IN (L) The second relation is set to L by specifying the system operation.
A JOIN operation is performed while storing in B2OL. Then, the designated key field of the read record from U B 20U (U side code) is compared with that of the read record from LB2OL (L side code),
When the calculation conditions are satisfied, an instruction to output the U-side and L-side codes is given from the control signal generator circuit 65. JOI
FIG. 19 shows the input/output logic of the control signal generation circuit 65 in the N-EQ calculation. However, the input/output logic in FIG. 19 is based on the premise that the input relations to the marsher 10 are sorted in ascending order. Note that in JOIN-based operations, the first and M2 relations are UB20U,
The capacity of LB201L must not be exceeded, and the sorting must be the same. The same sort type means that the above 5OR
The same applies to T-based operations and RESTRICT-based operations.

Now, the read records from UB20U and LB20L are read from URB30U in parallel with the comparison operation by CMP23.
, written to LRB30L. Then, when the FtJE flag 50U and the FLE flag 50L are both set, that is, when the reading of the final data of the U-side code and the L-side code are both detected, the control signal generation circuit 6
5 is LIB20U as in the case of external sorting described above.
, instructs to output records written to LB2OL, and controls record updating. In this example of the JOIN-EQ operation, assuming that U=L is determined in the comparison control section 62, the control signal generation circuit 65 performs the logic as shown in the input/output logic in FIG. Output instruction signals 85U and 85L of 11111 are output. This logic 11111
The signals 85U and 85L are the FUO flag 53U and FLO
It is guided by the flag 53L, which causes the same flag 53 (J,
It climbs 53m. The output sequence control section 83
The FUO flag 53U and FLO flag 53L are monitored.

As in this example, FUO flag 53U, FLO flag 5
When both 3L are set to Z, the output sequence control unit 83
First, the UB20U is sent to the URB readout control unit 84U.
It instructs the readout and output of records from the U-side code, and also instructs the extraction control section 89 to perform extraction control for the U-side code. The uRsi output control unit 84U clears the RAUR register 35U and UCTR counter 56 in response to instructions from the output sequence control unit 83, and then clears the RAUR register 35U and UCTR counter 56.
Data is read from LI R830LI using register 35U. The read data from UR"830U is sent to the ROUT register 33 via the multiplexer 32.
guided by. The URB read control unit 84U
It is led from 30LI to a predetermined byte to 59L and compared with SUA register 54tJ, SUB register 55U1R3U register 43LI, 08LA register 541, 03LB register 55L, and R8L register 43L. CM
The comparison results of P57tJ, 58U and CMP57L, 58L are led to the cutting control section 89.

When the cutout control unit 89 is instructed to control the cutout of the U-side code from the interrupt control unit 63, it starts CMP 57U and CMP 58U. Then, the cutting control section 8
9 indicates the position within the record of the data currently being read.
If the contents of the TR counter 56 (in this example, match the contents of the RAIJR register 35U, that is, the read address for the URB 30U) are X, then CM P 571J
, 57U Niyoi) OS U A ≦X≦08U
During the period when B is detected, exit permission is given to the gate 88. As a result, the URB readout control unit 84 is
The output strobe signal 87U from URB is led to the ROLI lower register 33, and the read data from URB 30U is sent to R.
It is latched into the OtJT register 33. Therefore, 0
8UA (first cutting position) and osus <second
By setting the cutout position) to an appropriate value, it is possible to selectively cut out and output only a desired feature from the U-side code to be output. This also applies to the L side cord. h 83.03UA (O3LA
) = O1osUS (O3LB) - R8UI7) In the case niha, one record's worth of data is output as is.

When the data read from the URB 30U becomes the final data of the corresponding record, the CMP 59LJ goes into an overflow state and a borrow signal is output from the CMP 59LI. When the URB read control unit 84U c receives a borrow signal from the CMP 59U, it determines that record reading has ended and notifies the output sequence control unit 83 to that effect. The output sequence control section 83 is an LJR8 readout control section 84.
The end is notified from U, and FLO flag 5 is set as in this example.
When 3L is set, the LRB continuous output control unit 84L
It instructs the LB 20L to read and output records, and also instructs the extraction control section 89 to perform extraction control for the L-side code. As a result, in the same way as in the above case, 08LA≦X≦08LB of the L side code
The data of the field portion that satisfies the above is extracted and output.

Note that in the above embodiment, the first record among the records to be output is
Although the case of center cutting in which the field portion sandwiched between the first and second cutting positions is cut out has been described, side cutting in which the outside portion thereof is cut out is also possible. Further, by providing a flag specifying center cutting/side cutting, it is also possible to deal with both center cutting and side cutting.

[Effects of the Invention] As described in detail above, according to the present invention, various relational operations can be performed efficiently by specifying the operation specification information.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block configuration diagram of a marsha according to an embodiment of the present invention, FIG. 2 is an overall configuration diagram of a relational database engine (RDBE) to which the marsha of FIG. 1 is applied, and FIG. Figure 4 is a format diagram of merge operation specification information, Figure 4 is a format diagram of command data, Figure 5 is a block diagram showing the different function configuration of the main control section shown in Figure 1, and Figure 6 is shown in Figure 5. Figure 7 is a block diagram of the area surrounding the interrupt control unit, Figure 7 is a circuit diagram of the area around the clear circuit shown in Figure 5, Figure 8 is a block diagram of the area around the output control unit shown in Figure 5, and Figure 9 is a diagram of the external sort. Figure 1o is a schematic diagram showing the procedure of external sorting, and Figure 11 is a diagram showing the command sequence for executing external sorting, and the contents of various registers and flags at the time of startup and termination by each command. Diagram showing correspondence, 1st
Figure 2 shows the U/L at the end of execution of each command shown in Figure 11.
13 is a diagram illustrating an example of the input/output logic of the control signal generation circuit when external sorting is specified. FIGS. It corresponds to Figures 11 to 13,
Figures 17 and 18, which are diagrams for explaining RESTRICT system operations, correspond to Figures 11 and 12. Figure 19, which is a diagram for explaining operations, shows JOIN operations (J
3 is a diagram illustrating an example of input/output logic of the control signal generation circuit when the control signal generation circuit (OIN-EQ) is specified; FIG. 10...Marsha, 11...CPLJ120LJ・
...U buffer, 20L...shi buffer, 23.28
U, 28L, 57U-59U. 57L to 59L... Comparator (CMP), 27U...
BUU register, 27L...BUL register, 38.
...Main control unit, 39...MOP register, 41...
CMD register, 42,...TRN register, 43U
...R8U register, 43L...R8L register,
47...VDL register, 50U...FUE flag, 50L...F'LE flag, 51U...FUWE
D flag, 51L...FLWED flag, 52U...
・FUEMP flag, 52L...FLEMP
Flag, 53U...FUO flag, 53m...FL
O flag, 54U...08UA register, 54L...
・oSLA register, 55LJ...03LJB register, 55L...03LB register, 61...Clear circuit, 62...Comparison control unit, 63...Interrupt control unit, 64...Output control unit, 65 ...Control signal generation circuit, "89... Cut-out control section. Applicant: Director of the Agency of Industrial Science and Technology Hirobe Kawada Figure 3 Figure 4 Main tA'J #mυ" 5s Figure 6 Figure 7 Figure 9 Figure 10 Figure 11 Figure η Figure UB LB ■ Figure 13 Figure 14 Figure 16 Figure 17 Figure 19

Claims (1)

[Claims] A first buffer that stores the first relation, a second buffer that stores the second relation, an operation code that indicates the operation type, and a buffer designation bit that designates either the first or second buffer. a first register to hold; a second register to hold record number information indicating the number of records of the relation stored in the first or second buffer;
a third register that holds record information indicating the record length of the relation stored in the buffer; a fourth register that holds key field length information indicating the key field length of the relation; and the above-mentioned information held in the first register. If load processing is specified by the operation code, the second buffer is stored in the buffer specified by the buffer specification bit among the first or second buffer.
A relational operation is specified by the means for writing the relation of the amount of data indicated by the number of records specified by the register and the record length specified by the third register, and the operation code held in the first register. If so, the data indicated by the number of records specified by the second register and the record length specified by the third register is stored in the first or second buffer specified by the buffer specification bit. a third buffer for temporarily storing data for one record read from the first buffer; and a third buffer for temporarily storing data for one record read from the first buffer. A fourth buffer temporarily stores data for one record read from the second buffer.
a buffer, a comparison circuit that compares both records read from the first and second buffers between the key fields specified in the fourth register, and a comparison result of the comparison circuit and the first register. means for controlling the updating of read addresses for the first and second buffers and controlling the output of the records temporarily stored in the third and fourth buffers to the outside according to the held operation code; A data processing device comprising: