JPS6160515B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a MOS static type semiconductor memory device.

(2) Prior art and problems Generally, in a MOS static type semiconductor memory device, a static type memory cell configured as a flip-flop is provided at each intersection of a word line and a bit line pair, and a row address buffer, a row address decoder, column address buffer,
1 by addressing means such as a column address decoder.
One word line and one bit line pair are selected, ie, one memory cell is selected.
In this case, actual word line selection is performed by the word line driver clock signal after the row address decoder determines the selected row. When one word line is selected in this way, a large number of unselected memory cells connected to that word line are also electrically connected to the bit line pair. For example, in a 16K bit memory, 127 unselected memory cells are also electrically connected to the bit line pair. This results in current flowing from the bit line to the memory cell. The power consumption of a static semiconductor memory device is mainly due to driving such a bit line load.

Conventionally, if the word line is in the selected state, that is, after receiving an external signal (RAS signal, etc.), the word line driver clock signal becomes high level, and one of the word lines is always in the selected state and the slave However, there was a problem in that the power consumption was large.

(3) Purpose of the Invention The purpose of the present invention is based on the concept of generating a word line driver clock signal only for a predetermined period of time after an address change. The object of the present invention is to reduce the current flowing to the cells and also reduce the power consumption in the row address decoder, thus reducing the power consumption and solving the above-mentioned problems in the conventional type.

(4) Structure of the invention In order to achieve the above-mentioned object, according to the present invention,
a static memory cell provided at the intersection of a plurality of word lines and a plurality of bit line pairs; a word line selection means for selecting the word line; a bit line selection means for selecting the bit line; an output buffer that latches the data read through the buffer, and a first buffer that detects changes in the input address.
and a second detection means for detecting that the output of the word line selection means has reached the end of the word line, and the word line selection means and the bit line selection means are connected to the first detection means. A static type semiconductor memory characterized in that the selection operation is performed only during the period from when the output of the second detecting means is generated until the output of the second detecting means is generated, and the output buffer latches data during the period. Equipment is provided.

(5) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 1 is a block circuit diagram showing an embodiment of a static semiconductor memory device according to the present invention.
In FIG. 1, known static type memory cells Cij (i, j=0, 1,..., n-1) are arranged in n rows and n
Arranged in a matrix of columns, each memory cell has one
It is connected to one word line and one pair of bit lines. For example, memory cell C ₀₀ is connected to word line WL ₀ ,
It is connected _to bit lines BL _0,0 . The word lines WL ₀ , WL ₁ , . . . , WL _o-1 are selected by row selection signals X ₀ , X ₁ , . . . , X _o-1 of the row address decoder RD. In this case, the row address decoder RD receives the address signals A ₀ ,
₀ , A ₁ , ₁ , ... A _l-1 , _l-1 (2 ^l = n) are decoded, but the above-mentioned row selection signals X ₀ , X ₁ , ..., X _o
The generation of _-1 is conditional on the generation of the word line driver clock signal φw of the word line driver WD. Moreover, the bit lines BL ₀ , ₀ , BL ₁ , ₁ ,...,
BL _o-1 , _o-1 are column selection gates Q _B0 , Q _B0 ′, Q _B
1 , Q _B1 ',..., Q _B , n-1, Q _B , n-1', respectively, and each gate pair receives a column selection signal _Y0 ,
Controlled by Y ₁ ,..., Y _o-1 . That is,
Selection of the bit line pair is performed by column selection signals Y ₀ , Y ₁ , ..., Y _o-1 of the column address decoder CD. In this case, the column address decoder CD selects the address signal A ₀ of the column address buffer CB. ′, ₀ ′, …, A _l-1 ′,
Decode _l-1 ′. The bit line pair is connected to the data bit line DB through the selected column selection gate. A sense amplifier SA is connected to the data bit line DB, and an output buffer OB is further connected to the subsequent stage.

The word line driver WD is set by the clock pulse _CP1 of the clock pulse generating circuit _CK1 , and by the clock pulse _CP2 of _the clock pulse generating circuit CK2. The clock pulse generation circuit CK ₁ receives address signals A ₀ , A ₁ , ..., A _l-1 ,
The clock pulse generation circuit CK 2 generates the clock pulse CP ₁ by detecting changes in _{A 0} ′, A 1 ′, ..., A _{l-1 ′} , while the clock pulse generation circuit CK ₂ generates the row selection signals X 0 , X ₁ , ..., X _o Detects the rising edge of _-1 and generates clock pulse CP ₂ . This clock pulse generation circuit CK ₂ is connected to the word line.
It is located at the end opposite to the row address decoder RD in WL ₀ , WL ₁ , ..., WL _o-1 . That is, the clock pulse generating circuit _CK2 detects when the row selection signal propagates to the end of the word line and generates the clock pulse _CP2 .

FIG. 2 shows the memory cells C ₀₀ , C ₀₁ , C ₁₀ ,
It is a circuit diagram of _C11 . In FIG. 2, each memory cell is composed of loads R ₁ and R ₂ , drive transistors Q ₁ and Q ₂ which are cross-coupled and form a flip-flop, and transfer gate transistors Q ₃ and Q ₄ . transfer gate transistor
Q ₃ , Q ₄ are bit lines BL ₀ , ₀ (or BL ₁ ,
₁ ), and their on/off state is controlled by the row selection signal _{X 0 (} or X ₁ ) on the word line WL ₀ (or WL 1 ). For example, if the row select signal _X0 goes high, the current _ILO
A current flows from BL ₀ to the transistor Q ₁ in the on state of the memory cell C ₀₀ , and a current I _L1 flows from the bit line BL ₁ to the transistor Q ₁ in the on state in the memory cell C ₀₁ . That is, in this case, even if the memory cell C ₀₀ is the selected cell, current also flows in the non-selected cell C ₀₁ . Since there are 127 such unselected cells in a 16K bit memory, reducing such current is advantageous in terms of power consumption.
The present invention reduces the time during which the row selection signal _X0 is at a high level even when the word line, for example _WL0 , is in the selected state, thereby reducing power consumption.

Returning again to FIG. 1, the circuit operation will be described with reference to FIGS. 3A to 3I. As shown in Figure 3A,
When any one of the row address signals A ₀ , A ₁ , ..., A _l-1 or the column address signals A ₀ ′, A ₁ ′, ..., A _l- 1 changes, the clock pulse generation circuit CK ₁ detects the change. Detection generates a clock pulse _CP1 shown in FIG. 3B. As a result, the word line driver WD is set to generate the word driver clock signal φw shown in FIG. 3C, and subsequently, the row selection signal of the selected word line changes as shown in FIG. 3D. . In this manner, as the selection operation progresses, the potential at the end of the selected word line changes to high. The clock pulse generating circuit _CK2 detects this and generates the clock pulse _CP2 shown in FIG. 3E. As a result, the word line driver WD is reset, its word driver clock signal φw changes to low as shown in FIG. 3C, and then the row selection signal
also changes to low as shown in FIG. 3D. Therefore, the selected state of the word line is maintained only between clock pulse _CP1 and clock pulse _CP2 .

During this time, the selected bit line pair receives the column selection signals Y ₀ ,
Data bit line pair by one of Y ₁ ,..., Y _o-1
DB, and this potential changes as shown in FIG. 3F. This data bit line pair DB,
The potential of is amplified by the sense amplifier SA, and the sense data SD shown in FIG. 3G is obtained.
This sense data SD is latched into a latch circuit in the output buffer OB. If the output of this latch circuit is D, it is shown as shown in Fig. 3H, and therefore, the output D _OUT of the output buffer OB is the third
It will look like Figure I. That is, since the data D of the latch circuit is determined between the clock pulse _CP1 and the clock pulse _CP2 , it is not necessary to maintain the word line in the selected state after the clock pulse _CP2 is generated. From this point of view, in the present invention, the selected state of the word line is canceled after the clock pulse _CP2 is generated, thereby reducing the power consumption of the memory cell.

FIG. 4 is a circuit diagram of the word line driver WD of FIG. 1. In FIG. 4, Q ₄₁ and Q ₄₂ are load transistors, Q ₄₃ and Q ₄₄ are transistors forming a flip-flop, and Q ₄₅ and Q ₄₆ are input transistors. That is, clock pulse CP ₁ acts as a set pulse, and clock pulse CP ₂ acts as a reset pulse. Therefore, the word driver clock signal φw is the clock pulse CP ₁
and reset by clock pulse _CP2 .

Figure 5A shows the clock pulse generation circuit in Figure 1.
FIG. ₁ is a block circuit diagram of CK1. In FIG. 5A, the clock pulse generating circuit CK ₁ is a pulse generating circuit for each address signal A ₀ , A ₁ ,..., A _l-1 , A ₀ ', A ₁ ',..., A _l-1 '. It has PG ₁ and ORGATE OR ₁ . This pulse generating circuit _PG1 detects a change in its input and generates a pulse of a constant width. For example, as shown in FIG. 5B, the pulse generating circuit PG ₁ includes NAND gates G ₁ to G ₄ , NOR gates G ₅ , G ₆ , OR gate G ₇ , and a capacitor.
It is composed of C ₁ and C ₂ . In this case, the gate
G ₁ , G ₂ , G ₅ , and capacitor C ₁ constitute a rising edge detection circuit; gates G ₁ , G ₃ , G ₄ , G ₆ , and capacitor C ₂
constitutes a rising edge detection circuit. Therefore, the gate
The output of _G7 detects the rise and fall of address signal Ai, that is, changes, and generates pulse _CP1 . By providing such a pulse generating circuit _PG1 for each address signal, the clock pulse generating circuit _CK1 generates the clock pulse _CP1 when any of the address signals changes.

Figure 6A shows the clock pulse generation circuit in Figure 1.
FIG. ₂ is a block circuit diagram of CK2. In FIG. 6A, the clock pulse generating circuit CK ₂ has a pulse generating circuit PG ₂ and an OR circuit OR ₂ for each row address signal X ₁ , X ₂ , . . . , X _o-1 . This pulse generating circuit _PG2 detects the rising edge of its input and generates a pulse of a constant width. For example, the pulse generating circuit PG ₂ is composed of gates G ₈ and G ₉ , an OR gate G ₁₀ and a capacitor C ₃ as shown in FIG. 6B.

(6) Effects of the Invention As explained above, according to the present invention, since the time that the word line is in the selected state is reduced, the current flowing from the bit line to the memory cell and the power consumption in the row address decoder are reduced. Therefore, power consumption can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing one embodiment of a static semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram of memory cells C ₀₀ , C ₀₁ , C ₁₀ , and C ₁₁ in FIG. 1, and FIG. Figures A to I are timing diagrams of signals appearing in the circuit of Figure 1, Figure 4 is a circuit diagram of the word line driver WD of Figure 1, and Figure 5A is a block diagram of the clock pulse generation circuit CK1 of Figure ₁ . Circuit diagram, FIG. 5B is a logic circuit diagram of the pulse generation circuit PG ₁ of FIG. 5A, and FIG. 6A is the clock pulse generation circuit of FIG. 1.
The block circuit diagram of CK ₂ , FIG. 6B, is a logic circuit diagram of the pulse generating circuit PG ₂ of FIG. 6A. C ₀₀ to _{C o-1} , n-1: static memory cell, WL ₀ , WL ₁ ,..., WL _o-1 : word line, BL ₀ ,
₀ ,...,BL _o-1 , _o-1 : Bit line, RD: Row address decoder, RB: Row address buffer,
CD: Column address decoder, CB: Column address buffer, SA: Sense amplifier, OB: Output buffer,
_CK1 , _CK2 : Clock pulse generation circuit, WD: Word line driver, φw: Word driver clock signal.

Claims (1)

[Claims] 1. A static memory cell provided at the intersection of a plurality of word lines and a plurality of bit line pairs, a word line selection means for selecting the word line, a bit line selection means for selecting the bit line, and the bit line selection means for selecting the bit line. an output buffer for latching data read out through the line; a first detection means for detecting a change in the input address; and a detection means for detecting that the output of the word line selection means has reached the end of the word line. said word line selection means and said bit line selection means perform selection operations only during a period from when the output of said first detection means occurs until the output of said second detection means occurs. A static semiconductor memory device characterized in that the output buffer latches data during the period.