JPS6154708A - Differential input circuit - Google Patents

Abstract

PURPOSE:To improve in-phase voltage characteristics (CMRR) greatly by shielding a hold capacitor, and controlling the potential of the shield so that it follows up the ground potential of the hold capacitor and also wiring both terminals of the hold capacitor so that wiring impedance values at both terminals are equal to each other. CONSTITUTION:Drain-source resistances of FETs Q1 and Q2 of a shield potential control circuit SD vary according to the potential e1 of a plus-side signal line and the potential e2 of a minus-side signal line, and the potential of the shield SI is controlled in following-up to the ground potential of the hold capacitor Ch. Consequently, even when stray capacities C1 and C2 are present, there is no charge entering and exiting from the hold capacitor Ch through those capacities and CMRR is improve greatly. Further, the both-terminal wiring of the hole capacitor Ch is branched from wiring shown by a thick line while equal impedance Z1 is held. Therefore, variations of the hold capacitor Ch with impedance Z1 are suppressed for fast charging and discharging by the effect of the stray capacities C1' and C2'.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a differential input circuit having a switch and a flying capacitor on the input side of a differential amplifier.

(Prior Art) FIG. 2 is a connection diagram showing a conventionally known flying capacitor type differential input circuit. In the figure, ei is the input signal, eCM is the common mode voltage of the input signal @ei, Sl is the first switch that takes in the input signal ei, and ch receives the input signal ei via the first switch S1 and holds it. Hold capacitor (flying capacitor), S2
is a second switch that is turned on at a timing different from that of the first switch S1, and Ul is a differential amplifier that receives the input signal ei held in the hold capacitor ah via the second switch S2.

R is a resistor connected between each input terminal of the differential amplifier U1 and the ground (common line). CI and C2 indicate stray capacitances existing between both ends A and B of the hold capacitor ah and the ground.

In the circuit having such a configuration, the first. The second switches 81 and 82 alternately operate on and off.

They cannot be turned on at the same time. Hold capacitor Ch
holds the input signal @ei at the timing when the eleventh switch S1 turns on, and outputs the input signal @ei to the input terminal of the differential amplifier U1 at the timing when the second switch S2 turns on.
Communicate.

Here, the ground potential of the hold capacitor ah is the common mode potential e of the input signal ei when the first switch S1 is on.
When the second switch S2 is on, the resistor ff1 is applied to CH.
Due to the action of R, it becomes -er/2. The differential amplifier PJU1 outputs a signal e, which is equal to the single-ended input signal ei from which the in-phase component of -ei/2 has been removed.

In this circuit, the common-mode voltage rejection characteristic (Q ommonMo
de Rejection Ratio (abbreviated as CMRR) is determined at the time of transition of the ground potential of the hold capacitor channel. The change in the ground potential of the hold capacitor channel is floating 1! Charges are on FffiC1 and C2,
It is generated by charging and discharging through the resistor R. 1st
At the timing when the second switch S2 is turned on from the turn on of the switch S1, both ends A of the hold capacitor Ch are turned on.
, [The potentials el and e2 at the three points are approximately C1 and R, respectively.
,02·R. At this time, C,1・R−
If it is C2/R, is it in the hold capacitor channel? lJ
No movement occurs and good CMRR can be obtained.

(Problem to be Solved by the Invention) Therefore, the relationship between each stray capacitance may be shifted from C1-C2, but in reality, it is not easy to set it to Cl-02 due to various constraints, etc. hold capacitor ch
The hold value ei fluctuated, making it impossible to significantly improve CMRR.

In the actual circuit, there is also a floating capacitance ff1C1' at the 0 point and the D point, which are downstream of the second switch S2.

C2' is present. Potentials e, , e at point 0 and point D.

is at ground potential when the second switch S2 is off,
When turned on, it becomes the common mode potential ecM. For this reason, the stray capacitances fftc1 and C2 around the hold capacitor ch,
Floating capacitance DC1' near point 0 and point D.

An instantaneous charge movement occurs between C2' and the unbalanced stray capacitance of the positive and negative signal paths is transferred to the hold capacitor C2'.
This results in a charge fluctuation of h.

The present invention was made in view of these problems, and its purpose is to eliminate the stray capacitance formed between various parts and printed circuit board patterns, etc., and to create a difference that can significantly improve CMRR. The objective is to realize a dynamic input circuit.

(Means for Solving the Problems) The present invention solves these problems by using a first switch that takes out an input signal, and holds the input signal taken out through the first switch. In the differential input circuit, the differential input circuit has a hold capacitor that is connected to the hold capacitor, and a second switch that applies the signal held in the hold capacitor to the input terminal of a differential amplifier at a timing different from that of the first switch. A shield potential control circuit is provided to provide a shield and control the potential of the shield so that it follows the ground potential of the hold capacitor, and only the wiring at both ends of the hold capacitor is connected to the first... This is characterized in that the wires are branched from the wires of the second switch and the shield potential control circuit, and wired so that the wire impedances at both ends are equal.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a connection diagram showing an example of the circuit of the present invention.

In this figure, parts corresponding to the parts of the circuit of FIG. 2 are denoted by the same reference numerals, and their explanations will be omitted.

In this embodiment, a shield S'■ is applied to the hold capacitor ch, and a shield potential control circuit SD is provided to control the potential of the shield Sr to follow the ground potential of the hold capacitor ch. or,
Connect the wiring at both ends of the hold capacitor 1ch to the 1st. Second
The switch S1° 82 and the shield potential control circuit SD are branched from each wire (the wire indicated by a thick line in the figure) and are connected to each other via the same impedance z1.

The shield potential control circuit SD includes a FET Ql whose gate is given a + side signal path potential e+ (a potential applied to one end of the hold capacitor Ch via an impedance Z1).
, FETC2 whose gate is supplied with negative side signal potential C2 (potential applied to the other end of hold capacitor Ct+ via impedance z1), and each FETQ1. Q2
A constant current circuit CC is configured to supply a constant current to the series circuit of each FET and the resistor. Each FETQ1. Drain of Q2.

The resistance between the sources changes according to the potential el of the + side signal path and the potential ez of the − side signal path, and the potential of the shield 81 is controlled to follow the ground potential of the hold capacitor ch.

When the potential of the shield 31 is controlled to be equal to the ground potential of the hold capacitor ch, even if there is a stray capacitance fic1°C2, the hold capacitor Ch
There is no charge flowing in and out of the , and its influence disappears,
CMRR can be significantly improved.

Also, 1st. Second switch 81.82. FETQl,C
The wiring shown by the thick line connecting 2 and the two resistors R is connected at the shortest distance, and the wiring at both ends of the hold capacitor channel is as follows.
The wires are branched from the wiring shown by the bold line, maintaining the same impedance z1.

By adopting such a structure, the stray capacitance ff1c1.02 of the hold capacitor ch becomes the smallest, and there is an impedance Z1 in series with the hold capacitor Qh. Therefore, stray capacitances c1', C2'
With respect to high-speed charging and discharging due to the effect of , fluctuations in the hold capacitor channels are suppressed by each impedance z1.

Here, each FETQ1. of the shield potential control circuit SD. Q
A structure in which the gate of No. 2 is directly connected to both ends of the hold capacitor Ch is also considered, but in this case, each F
ETQ1. The gate capacitance of Q2 accelerates charging and discharging of the hold capacitor Ch, making it impossible to follow the operation sufficiently. Therefore, it is important to branch only the wiring at both ends of the 2%-field capacitor channel from the wiring shown by the thick line.

The time constant of fast charging TL lightning is in the range of several ns to several tens of ns, and the length of the wiring at both ends of the hold capacitor Qh of several cm has sufficient effect, and no special resistance is inserted as the impedance 21. Alternatively, if the impedance is set to z1 and a resistor is inserted and connected, there is no need to lengthen the wiring length, and the mounting efficiency improves.

(Effects of the Invention) As explained above, according to the present invention, even if there is stray capacitance formed between various parts or printed board patterns, the influence of the stray capacitance can be eliminated and the CMRR can be significantly improved. A differential input circuit can be realized.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing one embodiment of the present invention, and FIG. 2 is a connection diagram of a conventional circuit. ei...Input signal Sl...First switch S
2...Second switch ah...Hold capacitor Sl...Shield

Claims (1)

[Claims] A first switch that takes out an input signal, a hold capacitor that holds the input signal taken out through this first switch, and a hold capacitor that holds the input signal that is taken out through this first switch, and a hold capacitor that holds the signal held in this hold capacitor at a timing different from that of the first switch. In a differential input circuit having a second switch applied to the input end of a differential amplifier, the hold capacitor is shielded and the shield potential control is controlled so that the potential of the shield follows the ground potential of the hold capacitor. A circuit is provided, and only the wiring at both ends of the hold capacitor is branched from each wiring of the first and second switches and the shield potential control circuit, and the wiring is arranged so that the wiring impedance at both ends is equal. Differential input circuit.