JPS6152702A - Sequence controller - Google Patents

Abstract

PURPOSE:To give opportunities for processing equally to plural processing request signals by outputting a counting pulse signal at each sequence control end time to count up the counted value of a counting circuit and using this counted value as a select signal to select a processing request signal and performing a corresponding sequence control. CONSTITUTION:Processing request signals S1-S4 are inputted to a signal selecting circuit 22 with waveforms shown in figures (a)-(d). When a counting pulse signal f1 is outputted from a sequence control circuit 10 to a signal line 18, a counting circuit 20 counts up counted value ''11'' to ''00'', and this counted value ''00'' is outputted as the select signal to signal lines 16 and 14 (waveforms g1 and h1). The select signal ''00'' means that the processing request signal S1 is selected in the signal selecting circuit 22, and the selected processing request signal S1 is outputted to a signal line 12 (waveform e1). The select signal ''00'' is inputted to the sequence control circuit 10 also, and the signal selecting circuit 22 is informed of selection of the processing request signal S1. Since the signal S1 at this time is in the low level, a prescribed processing is executed in the sequence control circuit 10.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a sequence system in which processing is performed respectively corresponding to a plurality of processing request signals. This relates to the ff1l device. [Prior Art] In a conventional sequence control device of this type, a priority is determined in advance for each processing request signal, and when a plurality of processing requests occur simultaneously, processing is performed in order of priority. However, in the case of such a processing procedure, if high-priority processing requests occur consecutively, all of the processing for low-priority processing requests that occurred at the same time will not be completed until the processing of the high-priority processing requests is completed. [Invention] Summary of the Invention The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a sequence control device that gives equal processing opportunities to a plurality of processing request signals. In order to achieve such an object, the present invention outputs a counting pulse signal every time sequence control ends to count up the counted value of the counting circuit, and uses this counted value as a select signal to select a processing request signal and respond. The present invention will be described in detail below along with examples. [Example] Fig. 1 is a block diagram showing an example of the present invention. The sequence control circuit 10 includes: This is a circuit that performs a predetermined sequence control process determined based on a selection signal inputted manually from the signal line 14 or 16, and whether or not to perform the sequence control process depends on the state of the processing request signal inputted manually from the signal line 12. In this processing request signal, a low level means on, that is, "execute a predetermined process," and a high level means off, that is, "no processing is required." In addition, the sequence control circuit 10 l!i: When the +, digit sequence control process is completed, a counting pulse signal is output to the signal line 18. FIG. 2 is a flowchart showing the processing procedure in the sequence control circuit 10. In step 101, the counting pulse signal After the process is generated, the process proceeds to step 102 to check the state of the manually input processing request signal.If the process request signal is on, the process proceeds to step 103 to execute a predetermined process, and if the process request signal is off, step 101 The process returns to generate a counting pulse signal. When the predetermined processing is completed in step 103, the process proceeds to step 104 and the state of the processing request signal is confirmed. Normally, the processing request signal is turned off when the predetermined processing is completed.
This is because after confirming this, the process returns to step 101 to generate a count pulse signal and start searching for the status of another processing request signal. The counting circuit 20 constitutes a 2-bit binary counter, and when the counting pulse signal from the signal line 18 is input manually, the counting circuit 20 counts up its own count value by one count. This count value is output as a select signal to signals vA14 and 16, and the lower value is output to the signal line 14 and the upper value is output to the signal line 16 in the form of a binary bell signal. Now signal line 14
．． If the signal outputted in 16 is high level, rlJ is low level, it is "0", then the select signal has four states, namely (00) (01
)(10)(11). In addition, signal line 1
4.16 extend to both the sequence control circuit 10 and the signal selection circuit 22. The signal selection circuit 22 selects four types of processing request signals 31 to S4.
are input via signal lines 241 to 244, respectively, and a processing request signal 5 is input based on a select signal from the counting circuit 20.
A predetermined processing request signal is selected from among signals 1 to S4. For example, select signal

If [00] is input, the processing request signal S1 is selected.The selected processing request signal is output to the sequence control circuit 10 via the signal line 12. The operation will be explained using the timing chart in FIG. 3. FIGS. 3(a) to 3(d) are waveform diagrams for the signals "! , (f) in the same figure is a waveform diagram on the signal line 18, and (g) and (h) in the same figure are waveform diagrams on the signal lines 16 and 14.Currently, the No. 13 selection circuit 22 receives processing requests No. 13 S1 to S
4 is input in the waveforms shown in FIGS. 3(a) to 3(d). When the counting pulse signal (waveform fl in FIG. 3) is output from the sequence control circuit 10 to the signal line 18, the counting circuit 20 counts up the count value [11] up to that point to (00).
), and this count value (00) is output as a select signal to the signal line 16.14 (waveform g1.hl in FIG. 3).

[00] means that the processing request signal S1 is selected, and the selected processing request signal S1 is output to the signal line 12 (waveform e in Figure 3).
l). In addition, the select signal

[00] is also input to the sequence control circuit 10 at the same time, and the signal selection circuit 22 knows that the processing request signal S1 has been selected. Since the processing request signal SL at this time is at a low level, the sequence control circuit 10 executes a predetermined process. A period T1 indicates a period during which processing is being executed for the processing request signal S1, and the sequence control circuit 10 waits for the processing to end and outputs a counting pulse signal (waveform "2" in FIG. 3). This waveform f2 is When output to the signal line 18, the counting circuit 2
0 counts up the count value again and makes the count value [01]
Then, the process continues in the same manner. Section T2. T3. T4 is the processing request signal S2゜S
4. (Execution of processing on Sl) Note that when the selected processing request signal is at a high level (waveform e2 in Fig. 3), the counting pulse signal is output without any processing being performed in the sequence control circuit 10 (waveform
Figure waveform f3). Furthermore, in this embodiment, the maximum count value in the counting circuit 20 is 2 bits, and there are four types of processing request signals; however, if the count value is n bits, up to 2'' types of processing request signals can be selected. [Effects of the Invention] As explained above, according to the sequence system ?111 device of the present invention, the count pulse signal is output every time the sequence control is completed, the count value of the counting circuit is counted up, and the count value of the counting circuit is counted up. Since a processing request signal is selected using the count value as a select signal and the corresponding sequence control is performed, a plurality of processing request signals are given an equal opportunity to process.Therefore, it is necessary to process a specific processing request signal. This eliminates the inconvenience of delays.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing a processing procedure in the sequence control circuit 1o, and FIG. 3 is a timing chart. 10... Sequence control circuit, 2o... Counting circuit,
22...Signal selection circuit.

Claims (1)

[Claims] A sequence control circuit that performs predetermined sequence control according to a select signal and a processing request signal, and outputs a counting pulse signal after the sequence control is completed, and a sequence control circuit that increments an n-bit count value by one count by inputting the counting pulse signal. A counting circuit outputs this counted value as a selection signal, selects a processing request signal corresponding to the selection signal from among a maximum of 2^n types of processing request signals, and sends the selected processing request signal to the sequence control. A sequence control device comprising: a signal selection circuit for outputting a signal to a circuit.