JPS6151869A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase electric capacitance without augnmenting the occupying area of a memory cell by forming a plurality of grooves onto the surface of a substrate constituting a capacitor section at predetermined fine pitches. CONSTITUTION:An element isolation region 2 is formed to a substrate 1, and sections except a sections corresponding to a memory capacitor are coated with photo-resists 9. A photo-resist 10 is applied onto the whole surface of the substrate 1, and fine striped patterns are shaped onto the photo-resist 10 through laser holography. The striped patterns may be shaped onto the whole surface of the substrate regardless of foundation patterns at that time, thus requiring no mask-alignment accuracy needed for forming normal fine patterns, then forming fine patterns by a simple process. The substrate 1 is etched in predetermined depth while using the photo-resist patterns as a mask to shape striped patterns with fine irregularities to the memory capacitor 7 section. A memory storage is manufactured according to a normal process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a structure of a dynamic semiconductor memory device that performs a storage operation by accumulating charge in a capacitor, and a method of manufacturing the same.

[Conventional technique 1 (i)] Fig. 1 is a diagram showing a cross-sectional structure of a conventional memory cell composed of one transistor and one capacitor. In Fig. 1, the memory cell has a memory capacitor 7 and a transfer gate. 8. The memory capacitor 7 includes a semiconductor substrate 1 and a very low gate insulator fAQ 3 a formed thereon.
W1 is formed from the memory cell plate 4 provided via the memory cell plate 4. A voltage from a power supply C is applied to the memory cell plate 4. The transfer gate 8 includes n+ diffusion regions R6a, 6b formed on the surface of the semiconductor substrate 1, and n+ diffusion@1g,
6a.

A gate electrode (word line) 5 is provided on a charge transfer region between 6b with an extremely thin oxide film 3b interposed therebetween. One n+ diffusion fi4 region 6a is connected to a signal read/write bit line.

An element isolation region [2] made of a thick insulating film made of, for example, 5t02 is formed at one end of the memory cell, and is electrically insulated from adjacent memory cells.

The operation of the above-mentioned memory cell will be explained below.

When the dielectric constant of the gate insulating film 3a is ε, the film thickness is t, and the area of the memory capacitor 7 is S, the electric capacitance C of the capacitor 7 is C-εS/l. When voltage V from the power supply Vcc is applied to capacitor 7 having electric capacity C, electricity ff1Q accumulated in memory capacitor 7 becomes Q=CV, and information is stored depending on the presence or absence of electricity ff1Q. Electricity mQ is transferred to the bit line of transfer gate 8, and electricity fd is transferred to the sense amplifier connected to the bit line.
The presence or absence of Q is detected, and the stored information is read out.

The conventional 11'-transistor-1-capacitor type memory cell is constructed as described above, and in order to increase the amount of electricity Q that accumulates in the capacitor section, it is necessary to increase the electric capacitance C of the capacitor section. There is. In order to increase the capacitance c, there is a method of reducing the thickness of the gate insulating film 3a (7) by 1 inch, and a silicon oxide film with a thickness of about 100 Å is being put into practical use.

However, if the gate insulating film is thinner than this, defects such as pinholes will increase, yield will decrease, and the electric field strength applied to the gate insulator 1rA3a will become extremely large, resulting in dielectric breakdown and other defects. The above problem arises. Furthermore, by increasing the area S of the capacitor, it is also possible to increase the electric capacitance c. However, this resulted in an increase in the area occupied by the memory cells, and became a major FIJ requirement in realizing a large capacity storage device with a high integration density.

[Summary of the Invention] An object of the present invention is to provide a semiconductor memory device that eliminates the drawbacks of the conventional device as described above and can increase the electric capacity without increasing the area occupied by memory cells, and its manufacture. The purpose is to provide a method.

In summary, this invention uses laser holography to form a minute 101 striped pattern on a photoresist on a semiconductor substrate, and uses this striped pattern of the photoresist as a mask to form a capacitor. A semiconductor memory device and a method for manufacturing the same, in which a plurality of grooves of a certain length m are formed on the surface of a semiconductor substrate, and the entire surface of the grooves is used as a main 11 pacitor area, thereby increasing the capacitor area. be.

The objects and other objects and features of the present invention will become more apparent from the detailed description given below with reference to the drawings.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a cross section of a memory cell structure according to an embodiment of the present invention. In FIG. 2, the same or corresponding parts as the corresponding parts in FIG. 1 are not indicated by the same reference numerals. As a feature of the present invention, the memory capacitor 7 in FIG.
．． Irregularities with a pitch of 5 μm or less are formed,
These irregularities increase the surface area S of the capacitor without increasing the area occupied by the capacitor.

If the pitch of the unevenness (distance between the center of a groove and the center of an adjacent groove) is △ and the depth is D, then the capacitor area S is S/5o=1 compared to the area So before the unevenness is formed. -G increases to 2D/△. For example, when D/A-0,5, S/So
=2. When D/Δ=1, S/5o-3, when D/Δ=2, S/5o-5, etc. The pitch of unevenness is 0.5
μm, if a groove with a depth of 1 μm is formed, D/A-2
According to the above equation, the surface area of the capacitor can be increased five times.

The smaller the pitch A of the unevenness is, the smaller the depth D of the groove can be, but it is practically difficult to form an uneven pattern with a pitch of 2 μm or less using ordinary photolithography technology.

In order to overcome this difficulty, the embodiments of the present invention employ a technique of forming fine striped patterns using laser holography.

FIG. 3 is a schematic diagram showing the principle of laser holography. In Figure 3, a laser beam (wavelength λ-325 nm) is generated from an @e-Cd laser oscillator, and a lens L
After converting the laser beam into a parallel beam with a beam diameter approximately equal to the size of the semiconductor substrate in step 2, the laser beam is converted into a parallel beam with a half mirror BS.
The laser beams are separated into 11M2. It is reflected by M3 and an image is formed on the semiconductor substrate coated with photoresist 1-. On the semiconductor substrate coated with photoresist, on the semiconductor U board coated with photoresist, there are two
An interference pattern of two sea 1f rays is formed.

The pitch Δ of this interference pattern is Δ=λ/ 2 sin θ. Therefore, for θ −90″, Δ−16
An interference pattern of 2.5n+++ was obtained, and the photoresist coated on the semiconductor substrate was exposed to light, and Δ=162.
A striped photoresist pattern with a pitch of 5n+++ is obtained.

FIGS. 48 to 4H are diagrams showing the manufacturing process of a semiconductor memory device using the above-described fine pattern forming method by laser holography. Hereinafter, the manufacturing process of the semiconductor memory device according to the present invention will be explained with reference to FIGS. 48 to 4H.゛Element isolation region v on semiconductor substrate 1
After forming A2 (FIG. 4A), the portion corresponding to the memory capacitor.

The remaining portions are covered with photoresist 9 (FIG. 4B). Next, in FIG. 4C, a photoresist I is formed on the entire surface of the semiconductor substrate 1.
-10, a fine stripe pattern is formed on the photoresist 10 using a laser hologram 1'. At this point, a striped pattern can be formed on the entire surface of the semiconductor substrate regardless of the underlying pattern, so there is no need for mask alignment required in normal fine pattern formation, making it a very simple process. can form fine patterns. Next, as shown in FIG. 4D, using the photoresist pattern as a mask, the semiconductor cloud 1 is etched to a predetermined depth to form a memory capacitor 7.
A striped pattern with fine irregularities is formed in the area. Thereafter, according to the usual steps, a thin insulating film 3 is formed (FIG. 4E), and a memory cell plate 4 is formed (FIG. 4E).
Formation of transfer gate 8 (FIG. 4G), source/drain (0" diffusion region) 68.6b, contact (not shown), phosphor glass layer 11, and aluminum wiring 12 (FIG. 4H) Figure) Manufacturing a semiconductor memory device.

[Effects of the Invention] As described above, according to the present invention, semiconductor memory! I! In addition, by forming a plurality of grooves in the capacitor portion, the capacitance of the capacitor is increased.

In addition, since Radhe holography is used as the manufacturing method for the grooves in the capacitor section, extremely fine pitches (0, 1
Grooves with a pitch of about 5 to 0.5 micron buttons can be formed without the need for mask alignment.

These features of the structure and manufacturing method make it possible to dramatically increase the electrical capacity of the memory capacitor without increasing the area occupied by the memory capacitor, and if such memory cells are used, large-capacity semiconductor memory V4 devices can be used. can be manufactured at high yield and at low cost.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross-sectional structure of a conventional memory cell. FIG. 2 is a V diagram showing a cross-sectional structure according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the ability to form fine patterns by laser holography. FIGS. 4A to 4H are process diagrams showing a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 is a semiconductor M, 2 is a device growth region, and 3.
3a and 3b are thin insulating films, 4 is a memory cell plate,
5 is a gate 1-if tM, 5a and 5b are n+ diffusion regions, 7 is a memory capacitor, 8 is a transfer gate, 9 is a photoresist, 10 is a photoresist, 11 is a phosphorus glass, and 12 is an aluminum wiring. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa 11th
Fig. 8 Axle load 'I''

Claims (3)

[Claims] (1) A semiconductor memory device that performs a memory operation by accumulating charges in a capacitor section composed of a semiconductor substrate, an insulating film, and an electrode, in which a certain fine pattern is formed on the surface of the semiconductor substrate constituting the capacitor section. A semiconductor memory device in which multiple grooves are formed at pitches. (2) The semiconductor memory device according to claim 1, wherein the certain fine pitch is 0.5 μm or less. (3) The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is a memory cell consisting of a transfer gate constituted by a MOS transistor and the capacitor. (4) A method for manufacturing a semiconductor memory device having a capacitor section composed of a semiconductor substrate, an insulating film, and an electrode, comprising the steps of: applying a photoresist on the surface of the semiconductor substrate; and the surface of the applied photoresist. An interference pattern is imaged on top using holography using short wavelength laser light,
forming a fine striped pattern on the photoresist; etching the surface of the semiconductor substrate constituting the capacitor portion using the formed striped pattern of the photoresist as a mask; and forming the insulating film. and forming the electrode on the formed insulating film.