JPS6150408A - Complementary mos transistor circuit - Google Patents

Abstract

PURPOSE:To obtain an oscillation amplifier oscillated and amplified normally to a minute amplitude signal while suppressing a through-current by connecting plural stages of inverters in series and connecting a large capacitance load to the intermediate point of a feedback resistor to the inverter connection. CONSTITUTION:Transistors (TR) Q4, Q9, Q5 and Q10 of transfer gate type acting like feedback resistors are arranged in series between an input point (a) of the 1st stage inverter 11 and an output point (b) of the 3rd stage inverter 13. The feedback resistor is divided into two, a large capacitance load C2 is connected to the midpoint (g) to form a delay circuit. Thus, a proper delay time is applied to a large amplitude waveform at the point (b) to a degree giving an effect onto the input section of the point (a). Thus, the effect of the output section onto the input is prevented by providing a delay means having a large time constant to an input signal frequency to a feed back section.

Description

[Detailed description of the invention] P) Industrial application fields The present invention relates to a complementary MOS transistor circuit.

(b) Prior Art This type of complementary MO8) transistor circuit is often used in applications such as oscillation amplifiers. FIG. 3 shows a conventional oscillation amplifier. In Figure 1, (1) is the one-stage inverter of the oscillation amplifier body connected between the power supply VD + and ground, K
is a feedback resistor to set the operating point near the circuit threshold. (2) is an inverter for waveform shaping connected between power supply Vt+nt and ground.

In this case, the input is often a waveform such as a sine wave that is very rounded compared to a rectangular wave.
), the through current was large. Therefore, there is a method to reduce the through current by lowering the drive capacity of the inverter (1), but due to loads such as the input load capacitance of the inverter (2) and the feedback resistor R, the point (al) is added to the point (bl). The input signal waveform cannot be sufficiently amplified.As a result, the through current in the inverter (2) increases, and even if the current consumption in the amplifier body can be reduced, the inverter that receives the output of this amplifier body The current consumption in (2) increases, and the overall current consumption cannot be reduced.In addition, as another method, Japanese Patent Publication No. 57-54965 has been proposed.However, the input is a minute amplitude signal. In such a case, in addition to the problem of through current, there is a problem that the input section is influenced by the output section due to feedback, and oscillation cannot be performed normally.

(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points, and provides an oscillation amplifier that can normally amplify the oscillation width for inputting a minute amplitude signal while suppressing the through current. Complementary type MO8) to obtain
The present invention provides a transistor circuit.

4. Means for Solving the Problems The complementary MO5) transistor of the present invention has a plurality of inverters connected in series, and a large capacitance load connected to the intermediate point of the feedback resistor for the inverter connection.

-) Effect According to the circuit of the present invention, the amplification factor is increased while suppressing the through current by connecting the inverters in multiple stages, and the delay effect of the feedback signal of the large capacitance load connected to the feedback resistor prevents malfunction. This makes it possible to increase the oscillation width for small amplitude signal inputs.

(F) Embodiment Adopting the complementary MO8 transistor circuit of the present invention OS transistors Q10 are N-channel MO8 transistors, complementary MO3 transistors Q1 and Q6 . Q
2 and Qy, Qs and Q8 are connected between the voltage @ VDll 7- and the three-stage series connected inverter circle,
It consists of In addition, the point (3) at the input section of the first stage inverter (111) and the point Tbl at the output section of the third stage inverter α
Transfer gate type transistors q4 and Q9, which act as feedback resistors between Q4 and Q9. Q5 and Qlo are arranged in series. Incidentally, C1 is a coupling capacitor of the input section (1) and is usually connected outside the IC. R1 is input protection resistor, C2
is the delay circuit capacitance.

Therefore, the driving capacity of the inverter (11) is kept quite small, and the inverter (12) is also set to have the same size as the inverter (11) so as to suppress its driving capacity. Therefore, the through current at the inverter (11) can be suppressed, and the waveform at point (e) becomes a considerably amplified waveform because the capacitance at point (el) is set small. Current can also be suppressed.

Although the driving capacity of inverter 0■ is large, the point (f
Since l has a waveform with a considerably large amplitude, the through current in the inverter (2) can also be considerably suppressed. In this way, it is possible to obtain a waveform with the same amplitude as the power supply voltage of the three inverters αtotaa.

Next, I will explain the return section. Usually, a feedback resistor is inserted between the input section and the output section as shown in FIG. However, in the case of a three-stage configuration and the input is a minute amplitude signal, the large amplitude signal at the output section affects the minute amplitude signal at the input side, making the oscillation state unstable or causing malfunction. Therefore, in the present invention, the feedback resistor is divided into two as shown in FIG.
are connected to create a delay circuit. In this way, the large amplitude waveform at point (bl) will take an appropriate delay time before it starts to affect the input section at point (al).Now, if we pay attention to the midpoint (g) of the feedback resistor, we will get the following: Even if point (b) reaches a level close to ■DD, which is the highest power supply voltage, it will take some time for point (g) to reach the vDD level, and input point Before it rises sufficiently to the Vbb side from the circuit threshold, it is reversed,
The output point 1bl is also inverted. In the same way, the point (gl) attempts to drop from a level that is not very high above the circuit threshold to the GND level under the influence of the point (bl, but
Before going down to the D side, the input is inverted again and the influence of the output point (bl does not appear at the input point (λ1). Therefore, a delay means with a somewhat large time constant relative to the frequency of the input signal is used as feedback. By providing it in the section, it is possible to prevent the input from being influenced by the output section.

Furthermore, according to the three-stage configuration of the inverter +411, <12r, and 03, if a drop occurs at the input section of the signal, the center level will deviate from the threshold of the circuit, which will only make the oscillation unstable. mosquito,
If this amount of leakage increases, oscillation may even stop. However, according to the above-described circuit configuration of the present invention, the point (gl) in the diagram js1 is always near the threshold value of the circuit. Therefore, it exhibits sufficiently strong characteristics against a certain degree of leakage current.

Next, a case where the embodiment circuit of FIG. 1 is realized by a semiconductor integrated circuit disclosed in Japanese Patent Publication No. 59-25381, that is, a gate array, will be explained based on FIG. 2. Since R1 is an input protection resistor, it is excluded and the inverter Ql)
, 02 and α3 can be easily constituted by a group of transistors used to constitute a normal input buffer and output buffer prepared in the I10 interface cell of the gate array. In addition, the feedback resistance part normally requires a resistance value of several hundred ohms, but this can be achieved by using a 110 interface cell (21J).
Although it is difficult to realize this within the area, it is sufficient to secure a separate area for arranging the resistor. In other words, in the case of such a cable array, because of its shape, no elements are placed at the four corners @ of the chip, nor do they serve as wiring areas. By arranging a transistor with a large value, a feedback resistor as shown in FIG. 1 can be obtained. It goes without saying that it is possible to create a feedback resistor using a resistive material such as a diffusion layer or boy 5. Also, is Iso the basic unit? 'J is 9 As described above, with a gate array, the present invention can be realized without increasing the area of the current master chip.

In the above description, FIG. 1 shows an example in which the feedback section is composed of two resistors and one capacitor, but it goes without saying that the feedback section can also be implemented using a plurality of both resistors and one capacitor.

(g) Effects Since the complementary MOS transistor circuit of the present invention has the above-described configuration, even if a minute amplitude signal of only a few gmV is input, the DC through current can be kept low and the high-speed oscillation amplifier can be operated without malfunction. can be obtained. Further, this oscillation amplifier can be realized with a gate array.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of an oscillation amplifier as a complementary MO8) transistor circuit of the present invention, FIG. 2 is a plan view of a master chip of a gate array constituting the oscillation amplifier according to the present invention, and FIG. is a circuit diagram of a conventional oscillation amplifier. +I11, (2), 031...Inverter, q...
・Transistor, C...capacitance, λ...resistance.

Claims (1)

[Claims] Multiple stages of inverters made of complementary MOS transistors are connected in series, a feedback resistor made of a plurality of series resistors is connected between the first stage input section and the final stage output section, and a large capacitance load is placed at the midpoint of the feedback resistors. A complementary MOS transistor circuit characterized by being connected.