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JPS6149471U - - Google Patents

Info

Publication number
JPS6149471U
JPS6149471U JP13365184U JP13365184U JPS6149471U JP S6149471 U JPS6149471 U JP S6149471U JP 13365184 U JP13365184 U JP 13365184U JP 13365184 U JP13365184 U JP 13365184U JP S6149471 U JPS6149471 U JP S6149471U
Authority
JP
Japan
Prior art keywords
resist layer
solder resist
covered
land
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13365184U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13365184U priority Critical patent/JPS6149471U/ja
Publication of JPS6149471U publication Critical patent/JPS6149471U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す印刷配線基板
の一部の平面図、第2図は同上縦断側面図、第3
図は同上電子部品を実装した縦断側面図である。 1…基板体、2…配線、3…ハンダレジスト層
、4…端子ランド、5…電子部品、6…テストラ
ンド。
Fig. 1 is a plan view of a part of a printed wiring board showing an embodiment of the present invention, Fig. 2 is a vertical sectional side view of the same, and Fig. 3
The figure is a longitudinal sectional side view of the electronic component mounted thereon. DESCRIPTION OF SYMBOLS 1... Board body, 2... Wiring, 3... Solder resist layer, 4... Terminal land, 5... Electronic component, 6... Test land.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ハンダレジスト層で被覆された基板体上の配線
にハンダレジスト層で被覆されない電子部品接続
用の端子ランドが形成された印刷配線基板におい
て、前記端子ランドに近い配線上にハンダレジス
ト層で被覆されないテストランドを形成したこと
を特徴とする印刷配線基板。
In a printed wiring board in which a terminal land for connecting an electronic component that is not covered with a solder resist layer is formed on the wiring on a board body covered with a solder resist layer, a test in which the wiring near the terminal land is not covered with a solder resist layer. A printed wiring board characterized by forming a land.
JP13365184U 1984-09-03 1984-09-03 Pending JPS6149471U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13365184U JPS6149471U (en) 1984-09-03 1984-09-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13365184U JPS6149471U (en) 1984-09-03 1984-09-03

Publications (1)

Publication Number Publication Date
JPS6149471U true JPS6149471U (en) 1986-04-03

Family

ID=30692190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13365184U Pending JPS6149471U (en) 1984-09-03 1984-09-03

Country Status (1)

Country Link
JP (1) JPS6149471U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016514367A (en) * 2013-03-01 2016-05-19 クアルコム,インコーポレイテッド Package substrate with test pads on fine pitch trace

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5346712B2 (en) * 1976-04-27 1978-12-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5346712B2 (en) * 1976-04-27 1978-12-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016514367A (en) * 2013-03-01 2016-05-19 クアルコム,インコーポレイテッド Package substrate with test pads on fine pitch trace

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