JPS6148191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a binarization circuit that binarizes an analog electrical signal output from a photoelectric conversion device.

In a general optical character reading device, an analog electrical signal obtained by scanning paper on which characters or symbols are written with a photoelectric conversion device is converted into a character area and a background area using a binarization circuit. 2 corresponding to
This is converted into a value signal, and characters, symbols, etc. are identified based on this binary signal. Therefore, characters,
In order to accurately identify symbols, etc., even if the level of the analog electrical signal output from the photoelectric conversion device fluctuates due to fluctuations in the background, the binarization circuit must accurately identify the character area. It is necessary to output a binary signal corresponding to the background area and the background area.

Conventional binarization circuits perform binarization by comparing an analog electrical signal applied from a photoelectric conversion device with a fixed reference voltage. However, if the level of the analog electrical signal applied from the photoelectric conversion device fluctuates due to fluctuations in the light source that illuminates the paper or differences in reflectance between sheets, a fixed reference voltage is used. There was a risk that an incorrect binary signal would be output.

In addition, in order to improve such drawbacks, means for detecting the maximum value or minimum value, or both of the output for one row scanning or one column scanning among the outputs of the photoelectric conversion device is provided. The maximum value or the minimum value obtained by this detection means, or the value obtained based on both, is used as the threshold value for one row scanning or one column scanning, and binarization is performed. Binarization circuits have also been proposed. In this way, by changing the threshold value every time one row or one column is scanned, it is possible to prevent fluctuations in the light intensity of the light source or differences in the reflectance of the paper on which characters are written depending on the paper. Errors caused by this can be prevented.

However, even if the threshold value is changed for each row or column scan, if the reflectance of one part of the paper is different from the reflectance of another part, if the light source has uneven irradiation, or if the paper is If the photoelectric conversion device is tilted with respect to the light-receiving surface, there is a risk that the analog electrical signal output from the photoelectric conversion element may not be converted into a binary signal that accurately corresponds to the character area and background area. Ta.

The present invention has been made to improve the above-mentioned drawbacks, and it is an object of the present invention to provide a binarization circuit that can obtain accurate binary signals even with background fluctuations. Examples will be described in detail below.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a light source 2 illuminates a paper 1 on which characters are written, a lens 3 condenses reflected light from the paper 1 and makes it enter a photoelectric conversion device 4. , sample and hold circuits 51 to 59 that sample and hold the output signal from the photoelectric conversion device 4, and sample and hold circuits 51 to 59
average level detection circuits 61 to 63 that binarize the output signal from 59; reference voltage generation circuits 71 to 73;
It is comprised of a binarization circuit 9 made up of comparison circuits 81 to 83, and an identification circuit 10 that identifies characters based on the output signal from the binarization circuit 9.

The photoelectric conversion device 4 has a self-scanning circuit, and the light receiving surface has, for example, a 9×12 bit two-dimensional array of photoelectric conversion elements as shown in FIG. Nine video signals I ₁ to I ₉ are output 12 times in accordance with the clock signal given. For example, when a clock signal K shown in FIG. 3 (CK) is applied to the photoelectric conversion device 4, at the time when the first clock is applied, a video signal I ₁ is output from the photoelectric conversion elements arranged in _one row. ~I prints ₉ ,
At the point when the second clock is added,
Video signals I ₁ to I ₉ are output from the photoelectric conversion elements arranged in _two rows. 3rd, 4th,...
…When the 12th clock is applied, ₃
Video signals I ₁ to I ₉ are output from the photoelectric conversion elements arranged in rows, ₄ rows, . . . ₉ rows. Therefore, scanning of one screen is completed while the 1st to 12th clocks are being applied. Furthermore, 13th and 14th
The period during which the th clock is applied is a flyback period, and the level of the video signals I ₁ to I ₉ output from the photoelectric conversion device 4 during this period is normally higher than the level of the signal corresponding to the background area. . Further, the photoelectric conversion device 4 outputs a synchronizing signal SYN at the time when the 14th pulse is applied.

In this way, for example, when the number "2" is imaged on the light receiving surface of the photoelectric conversion device 4, which outputs the video signals I ₁ to I ₉ and the synchronization signal SYN according to the clock signal CK, as shown in FIG. The video signals I _{1 to I 9 outputted} from the photoelectric conversion device 4 correspond to the amount of incident light as shown in FIG. Become.

Video signals _I1 - _I9 output in accordance with clock signal CK are applied to sample-and-hold circuits 51-59. The sample and hold circuits 51 to 59 are
Video signals I ₁ to I ₉ output from the photoelectric conversion device 4
is sampled and held at times t ₁ to _{t 14} shown in FIG. 3, outputs signals J ₁ to J ₉ at each time t ₁ to t ₁₄ of video signals I ₁ to _{I 9} , and binarizes them. It is added to average level detection circuits 61 to 63 and comparison circuits 81 to 83 that constitute circuit 9. In this case, the average level detection circuit 61 and the comparison circuit 81 receive the signals J ₁ to J ₃ , and the average level detection circuit 62 and the comparison circuit 82 receive the signal J _{4 .}
~ _J6 is the average level detection circuit 63 and the comparison circuit 83
The signals J ₇ to J 9 are applied to the signals J 7 to J ₉ .

The average level detection circuit 61 outputs a signal _K1 corresponding to the average level of the signals _J1 to _J3 and adds it to the reference voltage generation circuit 71, and the average level detection circuit 62 outputs the signal K1 corresponding to the average level of the signals J1 to J3.
A signal K ₂ corresponding to the average level of signals J ₄ to J ₆ is outputted and added to the reference voltage generation circuit 72, and an average level detection circuit 63 outputs a signal K 2 corresponding to the average level of signals J ₇ to J ₉ .
K ₃ is output and applied to the reference voltage generation circuit 75.
The reference voltage generation circuit 71 sets the level of the signal L ₁ used as a threshold value based on the signal K ₁ and applies it to the comparison circuit 81 . Also, reference voltage generation circuits 72, 73
Similarly, the levels of the signals L ₂ and L ₃ used as thresholds are set based on the signals K ₂ and K ₃ , and the comparator circuit 8
Add to 2,83.

Comparison circuit 81 includes sample and hold circuits 51 to
The signals J ₁ to _{J 3} applied from the reference voltage generation circuit 71 are compared with the signal L ₁ applied as a threshold value from the reference voltage generation circuit 71 to output binary signals M ₁ to _{M 3} , and the comparison circuit 82
compares the signals _J4 to _J6 applied from the sample and hold circuits 54 to 56 with the signal _L2 applied from the reference voltage generation circuit 72 and outputs binary signals _M4 to _M6 , and the comparison circuit 83 outputs binary signals M4 to M6. Hold circuit 57~
The signals J ₇ to J ₉ applied from the reference voltage generation circuit 73 are compared with the signal L ₃ applied from the reference voltage generation circuit 73, and binary signals M ₇ to _{M 9} are output. The identification circuit 10 receives binary signals M 1 - M ₁ - applied from comparison circuits 81 - 83.
Identifies characters based on _M9 and outputs character codes. Note that since the photoelectric conversion device 4 always outputs the video signals I ₁ to I ₉ in accordance with the clock signal CK, the identification circuit 10 identifies the characters based on the binary signals M ₁ to _{M 9} . It is determined whether the extraction is successful and the position of the character within the field of view of the photoelectric conversion device 4. Outputs the character code only when it is determined that the

As mentioned above, the signal J ₁ is obtained by sampling and holding the video signals I ₁ to I ₉ outputted from the photoelectric conversion device 4 in accordance with the clock signal CK at times t ₁ to t ₁₄ .
The binarization circuit 9 that binarizes ~J ₉ includes average level detection circuits 61 to 63, reference voltage generation circuits 71 to 73,
Comparing circuits 81 to 83 divide the signals J ₁ to J ₉ into three local regions, and generate a signal corresponding to the average level of each of the three divided regions.
_K1 to _K3 are determined by average level detection circuits 61 to 63, and based on these signals _K1 to _K3 , signals _L1 to _L3 are used as threshold values in reference voltage generation circuits 71 to 73.
and set the level of signal J ₁ in comparison circuits 81 to 83.
~ _J9 and signals _L1 - _L3 added as thresholds from reference voltage generation circuits 71-73 are compared for each region to output binary signals _M1 - _M9 . Therefore, the following drawbacks can be improved.

For example, due to uneven illuminance of the light source 2, the photoelectric conversion device 4
In the field of view, if the illuminance on the left side is higher than the illuminance on the right side, or if the left side of the paper 1 is closer to the light receiving surface of the photoelectric conversion device 4 than the right side, , even if the entire field of view is the background area, the levels of the video signals I ₁ and _{I 2} output from the photoelectric conversion elements arranged near the C ₁ and C ₂ columns are C as shown in Fig. 4. Video signal output from photoelectric conversion elements placed near columns ₈ and _C9
It will be higher than the level of I ₈ and I ₉ . In such a case, even if the threshold value is changed every time one row is scanned, if the same threshold value is used for the entire range scanned by one row, the data will be arranged near columns C ₈ and C ₉ . There is a risk that the video signals I ₈ and I ₉ from the photoelectric conversion elements included in the image will be converted into binary signals corresponding to the character area.

Conversely, even if the entire visual field of the photoelectric conversion device 4 is a character area, the video signals I ₁ and I ₂ from the photoelectric conversion elements arranged near the C ₁ and C ₂ columns correspond to the background area. There is a risk that the signal will be converted into a binary signal.

However, in the present invention, the signal J ₁ is obtained by sample-holding the video signals I ₁ to I ₉ at times t ₁ to _{t 14.}
~ _J9 is divided into three parts, a threshold value is determined for each divided area, and binarization is performed for each area.
As shown in the figure, the signal levels are approximately equal in each region, so the above-mentioned error is eliminated. Therefore, it is possible to obtain binary signals that accurately correspond to the character area and the background area.

FIG. 5 shows the specific circuit configuration of the average level detection circuit 61, the reference voltage generation circuit 71, and the synchronization signal removal circuit 11, which are omitted in the above description for convenience of explanation, which constitute the binarization circuit 9. This is a circuit diagram in which average level detection circuits 62 and 63 and reference voltage generation circuits 72 and 73 have the same configuration. The synchronization signal removal circuit 11 is also connected to these.

The average level detection circuit 61 is composed of an operational amplifier _OP1 and resistors _R1 to _R5 , and the reference voltage generation circuit 71 is composed of an operational amplifier _OP2 , a diode _D1 , a capacitor _C1 , and resistors _R6 to _R9 . The synchronizing signal removal circuit 11 includes a transistor Tr ₁ and a resistor R ₁₀ .
Consists of R ₁₂ .

The average level detection circuit 61 outputs a signal K ₁ corresponding to the average level of the signals J ₁ to _{J 3} applied from the sample and hold circuits 51 to 53, and applies it to the reference voltage generation circuit 71. The reference voltage generation circuit 71 charges the capacitor C _{1 with a charge corresponding to the potential of the signal K 1 with} a rise time constant Tr = R ₆ · C ₁ expressed as the product of the resistor R ₆ and the capacitor _{C 1 ,} and When the voltage becomes lower than the voltage across capacitor _C1 , the charge stored in capacitor _C1 is transferred to the resistor.
Falling time constant T determined by the product of R ₇ and capacitor C ₁
= _R7・_C1 , the voltage across _{the capacitor C1 is} amplified by an appropriate amplification factor using an operational amplifier _OP2 , and a signal _L1 is output, which is used as a threshold value. be. In this case, the rise time constant Tr
is set so that the charge charged in the capacitor _C1 faithfully follows the fluctuation of the signal _K1 , and the falling time constant T is the time required to scan the part where the character line width is maximum. Set it to the time.

By setting the rise time constant Tr and fall time constant T in this way, the average level setting circuit 61
When the signals J ₁ to J ₃ shown in FIG. 6 A to C added to the area are all at the level corresponding to the character area in the period T ₁ , the signal K ₁ outputted from the average level detection circuit 61 is as follows. As shown in period _T1 in FIG. 6D, the capacitor of the reference voltage generation circuit 71
Since the charge stored in _C1 is gradually discharged according to the falling time constant T, the output signal _L1 of the reference voltage generating circuit 71 becomes as shown by the dotted lines in FIGS. 6A to 6D. Therefore, even if the signals J ₁ to _{J 3} output from regions obtained by dividing one line scan into a plurality of regions are all signals at a level corresponding to a character region, they can be accurately binarized.

However, since the falling time constant T is set so that the charge stored in the capacitor _C1 is gradually discharged, the potential of the video signals _I1 to _I9 output from the photoelectric conversion device 4 during the flyback period The voltage across capacitor _C1 , which is charged with a charge corresponding to , will not drop immediately. That is, since the influence of the video signal output during the flyback period will extend to the next frame, the synchronization signal removal circuit 11 constituted by the transistor Tr ₁ and the resistors R ₁₀ to R ₁₂ is connected to the reference voltage generation circuit 71 to prevent the video signal output during the flyback period from affecting the next frame.

For example, assuming that the signals J ₁ to _{J 3} applied to the average level detection circuit 61 are shown in FIGS. 7A to C,
The output signal _K1 from the average level detection circuit 61 is as shown in Figure D, and the level of the signal output during the flyback period _T1 is higher than the level of the signal output during other periods. Become. As described above, since the charge stored in the capacitor _C1 is gradually discharged, the influence of the signal output during the flyback period _T1 will extend to the next frame. During this flyback period _T1 , from the photoelectric conversion device 4,
The synchronization signal SYN shown in is output. This synchronization signal SYN is applied to the base of the transistor Tr ₁ of the synchronization signal removal circuit 11 so that the transistor Tr ₁ is turned on when the synchronization signal SYN is at a high level. This way, capacitor C ₁
When the transistor Tr 1 is turned on, the charges stored in the transistor Tr ₁ are discharged through the resistor R ₁₀ and the transistor Tr ₁ . Therefore, the output signal _L1 from the reference level generating circuit 71 becomes as shown in FIG. 7F, so that the influence of the signal output during the flyback period does not extend to the next frame. In addition, since the charge stored in the capacitor C ₁ is discharged every frame, video signals I ₁ to I caused by gradual fluctuations in the light intensity of the light source, fluctuations in the reflectance of the paper, etc. ₉ fluctuations can be absorbed.

As explained above, the present invention provides a signal for one line scanning or one line of the signal output from the photoelectric conversion device.
An average level detection circuit that divides column scanning into a plurality of local areas and detects the average level for each area, and sets the level of a signal used as a threshold based on the average level determined by the average level detection circuit. Since it is equipped with a reference voltage generation circuit and a comparison circuit that compares the level of the signal output as a threshold value from the reference voltage generation circuit and the signal output from the photoelectric conversion device for each region, local paper Even if there is a fluctuation in the level of the video signal output from the photoelectric conversion device caused by changes in reflectance, local irradiation unevenness, or an inclination between the paper surface and the light-receiving surface of the photoelectric conversion device, characters A binarized signal that accurately corresponds to the region or background region can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a book diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of a photoelectric conversion device, FIGS. 3 and 4 are explanatory diagrams of signals output from the photoelectric conversion device, and FIG. 5 is an explanatory diagram of the present invention. 6 and 7 are detailed circuit diagrams of the embodiment, and are explanatory diagrams of its operation. 1 is paper, 2 is a light source, 3 is a lens, 4 is a photoelectric conversion device, 51 to 59 are sample and hold circuits, 6
1 to 63 are average level detection circuits, 71 to 73 are reference voltage generation circuits, 81 to 83 are comparison circuits, and 9 is 2.
10 is an identification circuit, 11 is a synchronization signal removal circuit, R ₁ to R ₁₂ are resistors, OP ₁ and OP ₂ are operational amplifiers, D ₁ is a diode, C ₁ is a capacitor, and Tr ₁ is a transistor.

Claims (1)

[Claims] 1. In a binarization circuit that converts an output signal from a photoelectric conversion device in which photoelectric conversion elements are arranged two-dimensionally into a binary signal, one line scanning of the signal output from the photoelectric conversion device is performed. An average level detection circuit that divides one line of scanning into a plurality of local areas and calculates the average level for each area, and the level of a signal used as a threshold based on the output signal from the average level detection circuit. A reference voltage generation circuit that sets
The output signal from the reference voltage generation circuit and the output signal from the photoelectric conversion device are compared for each region.
A binarization circuit characterized by comprising a comparison circuit that outputs a value signal.