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JPS6146068B2 - - Google Patents

Info

Publication number
JPS6146068B2
JPS6146068B2 JP9837079A JP9837079A JPS6146068B2 JP S6146068 B2 JPS6146068 B2 JP S6146068B2 JP 9837079 A JP9837079 A JP 9837079A JP 9837079 A JP9837079 A JP 9837079A JP S6146068 B2 JPS6146068 B2 JP S6146068B2
Authority
JP
Japan
Prior art keywords
source
semiconductor layer
electrode
gate electrode
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9837079A
Other languages
Japanese (ja)
Other versions
JPS5623780A (en
Inventor
Yutaka Takato
Hirosaku Nonomura
Sadatoshi Takechi
Hisashi Kamiide
Tomio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP9837079A priority Critical patent/JPS5623780A/en
Priority to DE3028718A priority patent/DE3028718C2/en
Priority to US06/173,818 priority patent/US4404578A/en
Priority to GB8025044A priority patent/GB2056770B/en
Publication of JPS5623780A publication Critical patent/JPS5623780A/en
Priority to GB08316196A priority patent/GB2126779B/en
Priority to GB08316195A priority patent/GB2127216B/en
Publication of JPS6146068B2 publication Critical patent/JPS6146068B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Non-Volatile Memory (AREA)

Description

【発明の詳細な説明】 本発明は薄膜トランジスタ（以下TFTと略
す）の電極構造に関するもので、特には、製造工
程上の制約あるいは製造工程の簡略化等のため
に、ソースあるいはドレイン電極がゲート電極と
重なつた構造をとれない場合、あるいはゲート電
極上の絶縁層が絶縁層形成後の工程で損傷を受け
る事を出来る限り避けるために、ソースあるいは
ドレイン電極と、ゲート電極とが重ならない構造
をとる場合等に、ゲート電極によつて制御される
半導体チヤンネル部の電気抵抗（動作時の電気抵
抗）に比べて、制御され得ない半導体層の部分の
電気抵抗を十分に小とし、TFTの動作特性を向
上せしめる方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode structure of a thin film transistor (hereinafter abbreviated as TFT), and in particular, due to manufacturing process constraints or simplification of the manufacturing process, the source or drain electrode is connected to the gate electrode. If it is not possible to create a structure in which the source or drain electrode overlaps with the gate electrode, or in order to prevent the insulating layer on the gate electrode from being damaged in the process after forming the insulating layer, create a structure in which the source or drain electrode and the gate electrode do not overlap. When the TFT operates, the electrical resistance of the semiconductor layer portion that cannot be controlled is made sufficiently smaller than the electrical resistance of the semiconductor channel portion (the electrical resistance during operation) that is controlled by the gate electrode. The invention relates to a method for improving properties.

まずTFTについて第１図で説明する。TFT
は、ガラス等の絶縁基板１の上に制御ゲート電極
２を形成し、これを絶縁層３で被覆し、その上に
半導層４、ソース電極５及びドレイン電極６を順
次形成した構造をしている。ゲート電極２の材料
としては、Al、Au、Ta、In等の金属が用いら
れ、マスク蒸着、フオトエツチング等の技術を用
いて形成する。絶縁膜３の材料としては、
Al2O3SiO、SiO2、CaF2、Si3N4等が用いられ、真
空蒸着、スパツタリング、CVD等の方法で形成
される。あるいはゲート電極２がAl、Ta等の場
合には、これらの金属を陽極酸化せしめる事によ
り、絶縁層を形成する事も可能である。半導体層
４としては、一般にCdSe、CdS、Te等が用いら
れ、真空蒸着、スパツタリング等の方法で積層さ
れる。ソース電極５、ドレイン電極６としては、
半導体層４とオーム性接触をする材料が使われる
が、一般には、Au、Al等の金属が用いられる。
TFTの構造は第１図に示したものに限られるも
のではなく、第２図に示すように半導体層４とソ
ース電極５及びドレイン電極６との位置を上下逆
転したものや、第３に示すように、絶縁基板１の
上に、ソース電極５、ドレイン電極６、及び両電
極間に半導体層４を形成し、さらにその上に絶縁
層３、ゲート電極２を形成したもの、あるいは、
第４図に示すように、半導体層４にソース電極５
及びドレイン電極６を一部重ね、これらの上に絶
縁層３、及びゲート電極２を形成してもよい。 First, TFT will be explained with reference to FIG. TFT
has a structure in which a control gate electrode 2 is formed on an insulating substrate 1 such as glass, this is covered with an insulating layer 3, and a semiconductor layer 4, a source electrode 5, and a drain electrode 6 are sequentially formed thereon. ing. The gate electrode 2 is made of metal such as Al, Au, Ta, In, etc., and is formed using techniques such as mask evaporation and photo-etching. As the material of the insulating film 3,
Al 2 O 3 SiO, SiO 2 , CaF 2 , Si 3 N 4 or the like is used, and it is formed by a method such as vacuum evaporation, sputtering, or CVD. Alternatively, when the gate electrode 2 is made of Al, Ta, etc., it is also possible to form an insulating layer by anodizing these metals. The semiconductor layer 4 is generally made of CdSe, CdS, Te, or the like, and is laminated by a method such as vacuum evaporation or sputtering. As the source electrode 5 and the drain electrode 6,
A material that makes ohmic contact with the semiconductor layer 4 is used, and metals such as Au and Al are generally used.
The structure of the TFT is not limited to that shown in FIG. 1, but may be one in which the positions of the semiconductor layer 4, source electrode 5, and drain electrode 6 are upside down as shown in FIG. As shown in FIG.
As shown in FIG. 4, a source electrode 5 is provided on the semiconductor layer 4.
and the drain electrode 6 may be partially overlapped, and the insulating layer 3 and the gate electrode 2 may be formed thereon.

現存の薄膜製造技術では、Al、Ta等の金属を
用い、これを陽極酸化する事によるゲート電極及
び絶縁層を形成する方法、あるいは金属のゲート
電極上に、CVDあるいは真空蒸着やスパツタリ
ング等によりSiO、SiO2、Al2O3、Si3N4等の絶縁
膜を積層する方法が用いられるが、ゲートの絶縁
層に陽極酸化膜を用いる場合には、TFTの構造
は第１図あるいは第２図に示された構造でなけれ
ばならない。また、CVDや真空蒸着あるいはス
パツタリング等により絶縁層を形成し、半導体層
として、CdSe、CdS、Te等を用いてTFTを製造
する場合、第３図、及び第４図の構造では半導体
層形成後のマスク、エツチング等の工程や熱サイ
クルの工程等により半導体層が損傷を受けたり、
化合物半導体においては化学的組成が変化する等
のため、TFTの特性が悪化したり、再現性が悪
くなる。このため、第１図あるいは第２図に示さ
れたようにゲート電極が絶縁基板上に密着した構
造が優れている。しかしながら、第１図あるいは
第２図に示された構造においては、ゲート電極と
ソース及びドレイン電極とに重なりがあるため、
ゲート電極及び絶縁層形成後にソース及びドレイ
ン電極、半導体層を積層しなければならないが、
第１図あるいは第２図に示された構造を、第５図
に示すように、ゲート電極とソース及びドレイン
電極とが重ならない構造に変えた場合には、ソー
ス及びドレイン電極形成後に、損傷を受け易いゲ
ート電極、ゲート絶縁層と半導体層を形成する事
が出来る。第５図に示された構造においては、第
１図あるいは第２図に示された構造に比べて、 (i) 絶縁層が、絶縁層形成後の工程で損傷を受け
る可能性が少なくなる。 Existing thin film manufacturing technology uses metals such as Al and Ta and forms gate electrodes and insulating layers by anodizing them, or deposits SiO on metal gate electrodes by CVD, vacuum evaporation, sputtering, etc. , SiO 2 , Al 2 O 3 , Si 3 N 4 and other insulating films are used, but when an anodic oxide film is used for the gate insulating layer, the TFT structure is similar to that shown in Figure 1 or 2. The structure must be as shown in the diagram. In addition, when manufacturing a TFT using CdSe, CdS, Te, etc. as a semiconductor layer with an insulating layer formed by CVD, vacuum evaporation, or sputtering, etc., the structures shown in Figures 3 and 4 are used after the semiconductor layer is formed. The semiconductor layer may be damaged due to masking, etching, thermal cycling, etc.
In compound semiconductors, the chemical composition changes, resulting in deterioration of TFT characteristics and poor reproducibility. For this reason, a structure in which the gate electrode is in close contact with the insulating substrate as shown in FIG. 1 or 2 is superior. However, in the structure shown in FIG. 1 or 2, since the gate electrode overlaps the source and drain electrodes,
After forming the gate electrode and insulating layer, source and drain electrodes and semiconductor layers must be laminated.
If the structure shown in FIG. 1 or 2 is changed to a structure in which the gate electrode and the source and drain electrodes do not overlap, as shown in FIG. It is possible to form a gate electrode, a gate insulating layer, and a semiconductor layer that are easy to accept. In the structure shown in FIG. 5, compared to the structure shown in FIG. 1 or 2, (i) the insulating layer is less likely to be damaged in a step after forming the insulating layer;

(ii) ソース及びドレイン電極の付着強度を増すた
めに熱をかけたり、あるいは下地にIn2O3等を
付着せしめたりする事により絶縁層が損傷を受
ける事がない。(ii) The insulating layer will not be damaged by applying heat to increase the adhesion strength of the source and drain electrodes or by attaching In 2 O 3 or the like to the base.

(iii) TFTをマトリツクス型液晶表示装置の駆動
のためのスイツチング素子として用いる場合、
表示電極等に用いるIn2O3の蒸着膜等の透明導
電膜を、半導体層あるいは絶縁層に損傷を与え
る事なく、そのままソース及びドレイン電極に
利用出来、製造工程の簡略化、あるいは見ばえ
の改善が可能である。(iii) When using TFT as a switching element for driving a matrix type liquid crystal display device,
Transparent conductive films such as vapor-deposited In 2 O 3 films used for display electrodes etc. can be used as source and drain electrodes without damaging the semiconductor layer or insulating layer, simplifying the manufacturing process and improving the appearance. improvement is possible.

等の利点がある。さらに、第５図あるいは第６図
に示すようにゲート電極と、ソース及びドレイン
電極とが重ならない構造においては、ゲート電極
とソース及びドレイン電極とが重なつた構造に比
べ、ゲートとソース間あるいはゲート−ドレイン
間の浮遊容量を小さく出来、また重なり部分で生
じ易い絶縁破壊を押える事にも効果がある。There are advantages such as Furthermore, in a structure in which the gate electrode does not overlap with the source and drain electrodes as shown in FIG. 5 or 6, compared to a structure in which the gate electrode and the source and drain electrodes overlap, It is effective in reducing the stray capacitance between the gate and drain, and in suppressing dielectric breakdown that tends to occur in the overlapped portion.

しかしながら、このようにゲート電極とソース
及びドレイン電極とが重ならない構造のTFTの
場合、第５図、第６図に７で示されたゲート電極
２とソース及びドレイン電極５，６との間隙部
の、ゲート電極２によつて制御し得ない半導体部
分が、直列の寄生抵抗としてTFTに入つてく
る。この寄生抵抗は、たとえば上記TFTをマト
リツクス型液晶表示装置の駆動のためのスイツチ
ング素子として使用する場合、オン抵抗を高く
し、駆動のために必要なオン／オフ比がとれなく
なる。これを避けるためには、ゲート電極と、ソ
ース及びドレイン電極との間隙部７を小さくすれ
ばよいが、リングラフイでのパターン合わせの限
度、オーバーエツチング等のためいくらでも間隙
を小さく出来るわけではない。 However, in the case of a TFT having such a structure in which the gate electrode and the source and drain electrodes do not overlap, the gap between the gate electrode 2 and the source and drain electrodes 5 and 6, which is indicated by 7 in FIGS. The semiconductor portion that cannot be controlled by the gate electrode 2 enters the TFT as a series parasitic resistance. For example, when the above TFT is used as a switching element for driving a matrix type liquid crystal display device, this parasitic resistance increases the on-resistance, making it impossible to maintain the on/off ratio necessary for driving. In order to avoid this, the gap 7 between the gate electrode and the source and drain electrodes can be made smaller, but it is not possible to make the gap as small as possible due to limitations in pattern alignment in ring graphing, overetching, and the like.

そこで、この避けられない間隙に比べて、ゲー
ト電極の幅Ｌを十分広くすれば、直列の寄生抵抗
の影響は十分に小さくおさえる事が出来る。しか
し、この場合、ゲート電極の幅Ｌが余り広くとれ
ば、伝達コンダクタンスが小さくなりTFTの特
性が悪化する。 Therefore, if the width L of the gate electrode is made sufficiently wide compared to this unavoidable gap, the influence of the series parasitic resistance can be suppressed to a sufficiently small value. However, in this case, if the width L of the gate electrode is too large, the transfer conductance becomes small and the characteristics of the TFT deteriorate.

この発明は、上述の点に鑑みてなされたもので
あり、その特性を良好なものに保ちながら、上記
寄生抵抗の影響を十分に小さくおさえることので
きるTFTの構造を提供するものである。更に述
べるならば、本発明は、ゲート線電極と、ソース
及びドレイン電極と、上記ゲート線電極上に形成
される絶縁膜と、該絶縁膜上に形成され且つその
両端がそれぞれ上記ソース及びドレイン電極と接
触する半導体層とを有する、絶縁基板上に形成さ
れた薄膜トランジスタであつて、上記ゲート線電
極と、上記ソースまたはドレイン電極とが重なら
ない構造の薄膜トランジスタに於て、上記ゲート
線電極と、上記ソースまたはドレイン電極間の間
隙部に生じる半導体層部分の抵抗を、上記ゲート
線電極によつて制御されるチヤンネル部の半導体
層部分の抵抗に比較して充分小とするために、上
記半導体層の幅、厚さ、不純物濃度の内の少なく
とも１つを、上記チヤンネル部の半導体層部分と
上記間隙部及びその近傍の半導体層部分間で異な
らせる構成としたことを特徴とする薄膜トランジ
スタの構造を提供するものである。 The present invention has been made in view of the above points, and provides a TFT structure that can sufficiently suppress the influence of the parasitic resistance while maintaining good characteristics. More specifically, the present invention provides a gate line electrode, a source and drain electrode, an insulating film formed on the gate line electrode, and an insulating film formed on the insulating film, both ends of which are connected to the source and drain electrodes, respectively. In a thin film transistor formed on an insulating substrate and having a semiconductor layer in contact with the gate line electrode, the thin film transistor has a structure in which the gate line electrode and the source or drain electrode do not overlap. In order to make the resistance of the semiconductor layer portion generated in the gap between the source or drain electrodes sufficiently smaller than the resistance of the semiconductor layer portion of the channel portion controlled by the gate line electrode, Provided is a structure of a thin film transistor, characterized in that at least one of width, thickness, and impurity concentration is different between the semiconductor layer portion of the channel portion and the semiconductor layer portion of the gap portion and its vicinity. It is something to do.

以下実施例を説明する。 Examples will be described below.

第１の実施例は、ゲート電極の幅Ｌを広くして
制御し得る半導体チヤンネル部の長さを長くする
とともに、ゲート電極とソース及びドレイン電極
との間隙部７の幅ｌを狭くすることによつて、ゲ
ート電極の幅Ｌに対する間隙部ｌの比を十分に小
さくし（数分の１乃至数百分の１）、且つ、ゲー
ト電極とソース及びドレイン電極との間隙部７及
びその近傍と、前記ソースまたはドレイン電極上
に於ける半導体層の幅Ｗを、半導体チヤンネル部
の幅Ｗに対して十分大きくしたものである。 In the first embodiment, the width L of the gate electrode is widened to increase the length of the controllable semiconductor channel part, and the width l of the gap 7 between the gate electrode and the source and drain electrodes is narrowed. Therefore, the ratio of the gap l to the width L of the gate electrode is made sufficiently small (a few fractions to a few hundredths), and the gap 7 between the gate electrode and the source and drain electrodes and the vicinity thereof are , the width W of the semiconductor layer on the source or drain electrode is made sufficiently larger than the width W of the semiconductor channel portion.

従来の間隙部を有するTFTの構造を第７図
に、そして、上記本発明の実施例の構造を第８図
に示す。 FIG. 7 shows the structure of a conventional TFT having a gap, and FIG. 8 shows the structure of the embodiment of the present invention.

第８図に示すような構造とすることにより特性
の良いTFTを得ることができた。 By using the structure shown in FIG. 8, a TFT with good characteristics could be obtained.

更に、上記実施例のように、半導体チヤンネル
部の幅に対し、半導体層が上記ソースまたはドレ
イン電極と接触する部分及びその近傍に於ける上
記半導体層の幅を広くし、上記半導体層と上記ソ
ース及びドレイン電極との接触面積を、半導体の
チヤンネル部の面積に比べて広くする事により、
接触不良による特性のバラツキが減少する。さら
にまた、多少の障害が出来る材料をソース及びド
レイン電極に用いても、障壁の影響を無視し得る
程度に軽減する事が出来、ソース及びドレイン電
極と、半導体材料の選択の自由度が増す。 Further, as in the above embodiment, the width of the semiconductor layer in the portion where the semiconductor layer contacts the source or drain electrode and the vicinity thereof is made wider than the width of the semiconductor channel portion, so that the width of the semiconductor layer and the source are increased. By making the contact area with the drain electrode larger than the area of the semiconductor channel,
Variations in characteristics due to poor contact are reduced. Furthermore, even if a material that causes some degree of hindrance is used for the source and drain electrodes, the influence of the barrier can be reduced to a negligible extent, increasing the degree of freedom in selecting the source and drain electrodes and the semiconductor material.

第９図に、第８図で示された構造で、ゲート電
極にAl、ゲート絶縁層に陽極酸化によるAl2O3、
ソース及びドレイン電極にNi、半導体にTeを用
い、ガラス基板上に形成したTFTのＶSD−ＩD特
性を、第１０図に同一の材料を用い、第７図で示
した従来の構造を持つTFTのＶSD−ＩD特性を示
す。尚、第７図及び第８図に於ける各部の寸法は
以下のとおりである。即ち、第７図に於ては、Ｌ
＝800μ、ｌ＝100μ、Ｗ＝50μであり、第８図に
於いては、Ｌ＝800μ、ｌ＝100μ、Ｗ＝50μ、Ｗ
＝500μである。また、第８図に示す実施例に於
ては、Ｌの値は数10μの範囲内に、Ｗの値は数μ
乃至数100μの範囲内に設定することがのぞまし
い。尚、Ｗの値は、可能な範囲で大きければ大き
い程よいことは言うまでもない。 FIG. 9 shows the structure shown in FIG. 8, with Al in the gate electrode, Al 2 O 3 by anodic oxidation in the gate insulating layer,
Figure 10 shows the V SD -I D characteristics of a TFT formed on a glass substrate using Ni for the source and drain electrodes and Te for the semiconductor, with the conventional structure shown in Figure 7 using the same materials. This shows the V SD -I D characteristics of TFT. The dimensions of each part in FIGS. 7 and 8 are as follows. That is, in FIG. 7, L
= 800μ, l = 100μ, W = 50μ, and in Fig. 8, L = 800μ, l = 100μ, W = 50μ, W
=500μ. In addition, in the embodiment shown in FIG.
It is desirable to set it within the range of 100 μm to several 100 μm. It goes without saying that the larger the value of W is within the possible range, the better.

上記両図から明らかに、第９図の場合特性が改
善されている事がわかる。 It is clear from the above two figures that the characteristics are improved in the case of Fig. 9.

第１１図に、第８図において、ゲート電極に
Alゲート絶縁層に陽極酸化によるAl2O3、ソース
及びドレインにIn2O3、半導体としてTeを用い、
ｌ＝100μ、Ｗ＝１／２ｌ、Ｌ＝8lの時、Ｗ／Ｗを変え てTFTを作つた場合のオン抵抗（動作時の抵
抗）ＲONの値を示す。但し、オン抵抗ＲONは、Ｖ
SD＝−10v、ＶG＝−12vの時のＶSD／ＩDの値、
ｌはゲート電極と、ソース及びドレイン電極との
間隙、Ｗは半導体チヤンネル部の幅、Ｗは間隙部
及びその近傍における半導体層の幅、Ｌはゲート
電極の幅である。 In Fig. 11 and Fig. 8, the gate electrode
Using Al 2 O 3 by anodic oxidation for the Al gate insulating layer, In 2 O 3 for the source and drain, and Te as the semiconductor,
The value of the on-resistance (resistance during operation) R ON is shown when a TFT is made by changing W/W when l=100μ, W=1/2l, and L=8l. However, the on-resistance R ON is V
The value of V SD /I D when SD = -10v, V G = -12v,
l is the gap between the gate electrode and the source and drain electrodes, W is the width of the semiconductor channel portion, W is the width of the semiconductor layer in the gap portion and its vicinity, and L is the width of the gate electrode.

上記実施例は、間隙部及びその近傍と、ソース
あるいはドレイン電極上における半導体層の幅
を、チヤンネル部の半導体層の幅と異ならせたも
のであるが、間隙部及びその近傍と、ソースある
いはドレイン電極上における半導体層の厚さ（ま
たは不純物濃度）を、チヤンネル部の半導体層の
厚さ（たは不純物濃度）と異ならせる構成として
もよい。更に述べるならば、幅、厚さ、不純物濃
度の内の任意の２つあるいはすべてを、上記両者
間で異ならせる構成としてもよい。 In the above embodiment, the width of the semiconductor layer in the gap and its vicinity and on the source or drain electrode is different from the width of the semiconductor layer in the channel part. The thickness (or impurity concentration) of the semiconductor layer on the electrode may be different from the thickness (or impurity concentration) of the semiconductor layer in the channel portion. More specifically, any two or all of the width, thickness, and impurity concentration may be different between the two.

第８図において、細い半導体チヤンネル部に
Teを真空蒸着し、８，９で示された部分には、
チヤンネル部の10倍の厚さにTeを真空蒸着した
場合にも第９図とほとんど同じ特性が得られた。 In Figure 8, in the thin semiconductor channel section
Te is vacuum-deposited, and the parts indicated by 8 and 9 are
Almost the same characteristics as in Fig. 9 were obtained when Te was vacuum-deposited to a thickness 10 times that of the channel part.

また、第８図において、８，９で示された部分
に、スパツタリングによりDdSeに微量のInを混
ぜて付着させ、続いて半導体チヤンネル部に
CdSeを付着させ、In2O3をソース及びドレインと
して蒸着した場合にも非常に良い結果が得られ
た。 In addition, in Fig. 8, a small amount of In was mixed with DdSe and deposited on the parts indicated by 8 and 9 by sputtering, and then the semiconductor channel part was coated with a small amount of In.
Very good results were also obtained when CdSe was deposited and In 2 O 3 was deposited as the source and drain.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図乃至第４図は従来のTFTの構造を示す
断面図、第５図は、最初にソース及びドレイン電
極を形成し、次にゲート電極及びゲート絶縁層を
形成し、最後に半導体層を積層する場合のTFT
の構造を示す断面図、第６図は、ゲート電極及び
ゲート絶縁層をまず形成し、次に半導体層を積層
し、最後にゲート電極と重ならないようにソース
及びドレイン電極を形成する場合のTFTの構造
を示す断面図、第７図は、ゲート電極と、ソース
及びドレイン電極とが重ならない場合の従来の
TFTの構造を示す平面図、第８図は本発明の一
実施例のTFTの平面図、第９図は、第８図に示
された構造を持つTFTのＶSD−ＩD特性を示す
図、第１０図は、第７図に示された構造を持つ
TFTのＶSD−ＩD特性を示す図、第１１図は、第
８図に示された構造でTFTを作りＷ／Ｗの値を
変化させた時のオン抵抗ＲONの変化を示す図であ
る。 符号、１：絶縁基板、２：ゲート電極、３：絶
縁膜、４：半導体層、５：ソース電極、６：ドレ
イン電極、７：間隙部、Ｌ：ゲート電極の幅、
ｌ：間隙部の幅、Ｗ：間隙部及びその近傍と、ソ
ース（またはドレイン）電極上における半導体層
の幅、Ｗ：半導体チヤンネル部の幅。 Figures 1 to 4 are cross-sectional views showing the structure of a conventional TFT, and Figure 5 shows that the source and drain electrodes are first formed, then the gate electrode and gate insulating layer are formed, and finally the semiconductor layer is formed. TFT for stacking
Figure 6 is a cross-sectional view showing the structure of a TFT in which a gate electrode and a gate insulating layer are first formed, then a semiconductor layer is laminated, and finally a source and drain electrode are formed so as not to overlap with the gate electrode. FIG. 7 is a cross-sectional view showing the structure of the conventional structure in which the gate electrode and the source and drain electrodes do not overlap.
FIG. 8 is a plan view showing the structure of a TFT, FIG. 8 is a plan view of a TFT according to an embodiment of the present invention, and FIG. 9 is a diagram showing the V SD -I D characteristics of the TFT having the structure shown in FIG. 8. , FIG. 10 has the structure shown in FIG.
Figure 11, a diagram showing the V SD -I D characteristics of a TFT, is a diagram showing the change in on-resistance R ON when a TFT is made with the structure shown in Figure 8 and the value of W/W is changed. be. Code, 1: insulating substrate, 2: gate electrode, 3: insulating film, 4: semiconductor layer, 5: source electrode, 6: drain electrode, 7: gap, L: width of gate electrode,
l: Width of the gap, W: Width of the semiconductor layer in the gap and its vicinity and on the source (or drain) electrode, W: Width of the semiconductor channel.

Claims (1)

【特許請求の範囲】 １ ゲート線電極と、ソース及びドレイン電極
と、上記ゲート線電極上に形成される絶縁膜と、
該絶縁膜上に形成され且つその両端がそれぞれ上
記ソース及びドレイン電極と接触する半導体層と
を有する。絶縁基板上に形成された薄膜トランジ
スタであつて、上記ゲート線電極と、上記ソース
またはドレイン電極とが重ならない構造の薄膜ト
ランジスタに於て、 上記ゲート線電極と、上記ソースまたはドレイ
ン電極間の間隙部に形成される半導体層部分の抵
抗が、上記ゲート線電極によつて制御されるチヤ
ンネル部の半導体層部分の抵抗に比較して充分小
となるように、上記半導体層の幅、厚さ、不純物
濃度の内の少なくとも１つを、上記チヤンネル部
の半導体層部分と上記間隙部に形成される半導体
層部分間で異ならせたことを特徴とする薄膜トラ
ンジスタの構造。[Claims] 1. A gate line electrode, a source and drain electrode, an insulating film formed on the gate line electrode,
A semiconductor layer is formed on the insulating film and has both ends thereof in contact with the source and drain electrodes, respectively. In a thin film transistor formed on an insulating substrate and having a structure in which the gate line electrode and the source or drain electrode do not overlap, a gap between the gate line electrode and the source or drain electrode is provided. The width, thickness, and impurity concentration of the semiconductor layer are adjusted so that the resistance of the semiconductor layer portion to be formed is sufficiently smaller than the resistance of the semiconductor layer portion of the channel portion controlled by the gate line electrode. A structure of a thin film transistor characterized in that at least one of the following is made different between the semiconductor layer portion of the channel portion and the semiconductor layer portion formed in the gap portion.
JP9837079A 1979-07-31 1979-07-31 Manufacture of thin film transistor Granted JPS5623780A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP9837079A JPS5623780A (en) 1979-07-31 1979-07-31 Manufacture of thin film transistor
DE3028718A DE3028718C2 (en) 1979-07-31 1980-07-29 Thin film transistor in connection with a display device
US06/173,818 US4404578A (en) 1979-07-31 1980-07-30 Structure of thin film transistors
GB8025044A GB2056770B (en) 1979-07-31 1980-07-31 Thin film transistors
GB08316196A GB2126779B (en) 1979-07-31 1983-06-14 Thin-film transistor
GB08316195A GB2127216B (en) 1979-07-31 1983-06-14 Improved s of thin film transistors and manufacture method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9837079A JPS5623780A (en) 1979-07-31 1979-07-31 Manufacture of thin film transistor

Publications (2)

Publication Number Publication Date
JPS5623780A JPS5623780A (en) 1981-03-06
JPS6146068B2 true JPS6146068B2 (en) 1986-10-11

Family

ID=14217985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9837079A Granted JPS5623780A (en) 1979-07-31 1979-07-31 Manufacture of thin film transistor

Country Status (1)

Country Link
JP (1) JPS5623780A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5867066A (en) * 1981-10-16 1983-04-21 Semiconductor Energy Lab Co Ltd Insulating gate type field-effect semiconductor device
JPS58134476A (en) * 1982-02-05 1983-08-10 Mitsubishi Electric Corp Thin film transistor
JPS58190063A (en) * 1982-04-30 1983-11-05 Seiko Epson Corp Thin film transistor for transmission type liquid crystal display panel
JPS61161764A (en) * 1985-01-11 1986-07-22 Nec Corp Manufacture of thin film transistor
JPH0537117Y2 (en) * 1985-12-12 1993-09-20
WO1986007432A1 (en) * 1985-06-11 1986-12-18 Institut Français Du Petrole Conduit usable particularly for transporting fluids and enabling to limit the permeability to transported fluids
JPS6298884U (en) * 1985-12-12 1987-06-24
JP2554931B2 (en) * 1989-06-07 1996-11-20 川崎製鉄株式会社 Laminated spiral tube
WO2019187070A1 (en) * 2018-03-30 2019-10-03 シャープ株式会社 Transistor and display device

Also Published As

Publication number Publication date
JPS5623780A (en) 1981-03-06

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