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JPS6141298Y2 - - Google Patents

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Publication number
JPS6141298Y2
JPS6141298Y2 JP170979U JP170979U JPS6141298Y2 JP S6141298 Y2 JPS6141298 Y2 JP S6141298Y2 JP 170979 U JP170979 U JP 170979U JP 170979 U JP170979 U JP 170979U JP S6141298 Y2 JPS6141298 Y2 JP S6141298Y2
Authority
JP
Japan
Prior art keywords
pin diode
transistor
circuit
emitter
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP170979U
Other languages
Japanese (ja)
Other versions
JPS55102220U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP170979U priority Critical patent/JPS6141298Y2/ja
Publication of JPS55102220U publication Critical patent/JPS55102220U/ja
Application granted granted Critical
Publication of JPS6141298Y2 publication Critical patent/JPS6141298Y2/ja
Expired legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Description

【考案の詳細な説明】 この考案はベース接地形トランジスタの高周波
増幅回路、特にPINダイオードをエミツタと接地
間に挿入し過大入力に対する減衰に利用した増幅
回路の改良に関する。
[Detailed description of the invention] This invention relates to an improvement of a high-frequency amplifier circuit using a grounded base transistor, particularly an amplifier circuit in which a PIN diode is inserted between the emitter and the ground to attenuate excessive input.

従来、リバースAGC方式のトランジスタ増幅
器は動作電流が少なくて電源回路を有利に構成で
きることから広く利用されている。しかしこの種
の増幅器では動作電流が小さいために過大な入力
信号に対し高周波歪を生じたり混変調特性の低下
を招く。このような欠陥は過大な入力信号に対し
歪の少ない減衰機能を与えるPINダイオードの使
用により解消され、例えば、第1図に示す通り、
ベース接地形トランジスタ1のエミツタ・アース
間にPINダイオード2を介挿して使用することが
提案された。同図PINダイオード2とエミツタ抵
抗3の接続点には高周波入力信号が供給され、ト
ランジスタ1のベースにはAGC信号が与えら
れ、コレクタに高周波出力信号が得られる。この
回路ではベースに与えられるAGC信号によつて
トランジスタ1のエミツタ電流IEはPINダイオ
ード2とベース抵抗3の直列回路を流れるので
PINダイオード2の入力信号に対する高周波抵抗
がその有効動作電流の範囲内で利用され過大入力
を減衰させる。
Conventionally, reverse AGC type transistor amplifiers have been widely used because their operating current is small and power supply circuits can be advantageously configured. However, since the operating current of this type of amplifier is small, high-frequency distortion occurs in response to excessive input signals, and cross-modulation characteristics deteriorate. These deficiencies can be overcome by the use of PIN diodes, which provide low-distortion attenuation of excessive input signals; for example, as shown in Figure 1,
It was proposed to use a PIN diode 2 inserted between the emitter and ground of the grounded base transistor 1. A high frequency input signal is supplied to the connection point between the PIN diode 2 and the emitter resistor 3 in the figure, an AGC signal is supplied to the base of the transistor 1, and a high frequency output signal is obtained at the collector. In this circuit, the emitter current I E of transistor 1 flows through the series circuit of PIN diode 2 and base resistor 3 due to the AGC signal applied to the base.
The high frequency resistance of the PIN diode 2 to the input signal is utilized within its effective operating current to attenuate excessive input.

しかし、PINダイオード2の有効動作電流範囲
は2mA程度以下であるのに対して一般のトラン
ジスタの入出力特性は2mAを越えるエミツタ電
流IEにおいて直線性が良くPINダイオード2の
有効動作電流範囲である2mA以下ではトランジ
スタの入出力特性の歪が大きくなる範囲であつて
トランジスタの動作電流の大きい直線性の良好な
範囲でのPINダイオードによる有効な減衰特性が
得られなかつた。
However, the effective operating current range of PIN diode 2 is about 2 mA or less, whereas the input/output characteristics of general transistors have good linearity at emitter currents exceeding 2 mA, which is within the effective operating current range of PIN diode 2. At 2 mA or less, effective attenuation characteristics by the PIN diode could not be obtained in the range where the distortion of the transistor's input/output characteristics becomes large and the transistor's operating current is large and the linearity is good.

従つて、本考案は上記に鑑み提案されたもので
あり、一般のRF増幅用トランジスタ、好ましく
はトランジスタ動作電流に関しフラツトな入出力
特性、特に低電流でも直線性の良いトランジスタ
を用いるリバースAGC方式のRF増幅回路を提供
する。すなわち、PINダイオードと抵抗の直列回
路に第2のエミツタ抵抗を並列接続してPINダイ
オードの動作電流をトランジスタの動作電流と異
なる状態で使用できるベース接地形トランジスタ
増幅回路を提供することにある。従つて、本考案
の増幅回路によればトランジスタの入出力特性の
直線領域での過大入力の減衰にも役立ち結果的に
混変調特性並びに高調波妨害特性で改良された。
Therefore, the present invention has been proposed in view of the above, and is based on a reverse AGC method using a general RF amplification transistor, preferably a transistor with flat input/output characteristics regarding the transistor operating current, and especially a transistor with good linearity even at low current. Provides RF amplification circuits. That is, the object of the present invention is to provide a grounded base transistor amplifier circuit in which a second emitter resistor is connected in parallel to a series circuit of a PIN diode and a resistor so that the operating current of the PIN diode can be used in a different state from the operating current of the transistor. Therefore, the amplifier circuit of the present invention helps to attenuate excessive input in the linear region of the input/output characteristics of the transistor, resulting in improved cross-modulation characteristics and harmonic interference characteristics.

以下、本考案に係る実施例について図面を参照
しつつ詳述する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第2図は本考案に係る実施例のベース接地形ト
ランジスタ増幅回路の主要部を示す。この回路に
おいて、第1図の従来回路に比べて第2エミツタ
抵抗10が挿入されるほかは実質的に同じであ
る。すなわち、トランジスタ11のエミツタと接
地間にはPINダイオード12と第1エミツタ抵抗
13の直列回路が挿入されPINダイオード12と
第1エミツタ抵抗13の接続点14に入力端子1
5から結合コンデンサ16を介して高周波信号が
入力され、コレクタに高周波出力信号が得られ
る。尚17はAGC信号入力端子である。また高
周波入出力回路は図示省略している。
FIG. 2 shows the main parts of a grounded base transistor amplifier circuit according to an embodiment of the present invention. This circuit is substantially the same as the conventional circuit shown in FIG. 1 except that a second emitter resistor 10 is inserted. That is, a series circuit of a PIN diode 12 and a first emitter resistor 13 is inserted between the emitter of the transistor 11 and the ground, and the input terminal 1 is connected to the connection point 14 between the PIN diode 12 and the first emitter resistor 13.
A high frequency signal is input from 5 through a coupling capacitor 16, and a high frequency output signal is obtained at the collector. Note that 17 is an AGC signal input terminal. Further, a high frequency input/output circuit is not shown.

この増幅回路は、特にTVチユーナで小型化の
為に入力回路を非同調とする場合にローチヤンネ
ル信号が強力であるとRF増幅段で高調波が生じ
てハイチヤンネル受信時に混信妨害を与える問題
に対して大巾な改善をすることができる。すなわ
ち、本案では第3図に示すトランジスタの入出力
特性に対して、直線性のよい2mA以上の動作範
囲においてもPINダイオード12の減衰効果が有
効に得られることにある。第4図は1%高調波
(2倍)妨害特性について、第1図の従来回路と
第2図の本考案回路の特性曲線をそれぞれ点線a
と実線bで示した。この特性曲線は希望波信号D
に200MHz60dBμ基準に、妨害信号Uに100MHzを
用いD/U比を40dB(1%)として測定された
ものである。更に、第5図は1%混変調特性につ
いて、第1図と第2図の回路に対し第4図と同様
に点線aと実線bで示した。この場合の測定条件
は希望波信号に185MHz,60dBμ基準に妨害波信
号の195MHz、変調度30%で行なわれた。これら
の信号周波数は日本チヤンネルの第6及び第8チ
ヤンネルに対応するもので混変調特性に問題を生
じ易い信号である。第4図及び第5図から明らか
なように本考案の回路は特性曲線bで示す通り、
いずれの特性でも大巾な改善がなされる。
This amplification circuit has the problem that when the input circuit is detuned for miniaturization, especially in TV tuners, if the low channel signal is strong, harmonics are generated in the RF amplification stage, causing interference when receiving the high channel channel. It is possible to make significant improvements. That is, in the present invention, the attenuation effect of the PIN diode 12 can be effectively obtained even in the operating range of 2 mA or more with good linearity with respect to the input/output characteristics of the transistor shown in FIG. Figure 4 shows the characteristic curves of the conventional circuit in Figure 1 and the circuit of the present invention in Figure 2 with dotted lines a for the 1% harmonic (doubled) disturbance characteristics.
and is shown by a solid line b. This characteristic curve is the desired wave signal D
This was measured using a 200 MHz 60 dBμ standard, a 100 MHz interference signal U, and a D/U ratio of 40 dB (1%). Furthermore, FIG. 5 shows the 1% cross-modulation characteristics for the circuits of FIGS. 1 and 2 by dotted lines a and solid lines b, as in FIG. 4. The measurement conditions in this case were that the desired wave signal was 185 MHz, the interfering wave signal was 195 MHz with a 60 dBμ reference, and the modulation degree was 30%. These signal frequencies correspond to the 6th and 8th channels of the Japan channel, and are signals that are likely to cause problems in cross-modulation characteristics. As is clear from FIGS. 4 and 5, the circuit of the present invention has the following characteristics as shown by the characteristic curve b.
Significant improvements are made in both properties.

第2図の回路は入力非同調回路での利用におい
て特に有効であるが、入力同調回路でも使用でき
る。非同調回路の場合には入力インピーダンスと
の整合があるので必然的に各エミツタ抵抗の抵抗
値が制限される。例えば、テレビジヨンチユーナ
における入力インピーダンスが75Ωで定在波比
VSWRを3.0以下にする場合、入力信号のフルゲ
イン点でのPINダイオードの導通時の抵抗値10Ω
程度とベース接地形トランジスタの入力インピー
ダンス(R成分)10Ω程度とに対しエミツタ抵抗
13は無視し得る程度である10倍位の抵抗値に選
定する必要がある。この場合、VSWRは約3.7
(≒75/10+10)となる。一方、カツトオフ点の
PIN ダイオードは数kΩとなるため、第1エミツタ抵
抗13は入力インピーダンス75ΩとVSWR3.0を
考慮しその抵抗値を225(=75×3)附近に設定
するのが望ましい。更に、第2エミツタ抵抗10
はPINダイオードが動作を開始する電圧VFであ
る0.7V附近でのエミツタ電流IEを決定するよう
に選定する必要がある。すなわち、 の関係式を満足させるように設定する。ここで、
R10は第2エミツタ抵抗10の抵抗値、R13は第1
エミツタ抵抗13の抵抗値及びRDはPINダイオ
ード12の抵抗値である。
Although the circuit of FIG. 2 is particularly useful for use in input untuned circuits, it can also be used in input tuned circuits. In the case of a non-tuned circuit, since there is matching with the input impedance, the resistance value of each emitter resistor is necessarily limited. For example, when the input impedance of a television channel is 75Ω, the standing wave ratio is
If the VSWR is 3.0 or less, the resistance value when the PIN diode is conductive at the full gain point of the input signal is 10Ω.
It is necessary to select a resistance value of the emitter resistor 13 that is about 10 times larger than the input impedance (R component) of the grounded base transistor, which is about 10Ω, which is negligible. In this case, VSWR is approximately 3.7
(≒75/10+10). On the other hand, the cutoff point
Since the PIN diode is several kΩ, it is desirable to set the resistance value of the first emitter resistor 13 to around 225 (=75×3) considering the input impedance of 75Ω and VSWR of 3.0. Furthermore, a second emitter resistor 10
must be selected to determine the emitter current I E around 0.7V, which is the voltage V F at which the PIN diode starts operating. That is, Set so that the relational expression is satisfied. here,
R 10 is the resistance value of the second emitter resistor 10, and R 13 is the resistance value of the first emitter resistor 10.
The resistance value of the emitter resistor 13 and R D are the resistance values of the PIN diode 12.

本考案の回路によれば、カツトオフ点附近での
利得減衰度が大きくとれ、例えば、一般のフオワ
ードAGC用トランジスタ増幅回路で40dB程度の
減衰を得るのに対しPINダイオードと第2エミツ
タ抵抗を用いた本考案の回路では55dB程度もの
減衰を得られる。これは前述のように第1エミツ
タ抵抗13を約200Ωに設定すると共に第2エミ
ツタ抵抗10を数百Ωに設定して付加挿入すると
カツトオフ点近辺でのミスマツチングが大きくな
り、トランジスタに印加される電圧が小さくなつ
て利得減衰が大きくなることによる。
According to the circuit of the present invention, a large degree of gain attenuation near the cut-off point can be obtained.For example, whereas a general forward AGC transistor amplifier circuit obtains an attenuation of about 40 dB, it is possible to achieve a large gain attenuation near the cut-off point. The circuit of this invention can obtain attenuation of about 55 dB. This is because, as mentioned above, if the first emitter resistor 13 is set to about 200 Ω and the second emitter resistor 10 is set to several hundred Ω and is additionally inserted, mismatching near the cut-off point increases, and the voltage applied to the transistor increases. This is because the gain attenuation increases as the value decreases.

尚、本考案の実施回路ではPINダイオードに低
価格PINダイオードとして開発された横型構造の
ISV77タイプが使用され、増幅素子としては2SC
−2353タイプの電流による利得変化の少ない一般
増幅用トランジスタが使用された。特に、後者の
トランジスタの使用はAGC用トランジスタを使
用する場合に比べ非直線特性部分でのビート妨害
がなく顕著な効果を奏する。
In addition, in the implementation circuit of this invention, the PIN diode has a horizontal structure developed as a low-cost PIN diode.
ISV77 type is used, and 2SC is used as the amplification element.
-2353 type general amplification transistors with little change in gain due to current were used. In particular, the use of the latter transistor is more effective than the case of using an AGC transistor because there is no beat disturbance in the non-linear characteristic portion.

本考案に係る増幅回路はリバースAGC方式の
RF増幅回路を安価な能動素子の使用と回路上の
簡単な構成により、第4図及び第5図に示す様
に、高調波妨害特性及び混変調特性において著し
い改善を達成する。
The amplifier circuit according to the present invention uses a reverse AGC method.
As shown in FIGS. 4 and 5, significant improvements in harmonic interference characteristics and cross-modulation characteristics can be achieved by using inexpensive active elements and a simple circuit configuration in the RF amplifier circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の前提となる増幅回路図、第2
図は本考案の実施例である増幅回路図、第3図は
トランジスタ特性図、及び第4及び第5図はそれ
ぞれ第1及び第2図の回路による妨害波に対する
高調波歪、及び混変調特性図である。 10……第2エミツタ抵抗、11……トランジ
スタ、12……PINダイオード、13……第1エ
ミツタ抵抗、15……入力側信号端子、17……
AGC信号端子。
Figure 1 is an amplifier circuit diagram that is the premise of this invention, Figure 2
The figure shows an amplifier circuit diagram as an embodiment of the present invention, FIG. 3 shows a transistor characteristic diagram, and FIGS. 4 and 5 show harmonic distortion and cross-modulation characteristics for interference waves caused by the circuits of FIGS. 1 and 2, respectively. It is a diagram. 10... Second emitter resistor, 11... Transistor, 12... PIN diode, 13... First emitter resistor, 15... Input side signal terminal, 17...
AGC signal terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ベース接地形トランジスタのエミツタと接地間
にPINダイオードと第1エミツタ抵抗の直列回路
を設け、PINダイオードと第1エミツタ抵抗の接
続点に高周波入力信号を供給し、ベースにAGC
信号を与え、コレクタに高周波出力信号を得るよ
うにしたリバースAGC方式の高周波増幅回路に
おいて、上記直列回路に第2エミツタ抵抗を並列
接続して前記PINダイオードの有効動作範囲をエ
ミツタ電流の大きい方向に移行させるようにした
ことを特徴とするリバースAGC方式の高周波増
幅回路。
A series circuit of a PIN diode and a first emitter resistor is provided between the emitter of the base-grounded transistor and the ground, a high-frequency input signal is supplied to the connection point of the PIN diode and the first emitter resistor, and an AGC is connected to the base.
In a reverse AGC-type high-frequency amplifier circuit in which a signal is applied to the collector to obtain a high-frequency output signal, a second emitter resistor is connected in parallel to the series circuit to direct the effective operating range of the PIN diode in the direction of larger emitter current. A high-frequency amplification circuit using a reverse AGC method.
JP170979U 1979-01-10 1979-01-10 Expired JPS6141298Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP170979U JPS6141298Y2 (en) 1979-01-10 1979-01-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP170979U JPS6141298Y2 (en) 1979-01-10 1979-01-10

Publications (2)

Publication Number Publication Date
JPS55102220U JPS55102220U (en) 1980-07-16
JPS6141298Y2 true JPS6141298Y2 (en) 1986-11-25

Family

ID=28804099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP170979U Expired JPS6141298Y2 (en) 1979-01-10 1979-01-10

Country Status (1)

Country Link
JP (1) JPS6141298Y2 (en)

Also Published As

Publication number Publication date
JPS55102220U (en) 1980-07-16

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