JPS6137705B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called one-transistor type dynamic random access memory in which one bit consists of one transistor and one storage capacity.

Taking the MOS type as an example, a one-transistor type memory stores the presence or absence (strictly speaking, magnitude) of the charge accumulated in a MOS capacitor in correspondence with binary information 1.0. Capacitors arranged in a matrix and lined up on the same bit line are commonly connected via a switching MOS transistor, and the voltage change applied to the bit line as the selected capacitor discharges or charges is detected. In actual memory devices with a large number of integrated bits, this voltage change has an extremely small value mainly due to the parasitic capacitance component of the bit line, and a so-called sense amplifier is used to efficiently amplify this voltage change.

FIG. 1 shows a basic sense amplifier circuit, memory cells, etc. Q ₁ , Q ₂ , and Q ₅ are flip-flop and pull-down transistors that constitute the sense amplifier SA, and Q ₃ and Q ₄ are transistors for precharging the bit line BL. C _S is the capacitor of the memory cell MC, C _d is the capacitor of the dummy memory cell DMC, and C _d is usually designed to have a value close to half of C _S .

The read operation of this circuit is as follows. First, by the precharge signal φ _p , the transistor Q ₃ ,
When _Q4 is turned on, the bit line BL, is the power supply voltage V
Charged to _DD or similar high potential. At the same time, transistor _Q8 is also turned on, dummy memory cell DMC is discharged, and the semiconductor surface of MOS capacitor _Cd is filled with electrons. After completing precharging and turning off transistors Q ₃ , Q ₄ , and Q ₈ , transfer transistors Q ₆ and Q ₇ are turned on by drive signals φ _W for word lines WL and DWL, and the bit lines are turned off.
BL, precharged charge and memory cell
Charge redistribution occurs between the MC and the dummy memory cell DMC. For example, when the capacitor C _S of the memory cell MC is full of electrons, the electrons in the C _S flow to the bit line BL through the transistor Q ₆ and slightly lower its potential. On the other hand, in the dummy memory cell DMC, the capacitor _Cd emits electrons to the bit line, so the bit line potential drops slightly, but since _Cd is about half the size of _Cs , _Cs The potential on the side has dropped more.

Next, when a sensing operation is performed by the clock φ _S to turn on the transistor _Q5 , the conduction of the transistor _Q1 is accelerated and its drain potential further drops.
On the other hand, transistor Q ₂ is hardly conductive and its drain potential remains high. As a result, the potential difference between the bit lines BL and BL is amplified by the drop on one side. If the information in the memory cell MC is reversed and the capacitor C _S is in an electron-depleted state, then
Since the semiconductor surface potential of the MOS capacitor C _S is the same as that of the precharged bit line BL, no potential change occurs on the bit line BL. Meanwhile dummy memory cell
Since a slight potential drop occurs on the DMC side, the sense operation causes the bit line potential on the transistor _Q2 side to unilaterally drop in this case, amplifying the cell information.

In this way, the dummy memory cell DMC has half the storage capacity of the memory cell MC, so the bit line has two
It is possible to give an intermediate potential with value information of 0.1.
The advantage of designing C _d to be approximately 1/2 the capacitance of C _S is that the relative capacitance ratio can be determined with high accuracy simply by changing the area of the active region for element formation between the memory cell and the dummy memory cell. By doing this, the capacitance ratio does not change even if the concentration of the semiconductor substrate used or the dielectric film thickness of the storage part changes, and the storage charge ratio does not change even if the power supply voltage changes.
The stored information is stable against all changes, and when precharging the bit line to a high potential almost to the power supply voltage, it is sufficient to precharge the dummy memory cell to 0 volts, that is, the ground potential, making it simple and does not require a special power supply. , etc. are derived.
On the other hand, if a junction capacitor is used in the storage capacitance part of the dummy memory cell, or if a dielectric film different from that of the memory cell part is used, the dummy memory cell becomes sensitive to changes in substrate concentration, substrate bias voltage, etc., and a special compensation circuit is required. Otherwise, the operating margin will be narrow.

Figure 2 shows a specific circuit example of a dummy memory cell.The storage capacitor section is a MIS FET Q ₁₀ whose gate is connected to V _DD (power supply voltage), and whose source (or drain) electrode is connected to the bit line. The other electrode is connected to _a precharge control transistor _Q11 . By doing this the transistor
The possibility that the connection of Q ₁₁ will have an adverse effect on the dummy memory cell, that is, the electrical characteristics will differ from the memory cell portion, will be reduced. FIG. 3 shows an example of the cross-sectional structure, and shows a case of a two-layer polycrystalline silicon electrode structure. As shown in the figure, the first polycrystalline silicon layer 1 forms the gate electrode of the transistor _Q10 , that is, one electrode of the charge storage portion _Cd . The gates of the transfer transistor Q ₉ and the write control transistor Q ₁₁ are made of the second layer of polycrystalline silicon layers 2a and 2b, and are partially connected through an insulating film 3 formed by oxidation of the first layer of polycrystalline silicon layer 1. overlap. This eliminates the need for n ⁺ diffusion layers for the source and drain electrodes that connect each transistor, reducing the size of the cell. 4 is a p-type silicon semiconductor substrate, and 5 is a gate oxide film (dielectric film) obtained by oxidizing the substrate.

FIG. 4 shows an example of a planar pattern of the dummy memory DMC, and FIG. 3 corresponds to the YY' cross section in FIG. 4. A hatched area 6 in FIG. 4 is an active area for forming an element, and a part of it (the n ⁺ area on the left side of FIG. 3) is a bit line BL. Also, dummy word line DWL and precharge line
PL is an aluminum wiring layer, and 7 is a power supply line.

In the above structure, the overlap dimension a between the first layer and the second layer of polycrystalline silicon depends on the alignment accuracy of the mask, but usually needs to be 2 to 3 .mu.m. Further, the pattern gap dimension g between the second polycrystalline silicon layers 2a and 2b is usually about 2 to 3 .mu.m, although it depends on the processing accuracy. Taking Figure 4 as an example, when the dummy memory cell is made the most compact,
The width W of the storage part is the same as that of the transfer transistor part.
Wmin, the overlap a of the first and second polycrystalline silicon layers is a minimum value amin, and the gate-to-gate dimension g is a minimum value gmin. At this time, the size of the accumulation portion is (2 ^a +gmin)×Win. Therefore, since the memory cell is twice the size of the dummy cell, the area of the storage part can be reduced to approximately (2amin + gmin) × Wmin × 2, but in order to reduce the area to less than this, the dimensions of each part of the dummy memory cell DMC must be reduced. Must be below the minimum value (real cells require one less transistor, so they can be made smaller)
Therefore, it is impossible due to manufacturing technology. Although this situation does not normally occur,
This is likely to occur in designs where Wmin is close to Wmin and alignment margin amin is relatively large.

In the present invention, the dummy memory cell has almost the same area and the same storage capacity as the memory cell, and sensing is enabled by writing information into the dummy memory cell at a voltage that is between 0.1 and the voltage for writing information to the real cell, thus facilitating pattern design. The aim is to make it possible to realize highly integrated memory. In this memory, it is necessary to generate the above-mentioned intermediate voltage, and an object of the present invention is to provide an intermediate voltage generation circuit capable of widening the operating margin against power supply fluctuations by tracking the intermediate voltage with the write voltage of the memory cell, that is, the charging power supply voltage. This is also another object of the invention.

The concept of writing an intermediate voltage of 0.1 into dummy memory cells has been around for a long time. However, in reality, it is much easier and more accurate to control the area of the storage part than to incorporate an accurate voltage generation circuit inside the IC chip, and it is also easier to take margins for various parameters, so the area ratio is mainly taken. Even if this is not possible, make the storage portion C _d of the dummy memory cell 1/2 of C _S by constructing it using relatively thick dielectric films with different thicknesses or using junction capacitance. However, these methods have the drawback of unstable operation due to slight differences in dielectric film thickness, differences in substrate impurity concentration, etc.

The simplest circuit to generate a voltage of 1/2 of the charging voltage to a memory cell, or 1/n (including a slightly modified value in some cases), is the resistive voltage divider shown in Figure 5a. It is a method. V _p is a precharge voltage and is usually the power supply voltage V _DD . V _pd is the resistance of V _p
This is the precharge voltage to the dummy memory cell divided by R ₁ and R _2. In order to constantly reduce power consumption, the resistors R ₁ and R ₂ must be made large in this circuit. voltage V
_PD regulation is bad. Also, the resistances R ₁ and R ₂
The regulation can be improved by reducing , but
This is not preferable because steady power consumption increases. resistance
The same applies when R ₁ and R ₂ are MISFET channels and the R ₁ and R ₂ ratios are set by changing the gain constants of the FETs. b is from the precharge power supply V _p , MIS
This is an example of a circuit that supplies the voltage V _pd that is lowered by the threshold values V _T1 and V _T2 of the transistors Q ₁₂ and Q _13. Since the dummy memory cell becomes a capacitive load, there is no steady power consumption in this circuit, and Since the MIS transistor connected in this way exhibits square-law type voltage-current characteristics, its regulation is also superior to that of circuit a. However, the fluctuation of V _p remains as V _pd
Since it appears on the V p side, the rate is larger than that on the V _p side.
It is difficult to maintain a margin for power supply voltage fluctuations. c is the so-called series regulator circuit with a threshold value V _T
It is composed of MIS transistor _Q14 , and steady power consumption does not become a problem if _R3 and _R4 are set to large values.A voltage proportional to _Vp can be generated as _Vpd , and regulation is also good. However, when the circuit 10 shown in FIG. 5C is used as a charging power source for a dummy memory cell, a problem arises in operation, unlike when using a normal resistive load.

This will be explained with reference to FIG. The dummy memory cell DMC in the figure includes a precharge transistor Q ₂₁ , a storage capacitor C _d transistor Q ₂₂ , and a transfer transistor.
The memory cell MC is composed of a storage capacitor C _S and _{a transfer transistor Q 20 . Q17} ,
Q ₁₈ is a precharge transistor for the sense amplifier SA, Q ₁₅ and Q ₁₆ are flip-flop transistors, and Q ₁₉ is a pull-down transistor. It is assumed here that memory cell MC is in an electron-filled state, dummy memory cell DMC is precharged to an intermediate state, and bit line BL is precharged to V _p (usually V _p =V _DD ). When a word line is selected by decoder operation and word line WL and dummy word line DWL are driven by clock _φW , bit line BL, cell MC,
Charge redistribution occurs between DMCs. That is, on the dummy memory cell DMC side, the capacitor _Q22 is charged with the voltage charged to the parasitic capacitance of the bit line, which is much larger than its own capacitance, and goes from an intermediate state to a state where electrons are completely emitted, that is, in terms of voltage. In this case, the potential becomes a high potential approximately equal to V _p . Since the real cell side is full of electrons, the potential of the bit line BL is lowered somewhat significantly, so the sense amplifier SA conducts on the transistor _Q16 side due to the sensing operation, and lowers the potential of the bit line BL to the ground potential. Since _Q15 is off, the bit line on the dummy memory cell side remains at a high potential. This completes the sensing operation, but the problem lies in the following operation process.

In other words, when the clock _φW falls, the memory cell
MC is disconnected from the bit line BL, but the above operation of the sense amplifier fills the cell MC with electrons and refreshes it, but the dummy memory cell
The DMC side changes from an intermediate state to an electron-depleted state,
No refresh operation is performed to return it to an intermediate state again. Therefore, when the precharge circuit is driven by the signal φ _p in order to perform a read operation again next time, the power supply line V _pd is reversely charged from the dummy memory cell side, which was in an electron depleted state in the previous read, and its potential is The potential will rise above the intermediate potential. In this state, the regulator transistor _Q14 of the circuit 10 is cut off, so the increased potential has no choice but to decrease due to leakage from junctions, etc., and a specified precharge voltage cannot be obtained.

Therefore, in the present invention, the precharge power supply voltage of the dummy memory cell is lowered to a predetermined precharge voltage or less at the beginning of the precharge operation to discharge the dummy cell, and after the operation is completed, the cell can be charged to a predetermined intermediate potential through the series regulator circuit. Make it. An example is shown in FIG. 5A is a circuit diagram, and b is a clock pulse waveform and a voltage waveform of a precharge power supply. The embodiment circuit in a is the one in which transistors Q ₂₄ to _{Q 27} are added to the series voltage regulator circuit 10 in FIG. 5c. be. Transistors Q ₂₅ and Q ₂₆ are diode-connected, and a switching transistor Q ₂₇ is connected in series with them.
is connected, and the series circuit of Q ₂₅ to _{Q 27} is discharge circuit 1.
1 between V _pd and ground. Switching transistor Q ₂₄ is a regulator transistor
It is interposed between the gate of _Q14 and ground, and is driven together with _Q27 by a new clock φ _p '.

The operation is as follows. First, at the beginning of the precharge operation, the clock φ _p ' turns on the transistor Q ₂₄ to turn off the transistor Q ₁₄ of the regulator, and at the same time turns on the transistor Q ₂₇ , thereby increasing the output voltage V _pd to the threshold of the transistors Q ₂₅ and Q ₂₆ . Reduce the total value to V ₁ (t ₀ is the start of precharge). FIG. 7b shows an example in which the power supply voltage and precharge voltage are 5V, and the clock φ _p is boosted to about 7V by the bootstrap. Since φ _p ' rises at the same time as φ _p rises, the precharge power supply V _pd to the dummy memory cell by the discharge circuit 11 is equal to the sum of the threshold values of transistors Q ₂₅ and Q ₂₆ V ₁ (approximately 2.3 V ). In detail, due to the internal impedance of the discharge circuit, the voltage rises due to the discharge of the dummy memory cell at the initial stage.
V ₀ is occurring. Since the clock φ _p ' exists only in the first half of the clock φ _p , the second half is a transistor.
Since Q ₂₄ and Q ₂₇ are turned off, V _pd is then changed to the intermediate value V 2 of binary information 1 and 0 by the regulator circuit 10 _.
rise to Therefore, at the beginning of the precharge operation, V
Even if _pd is reversely charged, it is discharged by the discharge circuit 11, so that the inconvenience of the voltage V _pd rising to more than V ₂ in the latter half can be avoided.

FIG. 8 shows another embodiment of the present invention. This circuit constitutes an analog arithmetic circuit using MOS transistors, and uses its output voltage V _pd as a precharge power source. Conventionally, analog circuits have rarely been used in digital circuits such as MOS memories. The reason for this is that it is true that there was no need for it, but rather that there is less freedom in circuit design when it is configured only with n-channel type or p-channel type, and it is difficult to obtain desired characteristics. However, in a limited range of applications such as an error amplifier in a voltage regulator, an analog circuit format is possible even in a single-channel semiconductor device. That is, the output voltage V _pd of the circuit shown in FIG. 8 is fixed at approximately 1/2 of the power supply voltage V _DD , and there is no need to widen the output amplitude as in the case of an operational amplifier.

The operation of the circuit shown in FIG. 8 will be explained below. Transistors Q ₂₈ and Q ₂₉ are a differential amplifier 1 that uses a depletion type transistor Q ₃₂ as a common source constant current source.
2, and depletion type transistors Q ₃₀ and Q ₃₁ serve as its load. The output of transistor Q ₂₈ is a depletion type transistor
It is connected to the source follower circuit 13 of transistor Q ₃₃ with Q ₃₅ as a constant current load, and is level-shifted by diode-connected transistor Q ₃₄ to drive output stage transistor Q ₃₇ . Since the transistor Q ₃₆ is driven by the other transistor Q ₂₉ of the differential amplifier 12, the pair of transistors Q ₃₆ and Q ₃₇ in the output stage have opposite phases to each other.
It makes a so-called push-pull motion. Output voltage V _pd
Since it is directly connected to the gate of transistor _Q29 , there is a 100% negative feedback, and the transistor
The voltage gain seen from the gate of _Q28 is 1. Therefore, by connecting the gate of transistor Q ₂₈ to a reference voltage V _S that tracks V _DD by means of a voltage regulator circuit 14 consisting of resistors R ₅ and R ₆ , the same voltage is obtained at the output. As R ₅ and R ₆ , pure resistances such as diffusion may be used, or FET channels may be used. If the output voltage V _pd increases for some reason, the drain current of the transistor Q ₂₉ of the differential amplifier 12 increases, and conversely that of the transistor Q ₂₈ decreases, so the transistor
Q ₃₆ is suitable for cut-off, and vice versa transistor Q ₃₇
conduction is promoted and the increased output voltage is lowered. When V _pd falls, the operation is reversed, so V _pd is always kept at the set potential V _S . Therefore, when the dummy memory cell is precharged, it has a more advanced voltage control function than the series regulator circuit shown in FIG. Incidentally, the same effect can be expected even if the circuit shown in FIG. 8 is replaced with a MOS analog amplifier circuit having the same function.

As described above, according to the present invention, even when setting the pre-charging voltage on the dummy memory cell side to an intermediate value of binary information 0.1, the charge storage part with the same area and the same capacity as the memory cell is sufficient. It has the advantage of being able to increase the density to the limit of manufacturing technology.

[Brief explanation of the drawing]

Figure 1 is a schematic configuration diagram of a dynamic random access memory, Figures 2 to 4 are circuit diagrams, cross-sectional structure diagrams, and plan pattern diagrams showing specific examples of dummy memory cells, and Figures 5 a to c are dummy memory cells. Circuit diagrams of various precharge power supplies for cells, FIG. 6 is a circuit diagram for explaining the problem of the circuit of FIG. FIG. 8 is a circuit diagram of a preliminary charging power supply circuit showing another embodiment of the present invention. In the figure, MC is a memory cell, C _S is its charge storage part, DMC is a dummy memory cell, C _d , Q ₁₀ , Q ₂₂ are its charge storage part, and 1 is the first polycrystalline silicon layer (conductive layer). , 2a, 2b are second polycrystalline silicon layers (conductive layers), 3 is an insulating layer, 4 is a semiconductor substrate, 5
1 is a dielectric film, 10 is a series voltage regulator circuit, 11 is a discharge circuit, 12 is a differential amplifier, and 14 is a voltage regulator circuit.

Claims (1)

[Claims] 1. Providing first and second conductive layers on the surface of a semiconductor substrate with a dielectric film interposed therebetween, and partially overlapping the second conductive layer on top of the first conductive layer with an insulating layer interposed therebetween; Further, in a one-transistor, one-storage capacitor type semiconductor memory device in which the first conductive layer is used as one electrode of a charge storage section and one of the second conductive layers is used as a gate electrode of a transfer transistor, the charge of the memory cell is A pre-charging power supply circuit that makes the storage section and the charge storage section of the dummy memory cell have approximately the same area and the same capacity, and further pre-charges the dummy memory cell with a voltage that is approximately 1/2 of the voltage charged to the memory cell. The pre-charging power supply circuit includes circuit means for dividing the power supply voltage to a predetermined voltage division ratio, and a source follower type output transistor that outputs the pre-charging voltage according to the divided voltage output of the voltage dividing circuit means. 1. A one-transistor, one-storage-capacitor type semiconductor memory device, characterized in that it has a circuit means for suppressing a rise in potential at an output terminal of the output transistor at least at the initial stage of a preliminary charging operation.