JPS61283144A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To flatly form wirings and to eliminate disconnection and shortcircuit of wiring metals by using two or more types of insulating films having different etching velocities as an interlayer insulating film, forming primary electrode and layer wiring metals with the insulating films as spacers, and forming a buried metal for flattening a contacting hole corresponding part of the insulating films in this case. CONSTITUTION:The first insulating film 2a is formed on a substrate 1, and a photoresist 3 is patterned thereon. Then, with the photoresist 3 as a mask the film 2a is removed, and an ohmic metal 4 is deposited. Then, the photoresist 3 is removed, and a gate metal 5 is formed in the film 2a by similar method. Similarly, the second insulating film 2b is formed, and a buried metal 6a is buried in the through-hole corresponding part. The third insulating film 7a is formed thereon, and the metal 8 of the first layer is then formed. At this time, the film 7a has faster etching speed than the film 2b, and the film 2b is not removed by etching when the third film 7a of the metal 8 is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming multilayer wiring in an S-product circuit of a semiconductor device.

[Conventional technology]

A conventional method for forming this type of multilayer interconnection is shown in FIG. is the gate metal. 2a, 2b
is a silicon oxide film.

Insulating film such as silicon nitride film, 8 is first layer wiring metal,
9 is a second layer wiring metal. The structure of the transistor in this figure is shown as an example of a MESFET tank structure.

Next, a method for forming the multilayer wiring shown in FIGS. 2(A) to 2(E) will be described. Ohmic electrode 4 on semiconductor substrate 1
is formed by lift-off or etching such as reactive ion etching, and then a gate electrode 5 is formed in the same manner (FIG. (A)).

Next, an insulating film 2a such as a plasma nitride film is formed (see FIG.
B)). A through hole 11 is formed in the insulating film 2a by a method such as reactive ion etching, and a first layer wiring metal 8 is formed thereon by lift-off or etching such as reactive ion etching (Fig. )). Next, an insulating film 2b is formed thereon, and a through hole 13 is formed (FIG. (D)). Finally, a second layer of wiring metal 9 is formed (FIG. (E)).

[Problem that the invention seeks to solve]

Since the conventional method for forming multilayer wiring is as described above, a step is formed between the ohmic metal, the gate metal, and the wiring metal. This step becomes larger as the layer goes up, making photo-etching for patterning difficult and causing a problem of disconnection or short-circuiting of the wiring metal.

This invention was made in order to solve the above-mentioned problems, and aims to provide a method for forming multilayer wiring that eliminates the step difference caused by the formation of various metals and is less prone to disconnections and short circuits in the metal wiring. purpose.

[Means for solving problems]

The method for forming a multilayer interconnection according to the present invention includes a first step of forming a first insulating film on a substrate and forming a base electrode on required parts thereof by a lift-off method, and forming a second insulating film thereon. A second step is to form a buried metal in a portion corresponding to the contact hole by a lift-off method, and a third insulating film having an etching rate different from that of the underlying insulating film is formed on the third insulating film, and a first step is performed by a lift-off method to the required portions of the third insulating film. A third step of forming a wiring metal layer, and then the second step described above. This step consists of a step of forming a second layer of wiring metal by the same step as the third step.

[Effect]

In the present invention, when forming multilayer wiring, each of the glabella insulating film layer containing wiring metal and the glabella insulating film layer containing metal in the contact hole portion is formed flat using a lift-off method, and Because the insulating film uses an insulating film that has a different etching rate for reactive ion etching than the underlying insulating film, wiring can be formed flat in multiple layers, eliminating problems such as disconnections and short circuits in metal wiring caused by steps. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a semiconductor substrate such as Si*GaAs, 4 is an ohmic metal such as a source and drain of a transistor formed on the substrate 1, 5 is a gate metal, and 3 is a photoresist. 2a, 2b, and 2C are first films such as silicon oxide films and silicon nitride films. Second. The fourth insulating films 5a and 5b are respectively connected to the second insulating films 5a and 5b. Fourth insulation 1i12b
, metal embedded in the through hole part of 2c, 7a, 7b
No. 3 has a faster etching rate of reactive ion etching than the insulating films 2a, 2b, and 2c. fifth insulating film, 8
．． Reference numeral 9 indicates wiring metal of the first layer and the second layer.

Next, a method for forming a multilayer wiring according to an embodiment of the present invention shown in FIGS. 1A to 1H will be described. A first insulating film 2a is formed on a semiconductor substrate 1, and a photoresist 3 is patterned thereon (Figure <A)). Next, using this photoresist 3 as a mask, reactive ion etching is performed to form the first insulating film 2a. is processed and removed, and an ohmink metal 4 is formed by vapor deposition using the same photoresist 3 as a mask (
Figure (B)). Next, the photoresist 3 is removed by a lift-off method to form ohmic gold M4, and then a second insulator li! ! 2b is formed, and a buried metal X16a is embedded in the portion corresponding to the through hole by the same method as described above. Then, a third insulating film 7a is formed thereon,
A first layer of wiring metal 8 is formed in the portion where the first WI eye wiring is to be formed by a method similar to that described above. At this time, the etching rate of the third insulating film 7a is faster than that of the second insulating film 2b, and when the third insulating film 7a of the wiring metal 8 portion is removed, the second insulating film 7a is etched faster than the second insulating film 2b. 2b is not etched away. Furthermore, in the same manner as above, a fourth insulator Im is filled with the embedded metal 6b in the portion corresponding to the through hole.
! 2c is formed, and then a fifth insulating film 7b having a second layer of wiring metal 9 is formed at required portions.

According to this embodiment, since all the layers are formed flat, problems such as disconnections and short circuits in metal wiring can be solved.

Note that in the above embodiments, a transistor with a MESFET structure is used as an example, but multilayer wiring can be formed using a similar method for transistors with other structures. Also,
Although up to two layers of wiring are shown in the above embodiment, any number of layers can be formed by the same method.

〔Effect of the invention〕

As described above, according to the method for forming multilayer wiring according to the present invention, two or more types of insulating films having different etching rates are used as the glabellar insulating film, and these insulating films are used as spacers to form the base electrode and each layer of wiring metal. It was formed by a lift-off method, and at this time, buried metal was provided in the portion of each insulating film corresponding to the contact hole for flattening.
The wiring can be formed flat no matter how many layers there are, and problems such as disconnections and short circuits in metal wiring can be solved.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing a method for forming a multilayer wiring according to an embodiment of the present invention, and FIG. 2 is a process diagram showing a conventional method for forming a multilayer wiring. 1... Semiconductor substrate, 2a, 2b, 2C... 1st
．． second and fourth insulating films, 7a, 7b... third. 5th insulating film, 8... first layer wiring metal, 9... second layer wiring metal. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a method for forming multilayer wiring, a first
The first step is to form an insulating film and form a base electrode on the required part by a lift-off method, and the second step is to form a second insulating film thereon and form a buried metal in a portion corresponding to the contact hole by a lift-off method. a third step in which a third insulating film having an etching rate different from that of the underlying insulating film is formed on the third insulating film, and a first layer of wiring metal is formed in required portions by a lift-off method; , including fourth and fifth steps of respectively forming a fourth insulating film having a buried metal in a portion corresponding to the contact hole and a fifth insulating film having a second layer wiring metal, similarly to the third step. A method for forming multilayer wiring characterized by: