JPS61270922A - Decoder for error correction code - Google Patents

Abstract

PURPOSE:To simplify an error correcting device by providing a memory converting a decode output in the 2nd direction into the series of the 1st direction error correction code and a flag memory storing the 2nd direction decoding error information. CONSTITUTION:A video reproducing data arranged in a matrix is subjected to an error correction decoding by using the 2nd direction correction code (inner code), the result is stored in a buffer memory 21 via serial parallel converting circuits 24A, 24B,-24H and a flag bit representing the data error is stored in a flag memory 22. Then a video data is read from the buffer memory 21 via parallel series conversion circuits 25A, 25B,-25H, the 1st direction correction code (external code) is used with the flag bit to apply error correction and normal reproduction is applied via a D/A converter. At high speed reproduction, the system is controlled so as to write a data not being the 2nd direction error only into the flag bit, the error data is sent to an error correction circuit, where the data is corrected. Thus, a multiplexer circuit used in a conventional system is not required and then the system is simplified.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a digital VTR configured to record digital video signals on a magnetic tape using a rotating head and to reproduce digital video signals from the magnetic tape using a rotating head. The present invention relates to a decoding device suitable for use as an error correction code decoding device.

[Summary of the invention]

This invention provides a first error correction code (referred to as an outer code) and a second error correction code (referred to as an inner code) in two mutually different directions, such as a horizontal direction and a vertical direction, of a two-dimensional array of digital data. In the decoding device for the error correction code that has been encoded, the output decoded by the inner code decoding device 12 is supplied to a large-capacity memory 13, and this memory 13 converts the time series of digital data into outer code data. By converting the data into a series and supplying the output of the memory to the outer code decoding device 14, this memory 13 can be used not only for converting the outer code into a data series but also for restoring data during deshuffling and variable speed playback. Regarding the processing of error information for devices that can be used for both purposes.

This invention focuses on the fact that error information is output from the memory 13 to the outer code decoding device 14, and
The control of error information processing is changed depending on the playback operation. In other words, the present invention supplies the inner code decoding result data and error flag to the outer code decoding device during normal playback or slow motion playback, and supplies the inner code decoding result data and error flag to the outer code decoding device during high-speed playback. Writing of data is prohibited, only error-free reproduced data is written to the buffer memory, and a flag is formed to distinguish between previously reproduced data and newly reproduced data.

[Conventional technology]

Digital V for recording/playing digital video signals
In TR, a product code is known as an error correction code that is effective against burst errors due to dropouts and the like, which encodes a two-dimensional array of data in both the horizontal and vertical directions.

FIG. 7 shows the configuration of a conventional digital VTR reproducing circuit using a product code as an error correction code. A digital signal reproduced from the magnetic tape 38 by the rotary head 37 is supplied to the reproduction input section 41 via a rotary transformer (not shown). The reproduction input section 41 includes a P for clock reproduction.
LL circuit, serial-parallel conversion circuit, block synchronization signal detection circuit.

An address reproducing circuit and the like are provided. Playback input section 41
The output is supplied to the inner code decoder 4.2, and the inner code is decoded.

The time series of the reproduced data matches the order of the data series of the inner code. Therefore, the inner code decoder 42 does not need to rearrange data.

The reproduced data corrected by the inner code is supplied to one input of the outer code decoder 43 and multiplexer 44,
The outer code is decoded by the decoder 43. The other input of the multiplexer 44 is connected to a decoder 43 for outer decoding.
output is supplied. This multiplexer 44 is
During normal playback, the output of the outer code decoder 43 is selected and output, and during variable speed playback, the outer code decoder 43 is bypassed.

The output of the outer code decoder 43 provides digital data that has been subjected to error correction processing for both the inner code and the outer code. This digital data is written to a large capacity buffer memory 45 via a multiplexer 44. This buffer memory 45 can store, for example, three fields of digital data.

Writing to the buffer memory 45 is performed according to the block address added to every two code blocks of the inner code. The buffer memory 45 is provided for data processing during variable speed reproduction when the inclination of the track formed on the magnetic tape 38 and the inclination of the scanning locus of the rotary head 37 do not match. During variable speed reproduction, data is reproduced in fragments, and the data stored in the buffer memory 45 also becomes fragmentary. The buffer memory 45 collectively outputs pieces of data in the same field that are reproduced piecemeal. During variable speed playback, since the data forming the code blocks of the outer code are not aligned, the multiplexer 44 bypasses the outer code decoder 43 and the outer code is not decoded.

The output read from the buffer memory 45 is supplied to a deshuffling circuit 46. Deshuffling circuit 4
6 performs data rearrangement processing that is the opposite of the shuffling circuit provided in the recording circuit in order to return the order of the data series to the original order. Recorded with shuffling/
By performing playback and deshuffling, it is possible to prevent errors from concentrating on one location. The deshuffling circuit 46 is made up of memory.

The capacity of this memory depends on the length of the shuffling unit.

The output of the deshuffling circuit 46 is the error correction circuit 47
supplied to The error correction circuit 47 interpolates the error sample data with surrounding correct sample data. The output of the error correction circuit 47 is sent to the D/A converter 48
is supplied to the output terminal 49, and an analog playback video signal is obtained at the output terminal 49.

[Problem that the invention seeks to solve]

The decoding device of the conventional error correction device described above has a drawback that it requires a large capacity memory in order to rearrange the inner code series to the outer code series in the outer code decoder 43. Further, in the deshuffling circuit 46,
A memory with a capacity corresponding to the unit length of deshuffling is required.

Therefore, an object of the present invention is to arrange a large capacity buffer memory between an inner code decoder and an outer code decoder,
It is an object of the present invention to provide an error correction code decoding device in which this buffer memory is used for conversion to an outer code sequence, deshuffling, and data restoration during variable speed reproduction.

Further, the conventional decoding device bypasses the decoding of the outer code during variable speed playback, performs only the decoding of the inner code, and writes only the data determined to be error-free by the decoding of the inner code to the buffer memory 45. In particular, during variable speed playback, the playback data becomes fragmented, so there is a large amount of past data that remains in the buffer memory 45 without being updated.Such past data deteriorates the playback image quality. Therefore, as described above, once written data is read out, a flag indicating that it is past data is generated.

However, in the case of a configuration in which a buffer memory is placed between an inner code decoder and an outer code decoder, when an error remains as a result of inner code decoding, as in the conventional case,
If writing to the buffer memory is prohibited, even if only part of the data in the code block of the inner code is in error, the entire code block will not be written, which has the disadvantage that the error correction ability of the outer code cannot be fully utilized. .

Therefore, another object of the present invention is to provide an error correction code decoding device that can effectively utilize the correction ability of the outer code and improve the error correction ability during normal playback or slow motion playback. It is in.

[Means for solving problems]

This invention provides a first error correction code (outer code) and a second error correction code for each of a series of digital data located in mutually different first and second directions of a two-dimensional array consisting of a predetermined amount of digital data. In an error correction code decoding device that encodes an error correction code (inner code), an inner code decoder 12 that decodes the inner code and the decoded output of the inner code decoder 12 are supplied, and the decoded output is A buffer memory that converts a time series into an outer code series, an outer code decoder 14 that decodes the outer code to which the output of the buffer memory is supplied, and a flag memory that stores error information of data output from the buffer memory. Then, during normal playback, the decoded output of the inner code decoder 12 and error information of the decoded output are written to the flag memory, and during high speed playback, only non-error data from the decoded output of the inner code decoder 12 is written to the flag memory. This is an error correction code decoding device characterized by comprising means for controlling writing.

[Effect]

A buffer memory is provided between the inner code decoder 12 and the outer code decoder 14 to perform conversion and deshuffling from the inner code series to the outer code series.

Therefore, the buffer memory can be used for data restoration, data sequence rearrangement, and deshuffling during variable speed playback, reducing the required memory capacity and the hardware scale. Furthermore, since playback data can be stored in the buffer memory during slow-motion playback, outer codes can be decoded during slow-motion playback.

Further, during normal playback and slow motion playback, data and error information decoded by the inner code decoder 12 are stored in a buffer memory, and these data and error information are output to the outer code decoder 14. Therefore, the error correction ability of the outer code can be effectively used, and the error correction ability can be improved.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to an error correction code decoding apparatus for a digital VTR will be described with reference to the drawings. The description of this embodiment will follow in the following order.

a, recording circuit A, reproducing circuit C, configuration of buffer memory 13, d, error information processing a, recording circuit FIG. An analog video signal is supplied from an input terminal indicated by 1 to an A/D converter 2, and a digital video signal in which one sample is quantized to, for example, 8 bits is formed, and this digital video signal is supplied to an outer code encoder 3. Ru. In the outer code encoder 3, encoding is performed using an outer code, for example, a (rH+2, m) Reed-Solomon code.

Digital video data from the outer code encoder 3 and outer code parity symbols are supplied to a shuffling circuit 4 . The shuffling circuit 4 is provided to prevent errors from concentrating even when there are many errors, such as during variable speed playback, by changing the order of digital video data. The output data of the shuffling circuit 4 is supplied to the inner code encoder 5, and the inner code, for example (
i+2. i) Reed-Solomon code encoding is performed. In this embodiment, a conventionally known product code as shown in FIG. 5 is used.

In other words, the outer code is encoded every m consecutive symbols (samples) of digital video data, two parity symbols are generated, and these (m+2) symbols form the code block BO of the outer code. It is formed.

The outer code code blocks BO are arranged in i columns, and the inner code is encoded for i symbols crossing the plurality of outer code code blocks BO. n inner code blocks BI each consisting of (i+2) symbols are arranged in the horizontal direction, and the ((m+2)xn) inner code blocks BI constitute a product code unit as a whole.

The output data from the encoder 5 of the inner code is output to the recording output section 6.
supplied to The recording output unit 6 includes a parallel-serial converter,
Includes recording amplifier, etc. A recording signal from the recording output unit 6 is sent to the rotating head 7 via a rotating transformer (not shown).
and recorded on the magnetic tape 8.

When recording on the magnetic tape 8, as shown in FIG. 6, two inner code blocks Bl (diagonal lines indicate parity)
A synchronization signal 5YNC and an address AD are added to the beginning of the synchronization block BS to configure one synchronization block BS. in fact,
The rotary head 7 has a configuration of four rotary heads, two rotary heads each arranged at an angular interval of 180°.

Color video data for 50H (H: horizontal section) is stored in the trunk formed by the second half of one scan of one pair of rotary heads and the first half of one scan of the other pair of rotary heads. It is recorded. Due to the amount of data recorded/reproduced by one rotary head among 50H of data,
A block of product codes as shown in FIG. 5 is formed.

b. Reproducing circuit Signals reproduced from the magnetic tape 8 by the rotating RAD 7 are supplied to the reproducing input section 11 via a rotary transformer (not shown) as shown in FIG.

The reproduction input section 11 is provided with a PLL circuit for reproducing a clock synchronized with reproduction data, a serial-parallel conversion circuit, a block synchronization detection circuit, an address reproduction circuit, and the like. The time series of the reproduced data corresponds to the time series of the inner code, and is supplied to the inner code decoder 12 to decode the inner code. The inner code decoder 12 performs (i
+2°i) It performs error correction and residual error detection of Reed-Solomon codes.

The output data of the inner code decoder 12 is stored in the buffer memory 1.
3. The buffer memory 13 is composed of a large capacity buffer memory for storing data and a flag memory for storing error information, as will be described later. The flag memory stores the decoded output data of the inner code decoder 12 and the accompanying error flag during normal playback and slow motion playback. On the other hand, during high-speed playback, N10 is used to distinguish between past data and new playback data.
Flags are stored in flag memory.

The reproduced video data and error flag output from the buffer memory 13 are supplied to an outer code decoder 14.

The outer code decoder 14 decodes the (m+2, m) Reed-Solomon code. Buffer memory 13
Since the time series of output data is an outer code series, the outer code decoder 14 does not need to be provided with a memory for converting from an inner code series to an outer code series. In this outer code decoder 14, the error flag read from the buffer memory 13 is treated as error information, and in the outer code decoder 14, one error symbol in one outer code block BO is corrected. Ordinary error correction using error flags or pointer laser correction using error flags is performed.

The output data of the outer code decoder 14 is sent to the error correction circuit 1.
5. The error correction circuit 15 is for interpolating error data that cannot be corrected by the outer code decoder 14. The output data of this error correction circuit 15 is taken out to an output terminal 17 via a D/A converter 16. During high-speed reproduction, where the speed of the magnetic tape 8 is faster than during recording, most of the data constituting the outer code block is not complete, so only the inner code is decoded and the outer code is not decoded. In this case, the error is corrected only by the error correction circuit 15.

C. Configuration of Buffer Memory 13 The buffer memory 13 will be explained with reference to FIG. In FIG. 1, a dynamic RAM is used as the buffer memory 13.

In FIG. 1, 21 is a buffer memory for storing digital video signals, 22 is a flag memory for storing error information, and 23 is a memory control circuit. The buffer memory 21 is supplied with input data via eight serial-parallel conversion circuits 24A, 24B, . . . 24H. Further, the output data of the buffer memory 21 is transmitted to eight parallel-to-serial conversion circuits 25A, 25B,
...taken out via 25H.

The input data is 8-bit parallel data of one sample, and is supplied one bit at a time from the most significant bit to each of the serial-parallel conversion circuits 24A to 24H. From each of the serial-parallel conversion circuits 24A to 24H, 1 is output for each bit.
5-bit parallel data is formed. 15 vias of buffer memory 21) Each of the parallel output data is
Each of the serial conversion circuits 25A to 25H converts the data into serial data, and obtains 8-bit parallel output data.

The flag memory 22 is supplied with a 1-bit error flag from the latch 26, and the error flag read from the flag memory 22 is taken into the latch 27. terminal 2
8 supplies the error flag from the inner code decoder 12 to the latch 26. The error flag taken out from the latch 27 to the output terminal 29 is supplied to the outer code decoder 14 together with the data read from the buffer memory 21.

The memory control circuit 23 is supplied with a write clock from a terminal 30 and a read clock from a terminal 31 . Furthermore, the memory control circuit 23 is supplied with a reproduction mode signal from the terminal 32. For example, the playback mode signal becomes high level during normal playback operation where the tape speed during recording is equal to the tape speed during playback, and during slow motion playback operation where the tape speed during playback is slower than the tape speed during recording. For example, it becomes a low level when the tape speed during playback is faster than the tape speed.

The memory control circuit 23 has a common address (ADD) for the buffer memory 21 and flag memory 22.

Generates a row address strobe signal (RAS) and a column address strobe signal (CAS), as well as a write enable signal WE for the buffer memory 21.

A write enable signal RWE and a latch pulse for the flag memory 22 are generated. The write clock is synchronized with the input data and the read clock is formed from the reference clock. Therefore, the buffer memory 21 removes the time axis variation.

Although omitted in FIG. 1, the synchronization block B
Is the playback address for each S memory II? The signal is supplied to the i11 circuit 23, and the write address is determined based on this playback address. The memory control circuit 23 performs conversion from an inner code series to an outer code series and deshuffling by controlling one or both of write addresses and read addresses. Since address control is performed in common between the buffer memory 21 and the flag memory 22, each sample data of the output data and the error flag are synchronized.

d. Processing of error information The first step is to process the error flag input for each sample group among the data from the internal code decoder 12.
This will be explained with reference to the drawings and FIG.

FIG. 2A is a timing signal that defines a read cycle (R) and a write cycle (W). Figure 2B
indicates address ADD supplied to buffer memory 21 and flag memory 22.

The column address is set first, and then the row address is set. FIG. 2C shows the column address strobe signal RAS, and the second diagram shows the row address strobe signal CAS.

The buffer memory 21 performs a read operation when the address ADD is determined, the address strobe signals RAS and CAS are sequentially set to low level, the column address and the row address are sequentially read, and the write enable signal rises. , CAS are sequentially set to low level, the address is read, and when the write enable signal falls, a write operation is performed. The write operation and read operation of the flag memory 22 are similar, but are controlled by a write enable signal RWE different from that of the buffer memory 21.

FIGS. 2E and 2F show examples of write enable signals WE and RWE, respectively, during normal reproduction operation. Second
The write enable signal WE shown in FIG. E always falls to a low level in a write cycle. Therefore, input playback data is sequentially written into the buffer memory 21.

In FIG. 2F, as shown by 33a and 34a, the write enable signal RWE of the flag memory 22 is set to a low level immediately after reading the error flag at a specified address, indicating that there is an error at this specified address. An error flag indicating this is written. If there is no error in the data written to the buffer memory 21 during the low level section 33b of the write enable signal WE, an error flag indicating that there is no error is set in the flag memory 21 during the low level section 33C of the write enable signal RWE. , and the error flag is rewritten.

On the other hand, if there is an error in the data written to the buffer memory 21 in the section 34b, the write enable signal RWE remains at a high level in the section 34C, and the error flag is not rewritten. In this manner, both the data from the inner code decoder 12 and the error flag are stored in the buffer memory 21 and the flag memory 22 during the normal playback operation and during the slow motion playback operation in which the data of the outer code block BO is played back in several fields. will be written to.

Further, FIGS. 2G and 2H show examples of write enable signals WE and RWE, respectively, during high-speed reproduction operation. The flag memory 22 is connected to the buffer memory 21 in the same way as in the above-mentioned normal playback operation and slow motion playback operation.
After data is read from an address, an error flag is written to indicate that the data at that address was previously recovered. In addition, the buffer memory 21 has
Error data is not written. Error-free data is written to the buffer memory 21, and an error flag indicating that there is no error is written to the flag memory 22, and the error flag is rewritten. The data and error flags read from each of the buffer memory 21 and the plug memory 22 are supplied to the error correction circuit 15 and subjected to error correction without being subjected to error correction processing by the outer code decoder 14.

〔Effect of the invention〕

According to the present invention, a large capacity buffer memory can perform conversion to an outer code series, deshuffling, and data restoration during variable speed playback, thereby reducing the memory capacity and the scale of the memory peripheral circuit. can be made smaller.

Further, according to the present invention, by writing error data to the buffer memory during normal playback operation and slow motion playback operation, it becomes possible to correct this error data by the outer code decoder at the next stage. Correction ability can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a buffer memory according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the buffer memory, and FIG. 3 is a block diagram of a recording circuit according to an embodiment of the present invention. 4 is a block diagram of a reproducing circuit according to an embodiment of the present invention, FIGS. 5 and 6 are route diagrams respectively showing the error correction code and the format of recorded data in an embodiment of the present invention, and FIG. The figure is a block diagram of a reproduction circuit of a conventional digital VTR. Explanation of main symbols in the drawings 12: Inner code decoder, 13: Buffer memory,
14: Outer code decoder, 21: Buffer memory for storing data, 22: Flag memory, 23
:Memory control circuit. Agent Patent Attorney Tadashi Sugiura Siblings 1 Figure 3 Figure 8

Claims (1)

[Claims] A first error correction code and a second error correction code are applied to each of the series of digital data located in mutually different first and second directions of a two-dimensional array consisting of a predetermined amount of digital data. In the error correction code decoding device that encodes the error correction code, a second decoding device that decodes the second error correction code and a decoding output of the second decoding device are supplied, and the decoding a memory for converting an output time series into a sequence of the first error correction code; a first decoding device for decoding the first error correction code to which the output of the memory is supplied; and an output from the memory. a flag memory for storing error information of the data to be played; and a flag memory for storing error information of the data to be encoded; and a flag memory for writing the decoding output of the second decoding device and the error information of the decoding output during normal reproduction into the flag memory; A decoding device for an error correction code, comprising means for controlling so that only non-error data out of the decoded output is written into the flag memory.