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JPS61267164A - Abnormality processing system in multiprocessor system - Google Patents

Abnormality processing system in multiprocessor system

Info

Publication number
JPS61267164A
JPS61267164A JP60108139A JP10813985A JPS61267164A JP S61267164 A JPS61267164 A JP S61267164A JP 60108139 A JP60108139 A JP 60108139A JP 10813985 A JP10813985 A JP 10813985A JP S61267164 A JPS61267164 A JP S61267164A
Authority
JP
Japan
Prior art keywords
processor
stop
abnormality
processors
detected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60108139A
Other languages
Japanese (ja)
Inventor
Katsuyuki Miyazaki
宮崎 勝行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60108139A priority Critical patent/JPS61267164A/en
Publication of JPS61267164A publication Critical patent/JPS61267164A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To know surely the condition of a processor at detecting the abnormality by providing the exclusive-use line for stopping the processor between plural processors, detecting the abnormality by an optional processor and stopping immediately all other processors. CONSTITUTION:A program is prepared so that a processor PRS 10 may access the special memory address when the abnormality is detected, an address bus 12 to an individual memory IM11 comes to be a special pattern, this is detected by a decoder DEC 13, the pulse is generated by a timing pulse generating circuit TIM 14, a flip-flop 15 is turned on, a driver 16 is driven and a stop signal is sent to a processor stop line 17. On the other hand, the processor unit of other sub-system receives the stop signal by a receiver 18, then the unit discriminates the coincident conditions with the stop permitting signal from a DBG key 19 with a NAND 20 and indicates the stop of the processor.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はマルチプロセッサシステムにおける異常処理に
係り、特にシステムのデバッグ時に好適なデバッグ手段
を提供するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to abnormal processing in a multiprocessor system, and particularly provides a debugging means suitable for debugging the system.

〔発明の背景〕[Background of the invention]

マルチプロセッサシステムの定義は権々あるが、従来技
術の1例として自動電話交換機やデ。
Although there is an authoritative definition of a multiprocessor system, examples of prior art include automatic telephone exchanges and digital telephone exchanges.

−タ交換機におけるマルチプロセッサをとりあ。- Consider multiprocessors in data exchanges.

げ、その問題を記述する。and describe the problem.

第2図は、自動電話交換機にマルチプロセラ。Figure 2 shows a multiprocessor installed in an automatic telephone exchange.

すを適用した例である。第2図から容易にわか。This is an example of applying the method. It is easy to understand from Figure 2.

るように、本システムは独立した複数個のサブ。As shown in the figure, this system has multiple independent sub-systems.

システム1より構成され1各サブシステムは電。The system consists of 1 and each subsystem is electrically connected.

話交換処理を行うプロセッサユニット(PR8U)2お
よびプログラムやデータ類を格納する個゛別。
A processor unit (PR8U) 2 that performs speech exchange processing and an individual unit that stores programs and data.

メモリ(IM)3、また通話線4を収容し、音声、。It also accommodates a memory (IM) 3 and a voice line 4.

やデータを交換接続するネットワーク(NW) 5)さ
らにそのNW5をPR8U2の指令に基づきコ。
Network (NW) that exchanges and connects data 5) Furthermore, the NW5 is connected based on the command of PR8U2.

シト。ロールするネットワークコントローラ(NWC)
6より構成されている。これら各サブシステムは独立に
動作を行っているが、各サブシス。
Shito. network controller (NWC)
It is composed of 6. Although each of these subsystems operates independently, each subsystem.

テムに共通なリソース、例えば第2図における各サブシ
ス間を接続する通話m6、一般的にはジャンフタと呼ば
れているものは1つのサブシステムで管理することは困
難である。この共通リソース、例えばジャンクタロの空
き、塞り、の管理を行うためのものが共通メモリ7であ
る。
It is difficult for a single subsystem to manage resources common to all systems, such as the communication line m6 connecting each subsystem in FIG. 2, which is generally called a jumper. The common memory 7 is used to manage the common resources, such as free and blocked junk data.

゛ つぎに、止1のサブシステム1に収容されている通
話線4とINのサブシステムに収容されている通話線4
を接続する動作概要は次の様になる。発信側のPR8U
2は着信側のサブシステム番号を加入者からの情報より
識別し、着信側へのジャンクタロが空いているか否かを
CM7より知り、空いていれば該ジャンフタを使用予約
する。次にPR8U2はNWC6を駆動し通話線4と、
ジャンクタロを接続すると、共にプロセッサ間バス9を
通して着信側のプロセッサ8ヘジヤンクタ6と着信側の
通話線4とを接続する要求を送出する。着信側のPR8
U8はこれを受はジャンクタロと通話線4との接続制御
を実行する。このように、マルチプロセッサシステムで
は、プロセッサ間の通信、それも不特定多数のプロセッ
サの通信を行い全体として目的とする処理を実行する。
゛ Next, the communication line 4 accommodated in subsystem 1 of station 1 and the communication line 4 accommodated in subsystem IN
The outline of the operation for connecting is as follows. Calling side PR8U
2 identifies the subsystem number of the called side from the information from the subscriber, learns from the CM 7 whether or not the jumper for the called side is available, and if so, reserves the use of the jumper. Next, PR8U2 drives NWC6 and connects communication line 4.
When the janctor is connected, a request to connect the junctor 6 and the communication line 4 of the terminating side is sent to the processor 8 on the terminating side through the inter-processor bus 9. Called side PR8
U8 receives this and executes connection control between Junctaro and communication line 4. In this way, in a multiprocessor system, communication between processors, especially communication among an unspecified number of processors, is performed to execute a desired process as a whole.

即ち各サブシステムは、独立に制御を実行しているが、
他プロセツサ間との通信により、その制御は決められて
ゆく。このように1つのサブシステム内のプロセッサの
動作、即ちソフトウェアは他プロセツサとの情報交換内
容により大きく影響を受ける。マルチプロセッサシステ
ムが完全に完成されていれば、無論問題はないが、そこ
へ到達するまでのデバッグ、特にソフトウェアのデバッ
グは、他プロセツサとのからみがあり、非常に複雑かつ
多大の工数を要する。特にあるプロセッサが異常を検出
したときは、也プロセッサがどのような動き、即ちどん
なデータな基してて、どんなプログラムが走っていたの
かを知ることがデバッグのキイポイントとなる。
In other words, each subsystem executes control independently, but
Control is determined through communication with other processors. As described above, the operation of a processor within one subsystem, that is, the software, is greatly influenced by the contents of information exchange with other processors. If the multiprocessor system is completely completed, there will of course be no problem, but debugging to reach that point, especially software debugging, involves interaction with other processors, and is extremely complex and requires a large amount of man-hours. In particular, when a certain processor detects an abnormality, the key point in debugging is to know how the processor is operating, that is, what data it is based on, and what programs are running.

従来のマルチプロセッサシステムでは、上記文献に示さ
れるように、あるプロセッサが異常を検出したとき、他
プロセツサを停止させ、その時の各プロセッサの状況を
知るためには1プロセッサ間パス9を通して相手プロセ
ッサに停止要求を出し、それを相手プロセッサが受はメ
ツセージを解乳し、その結果停止するか・または人が強
制的に外部より、例えばコンソール盤から各プロセッサ
を停止させ、個別メモリ3の内容をダンプさせていた。
In a conventional multiprocessor system, as shown in the above-mentioned document, when one processor detects an abnormality, it stops the other processors, and in order to know the status of each processor at that time, one processor communicates with the other processor through the inter-processor path 9. Either a request to stop is issued, the other processor receives the message, decodes the message, and as a result stops each processor, or a person forcibly stops each processor from the outside, for example from a console board, and dumps the contents of the individual memory 3. I was letting it happen.

この様に従来技術では、あるプロセッサが異常を検出し
、他プロセツサな停止させても蔦異常を検出した時点と
他プロセツサが停止する時点とでは時間差があるため、
異常を検出した時点での他プロセツサの状態を把握する
ことができず、ソフトウェアのデバッグは非常に困難で
ある。
In this way, in the conventional technology, even if one processor detects an abnormality and stops other processors, there is a time difference between the time when the abnormality is detected and the time when other processors stop.
It is not possible to grasp the status of other processors at the time an abnormality is detected, making software debugging extremely difficult.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上記した従来技術の欠点をなくシ、ソフ
トウェアのデバッグ、特に異常時のソフトウェアのデバ
ッグに有効なマルチプロセッサシステムを提供すること
にある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a multiprocessor system that is effective for software debugging, particularly for software debugging in abnormal situations.

〔発明の概要〕[Summary of the invention]

本発明は上記した目的を達成するために、各プロセッサ
間にプロセッサ停止用の専用、lll膜設、任意のプロ
セッサが異常を検出し、他プロセッサ全てを直ちに停止
させたい時は該プロセッサ停止線に信号を送出すること
により各プロセッサを強制的に停止させることを特徴と
じたマルチプロセッサの異常処理方式である。
In order to achieve the above-mentioned object, the present invention provides a dedicated processor stop line between each processor, and when any processor detects an abnormality and wants to immediately stop all other processors, the processor stop line is connected to the processor stop line. This is a multiprocessor abnormality processing method characterized by forcibly stopping each processor by sending a signal.

〔発明の実施例〕[Embodiments of the invention]

以下本発明の実施例を図に基づいて説明するe@1図は
本発明を適用したマルチプロセッサ内の1つのプロセッ
サユニットの構成を示したものである。第1図において
プロセッサ(PH1)10および個別メモリ(IM)1
1は従来技術のものと同一である。このPR810が異
常を検出したときに、他プロセツサを停止させる動作概
要を以下に説明する。異常を検出したとき、PR810
は特定のメモリアドレスをアクセスする様プログラムは
作られている。即ちIMllへのアドレスバス12は特
定のパターンになっている。この’lI定パターンをデ
コーダ(DEC) 13で検出すると共にタイミングパ
ルス発生回路(TIM)14によりパルスを発生させ、
7リツプフロツプ15をオンさせる。この7リツプフロ
ツプ15により、ドライバ16を駆動しプロセッサ停止
線17に停止信号を送出する。−万能サブシステムのプ
ロセッサユニットは第2図と同じ構成であるから、プロ
セッサ停止線17からの信号をレシーバ18で受信する
。また他プロセツサからの停止信号によりプロセッサを
停止してもよいことを示すDBGキイ19からの信号と
1停止信号との一致条件をNAND20でq別し、プロ
セッサの停止を指示する0 なお第1図では、異常を検出しても、他プロセツサを停
止させないための停止信号送出禁止キイ20やプロセッ
サをマニアルで停止させるマニアル停止キイ21がかか
れているが本発明とは直接には関係しない。
Embodiments of the present invention will be described below with reference to the drawings. Figure e@1 shows the configuration of one processor unit in a multiprocessor to which the present invention is applied. In FIG. 1, a processor (PH1) 10 and an individual memory (IM) 1
1 is the same as that of the prior art. An outline of the operation of stopping other processors when the PR 810 detects an abnormality will be described below. When an abnormality is detected, PR810
A program is created to access a specific memory address. That is, the address bus 12 to IMII has a specific pattern. This constant pattern is detected by a decoder (DEC) 13 and a pulse is generated by a timing pulse generation circuit (TIM) 14.
7 Turn on the lip-flop 15. This 7-lip flop 15 drives the driver 16 and sends a stop signal to the processor stop line 17. - Since the processor unit of the universal subsystem has the same configuration as in FIG. 2, the signal from the processor stop line 17 is received by the receiver 18. In addition, the NAND 20 is used to differentiate the match condition between the signal from the DBG key 19, which indicates that the processor may be stopped by a stop signal from another processor, and the 1 stop signal, and 0 is used to instruct the processor to stop. Here, a stop signal transmission prohibition key 20 is used to prevent other processors from being stopped even if an abnormality is detected, and a manual stop key 21 is used to manually stop the processor, but these are not directly related to the present invention.

〔発明の効果〕〔Effect of the invention〕

本発明によればマルチプロセッサシステムにおいて、任
意のプロセッサが異常を検出したとき、システム内の全
プロセッサを直ちに停止させることができるので、異常
を検出したとき各プロセッサの状態、即ちどんなプログ
ラムを実行していたか、どんなデータを格納しているか
、さらには、ハードウェアの状態はどんなかを知ること
ができる。これは、多数のプロセッサでもって1つの処
理を実行するマルチプロセッサの異常時の解析、特にソ
フトウェアのデバッグに゛顕著な効果が得られる。
According to the present invention, in a multiprocessor system, when any processor detects an abnormality, all processors in the system can be immediately stopped. You can find out what data is being stored, what data is being stored, and what is the state of the hardware. This has a remarkable effect on analysis of abnormalities in multiprocessors that execute one process using a large number of processors, and especially on software debugging.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のマルチプロセッサシステム
のプロセッサユニットの回路図、第2図は従来のマルチ
プロセッサシステムの一構成図である。 1・・・サブシステム 2・・・プロセッサユニット 5・・・個別メモリ 4・・・通話線 5・−・ネットワーク 7・・・共通メモリ 8・・・プロセッサユニット 9・・・プロセッサ間バス 10・・・プロセッサ 11・・・個別メモリ 12・・・アドレスバス 13・・・デコーダ 14・・・タイミングパルス発生回路 15・・・フリップフロップ 16・・・ドライバ 17・・・プロセッサ停止線 18・・・レシーバ
FIG. 1 is a circuit diagram of a processor unit of a multiprocessor system according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of a conventional multiprocessor system. 1... Subsystem 2... Processor unit 5... Individual memory 4... Communication line 5... Network 7... Common memory 8... Processor unit 9... Inter-processor bus 10. ... Processor 11 ... Individual memory 12 ... Address bus 13 ... Decoder 14 ... Timing pulse generation circuit 15 ... Flip-flop 16 ... Driver 17 ... Processor stop line 18 ... receiver

Claims (1)

【特許請求の範囲】[Claims] 1.複数のプログラム制御のプロセッサと該プロセッサ
間の通信手段を備えたマルチプロセツサシステムにおい
て、各プロセッサ間にプロセッサ停止用の専用線を設け
、任意のプロセッサが異常を検出したとき、該専用線に
プロセッサ停止信号を送出することにより、マルチプロ
セッサ内のすべてのプロセッサを同時に停止させること
を特徴とするマルチプロセッサにおける異常処理方式。
1. In a multiprocessor system equipped with a plurality of program-controlled processors and communication means between the processors, a dedicated line for stopping the processors is provided between each processor, and when any processor detects an abnormality, the processor is connected to the dedicated line. An abnormality processing method in a multiprocessor characterized by simultaneously stopping all processors in the multiprocessor by sending a stop signal.
JP60108139A 1985-05-22 1985-05-22 Abnormality processing system in multiprocessor system Pending JPS61267164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60108139A JPS61267164A (en) 1985-05-22 1985-05-22 Abnormality processing system in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60108139A JPS61267164A (en) 1985-05-22 1985-05-22 Abnormality processing system in multiprocessor system

Publications (1)

Publication Number Publication Date
JPS61267164A true JPS61267164A (en) 1986-11-26

Family

ID=14476923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60108139A Pending JPS61267164A (en) 1985-05-22 1985-05-22 Abnormality processing system in multiprocessor system

Country Status (1)

Country Link
JP (1) JPS61267164A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005527022A (en) * 2002-03-15 2005-09-08 インテル コーポレイション Processor temperature control interface
JP7204057B1 (en) * 2022-03-08 2023-01-13 三菱電機株式会社 Programmable logic controller, CPU unit, control method and program

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005527022A (en) * 2002-03-15 2005-09-08 インテル コーポレイション Processor temperature control interface
JP2011070702A (en) * 2002-03-15 2011-04-07 Intel Corp Processor temperature control interface
JP4717352B2 (en) * 2002-03-15 2011-07-06 インテル コーポレイション Processor temperature control interface
JP2014017018A (en) * 2002-03-15 2014-01-30 Intel Corp Processor temperature control interface
JP7204057B1 (en) * 2022-03-08 2023-01-13 三菱電機株式会社 Programmable logic controller, CPU unit, control method and program

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