JPS6125322A - Multiplexer circuit - Google Patents

Abstract

PURPOSE:To decrease an error due to a leakage current by providing a switch group comprising three switches turned on/off in response to a selection input signal and a non-selection input signal. CONSTITUTION:When an input VIN1 is selected as the selection input signal, switch elements SA1, SB1 are turned on by a control circuit and other switch elements SA2-SAn and SB2-SBn are turned off. Further, a switch element SC1 is turned off and other SC2-SCn are turned on. Thus, two series of leakage currents ILB, ILC exist. Since no potential difference is produced across the elements SC1, SB2-SBn, the relation of ILB 0 is caused and the error due to a leakage current is very small. Since the ILC flows to an output terminal of an operational amplifier 3, the error voltage is (ILC X output resistor of the amplifier 3), and since the output resistance is small, the error voltage is negligibly small. Thus, the error due to the leakage current is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to reducing errors due to wetting current in analog multiplexer circuits.

(Prior Art) FIG. 2 is an equivalent circuit diagram for explaining the operation of a conventional multiplexer circuit. A multiplexer using reed relays or MOS switches as switching elements switches multiple input signals from sensors and the like. The main error factor of this multiplexer is the total 1! flowing through the on-resistance roN of the selected channel! Flow■T, that is, leakage of non-selected channels 1m1
This is the voltage drop that occurs in the on-resistance ros due to the sum of L+ to IL4 and the leakage current (input bias current) of the selected channel.

FIG. 3 shows a conventional example of a two-channel multiplexer circuit that reduces this leakage current. Leakage current is reduced by clamping the unselected signal sources (032 in the figure) to common. However, in this configuration, the input side resistors R3+ and R92 are the output resistance'! of the input signal source e31+032. ! ++'92 and input resistance RI of amplifier 1
rs + * rs2(R311R:I 2
(If the relationship of RIN is not satisfied, the error will not be reduced sufficiently.

(Problems to be Solved by the Invention) The present invention has been made to solve the above problems, and is an analog technology that can reliably reduce errors caused by leakage current flowing through switch elements and improve precision. The purpose is to realize a multiplexer circuit.

(Means for Solving the Problems) The multiplexer circuit of the present invention is a multiplexer circuit that selects and outputs one from a plurality of input signals, and includes a first switch means to which the input signal is applied at one end;
a switch section comprising second and third switch means corresponding to each input signal, one end of which is connected to the other end of the second switch means; and a buffer amplifier connected to the input terminal and the other end of the third switch means connected to the output terminal.

(Function) In the multiplexer circuit having the above configuration, the first . Turn on the second switch and the third switch corresponding to the non-selected input signal, and turn off the first and second switches corresponding to the non-selected input signal and the third switch corresponding to the selected input signal. As a result, the second. By keeping the potentials across the third switch substantially equal, errors due to leakage current can be reduced.

(Example) The present invention will be explained in detail below using the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a multiplexer circuit according to the present invention. SAI~SAn are input signals VxN
A first switch element such as a reed relay or a MOS transistor, S
a+~San are the same second switches connected to one end of each of the switch elements SA1~SAn.
3 is a buffer amplifier with a gain of 1, the other ends of which are connected to the input terminals of the switch elements Ss+ to SBn, and the other ends of the switch elements Sc+ to Scn are connected to the output terminals of the buffer amplifier 3. and a third switch element as described above, each one end of which is connected to the other end of each of the switch elements SAI-SAn; 2 is the switch element SAT-SAn, Sat-San, Sc+
Scn is a switch section, and 4 is an output terminal to which a selection output from the operational amplifier 4 is connected.

When the first input VX
t and Set are on, other switch elements SAJ and SB
j is off (j to i), Sc1 is off, and other SCJs are on. FIG. 3 shows the case 1-1. Leakage current in this case exists in a column. However, ILB2 to ILan are leakage currents of switch elements 882 to San in the off state, I
tct~1tcn is the leakage current m flowing through the switch elements S01~SCn.

Generally, the wetting current of a switch element is approximately proportional to the n-th power of the potential difference across the switch element. If the on-resistance of the switch element is purely resistive, it is n-1, and if it uses a semiconductor PN junction, it is approximately n, -1/2.
becomes. Therefore, if there is no potential difference between both ends of the switch element, the leakage current will be approximately O.

In the circuit shown in Figure 1, if the voltage drop due to the on-resistance of the switch element is ignored, then A1 to An
, B, and C are approximately equal. In other words, no potential difference is generated between the switching elements SC4 and Ss2 to Ssn. Therefore, the current is O in ILa, and the error caused by these leakage currents becomes extremely small.The switching element S
The leakage current flowing through A2 to SAn has the same magnitude as a normal leakage current, but the sum current ILC flows through the output terminal of operational amplifier 3, so the error voltage is ILCX (output resistance of operational amplifier 3) Since the output resistance of the operational amplifier is small, it can be ignored.

FIG. 4 is a partial electrical circuit diagram showing a second embodiment of the present invention in which the error caused by ILC in the embodiment of FIG. 1 is further reduced, and only the parts different in configuration from FIG. It is something. In this case, operational amplifier 5 acts only as an output buffer, and 3 is an operational amplifier with high input resistance.

As in the case of the embodiment shown in FIG. 1, the potentials at point B and point 0 are approximately equal.

FIG. 5 is a circuit diagram of a two-channel differential input type multiplexer according to a third embodiment of the present invention. 8
5+1852 is a signal source, ecMI+ecM2 is a common mode voltage superimposed on this signal source e51+052, and S
A + + + SA 21 has one end connected to the signal source.
Switch elements SA+z and 5A22 each connected to one end of 51+052 have one end connected to the signal source e5+.
The switch elements Sa+j and 5ctj (i, j=1.2) each connect to the other end of the switch element 5A1j, and the switch element 1j connects to the other end of the switch element 5A1j. A buffer amplifier with a gain of 1, the other end of which is connected to the input terminal of 5eaj, and the other end of switch element Sc+j is connected to its output terminal, and 6 is the switch element 5Aij, Sa+j.

5clj, 7 is a differential amplifier circuit in which the other end of the switch element 5ai1 is connected to its non-inverting input terminal, and the other end of the switch element 5B12 is connected to its inverting input terminal; 8 is a differential amplifier circuit which is connected to this difference; This is a selection output terminal to which the output of the dynamic amplifier circuit 7 is connected.

FIG. 5 shows a state in which the channel 1 signal CS+ is selected. As in the previous embodiment, the switch element 5CI
The potential difference between both ends of IISB211SC12 and 5B22 is approximately O, and no leakage current flows.

In addition, generally les + l, 1e + 21 (lecM +
l, 1ecr+21, so the switch element SA2,
A voltage of 80M2 ecMI is applied to 5A22 and a leakage current flows, but the incoming light passes through the amplifiers 11 and 12.
Since the output terminal has low impedance, no errors occur.

The potential of the area surrounded by the broken line 9 in Fig. 5 is uniformly approximately ecM.
Since it is equal to I, it is also possible to make the entire circuit with a monolithic IC that operates with one floating power supply.

In other words, no matter how high the common mode voltage is, SA +
+ * SA 21 I SA +28 and SA 2
It is sufficient if only 2 has a high withstand voltage.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize an analog multiplexer circuit with a simple configuration that can reliably reduce errors caused by leakage current flowing through switch elements and achieve high precision.

[Brief explanation of drawings]

Fig. 1 is a configuration circuit diagram of an embodiment of a multiplexer circuit according to the present invention, Fig. 2 is an equivalent circuit diagram for explaining the operation of a conventional multiplexer circuit, and Fig. 3 is a circuit showing a second conventional example. 4 are partial circuit diagrams of a second embodiment of the present invention, and FIG. 5 is a configuration circuit diagram showing a third embodiment of the present invention. 2.6... Switch section, 3, 11.12... Buffer amplifier) sA+'SAn+SA+++SA2++5A
I21SA22...1 switch means, Sat~S
en, Ss++, Se2+, Sa+2
．． 5s22...Second switch means, Sc+~SCn
, Sc+++sc2++sc+2+5c22・”Third switch means, Vxs+′Vrsn+ e+1.e52
···input signal. Figure 1 Figure 2 Cold N Figure 3 Figure 4

Claims (1)

[Claims] In a multiplexer circuit that selects and outputs one from a plurality of input signals, a first switch means to which the input signal is applied at one end, and second and third switch means whose one ends are connected to the other end of the first switch means. The other end of the second switch means is connected to its input terminal, and the other end of the third switch means is connected to its output terminal. the first and second switches corresponding to the selected input signal and the third switch corresponding to the non-selected input signal are turned on, and the first switch corresponding to the non-selected input signal is turned on; A multiplexer circuit characterized in that the second switch and the third switch corresponding to the selection input signal are turned off.