JPS6125278A - Real time three dimensional image process device - Google Patents

Abstract

PURPOSE:To make it possible to stretch input screen even to a complicated three dimensional object and to obtain special effects of image never experienced before by performing address operation at the write-out side, and by carrying out the interpolation of frame. CONSTITUTION:An input image signal is converted into plural bits of a digital signal by an A/D convertor, and written in memory 14 following a write-address formation circuit 13 after receiving the processing in advance by a low pass filter (LPF)8 and an interpolator 9. Three dimensional address formation circuit 14 stretches an input image signal to a three dimensional object every n frames to form three dimensional addresses X, Y, Z. A frame interpolator 10 interpolates the operated three dimensional addresses X, Y, Z in each n(>1) frame to prepare the data of i frame (n>=i>=1). A fill-up circuit 12 converts two dimensional data after conversion by fluoroscopy into an actual address on the screen.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a real-time three-dimensional image processing apparatus used in the field of image processing, such as broadcasting stations and production facilities.

Conventional configurations and their problems The theory of pasting a two-dimensional input video signal onto a three-dimensional object is widely used in the fields of computers and graphics, but because it requires a huge amount of processing time, it is often used for still images. It is extremely difficult to create a machine that performs mapping in real time.

FIG. 1 shows a conventional real-time three-dimensional image processing device. The configuration of this conventional example will be explained below with reference to FIG.

In FIG. 1, 1 is an A/D converter, and this A/D
The input image is converted into PCM by the converter and written into the memory 4 according to the address generated by the write address generation circuit 6. When reading an image, the input image is pasted in a three-dimensional space by the three-dimensional address generation circuit 3, and by viewing it on the screen, a read address is generated by the read address generation circuit 2, and the memory 4 is read according to the address. The D/A converter 6 converts it into an analog signal and outputs it.

However, in the above conventional example, since the control on the readout side is to obtain a three-dimensional image, frame interpolation to save calculation time cannot be used, and it is necessary to calculate one screen worth of address data for each field. However, there was a drawback that pasting an input image onto a complex three-dimensional object would require an enormous amount of calculation, making it unfeasible. As a result, this conventional example has a drawback in that its functionality is limited to linear transformation regarding a 4×4 matrix.

Purpose of the Invention The present invention eliminates the Kuki of the above-mentioned conventional example.
Paste an input image onto a complex three-dimensional object such as a cylinder, two cones, or an ellipsoid, and process the three-dimensional image as if the object were being freely moved, rotated, reduced, or transformed in three-dimensional space in real time. The purpose is to

Structure of the Invention In order to achieve the above object, the present invention performs address calculation on the writing side and performs one frame interpolation, thereby generating a three-dimensional address by one frame calculation every n/30 seconds. Once generated, the interpolator generates the addresses between them, which increases the calculation time by n times, and allows the input screen to be attached to complex three-dimensional objects, creating unprecedented image special effects. be. At this time, the generated address data is outputted sequentially due to the writing side control, and the memory that stores the data is serial-parallel converted so that an inexpensive low-speed memory can be used, which also has the effect of reducing costs.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, an input video signal is converted into a multi-bit digital signal by an A/D converter 1, subjected to preprocessing by a low pass filter (LPF) 8 and an interpolator 9, and then subjected to a write address generation circuit 13. It is written to memory 4 according to the following.

The three-dimensional address generation circuit 14 pastes the input video signal onto the three-dimensional object every n frames and generates the three-dimensional address X, Y.
, Z is generated. Frame interpolation 1° creates data for i frames (n≧i≧1) by using a frame interpolator to use three-dimensional addresses X, Y, and z calculated every n (>1) frames. A perspective conversion circuit 11 converts a subdimensional address into a two-dimensional address. The hole-filling circuit 12 converts the two-dimensional data after the perspective transformation into a real address on the screen. The video data written in the memory 4 is read out according to the address generated by the read address generation circuit, and then output to the D/A.
A converter 6 converts the signal into an analog video signal and outputs it.

Next, the operation of each part of the above embodiment will be explained.

First, the three-dimensional address generation circuit 14 uses a plurality of 16-bit microprocessors and arithmetic units to generate a two-dimensional input image P, as shown in FIGS. 3(a) and (b).
In this case, for example, (x, y) is pasted on a sphere and a three-dimensional image p' (x, y, z) is calculated using software. This amount of calculation is calculated using the following equations (3-1) to (3-3)
As shown in FIG. 2, the number of three-dimensional addresses P' for all input images is enormous, and software cannot calculate the three-dimensional addresses P' of all input images within one frame time.

However, it has a high degree of versatility, allowing you to change the software even if the object to be pasted changes.

X = Jq2− Y2cos−m−−−−−−(3
-1)y --i-y 0. -0-<
3-2) Z = Jq2- Y2s1n -=-(3
-3) Since the three-dimensional address generation circuit can perform calculation only once every n frames, the frame interpolation path 1o is used to fill in the intervening frames by interpolating the first image and i as shown in Figure 4.
From the +1st image, for example, the following equations (4-1) to (4-
3) In addition to linear interpolation, the three-dimensional address of the intervening frame is calculated.

xn-x.

Xi: X0+-1...(4-1)(n-1)
i) o) n: number of frames to be interpolated The perspective conversion circuit 11 is
The three-dimensional address calculated by frame interpolation is multiplied by a 4x4 matrix in three-dimensional space, and after performing linear transformation such as moving or rotating it to an arbitrary location, 5
figure.

A two-dimensional address Q(ff, m) on the screen is calculated by performing perspective transformation using the similarity of triangles as shown in FIG. In FIG. 6, if the three-dimensional address is P', the triangle P'ZH and the triangle LOH are similar, so the X address 4 on the screen can be calculated using the formula (e-
1), and the y address m is calculated using the formula (e=2).

Since the two-dimensional address Q (#, In) calculated by the perspective conversion circuit 11\ does not apply to the actual pixel on the screen as shown in FIG. Using , the two-dimensional addresses Q, to Q4 are viewed as a lattice, and the memory address (actual pixel address) S within the lattice is calculated. As a method, first, in FIG. 7, the two-dimensional address Q2 having the maximum value in the y direction is
Then, since C2 is not on the memory address,
The decimal part is rounded down to an integer. The straight line based on the integer value of y is e, and the straight line 11 and the straight line Q1.
Q2, straight line Q2. Compute the intersection C,,C2 of C4, and
A real pixel in the grid is searched depending on whether there is a real pixel address between 1 and C2. Similar processing is performed on the straight line 12 obtained by subtracting 1 from this value of y, and in this case, a maximum of two actual pixel addresses are searched. Also at this time, Fig. 8 (2L) t
The normal of the lattice is also calculated as shown in (b), and the normal N Z of
This is done by determining whether the component is positive or negative.

Nz” (X+ , xzXY, +Y2)+(Xz
3XY12+Y3)+ (X, -Xl) (Y, +Y,)
--------(s -1) The write address generation circuit 13 calculates the weight of data to be written to the memory address S determined by the hole filling circuit 12. The data to be written is weighted based on the distances from each of the four points Q1 to q4 of the droplet to S as shown in FIGS. 9(Ia) and 9(b). For example, in the case of FIG. 9(a), S is close to Q, so the image data written to S is Q.
Make the l component the most. Conversely, in the case of Figure 9(b),
It is sufficient to add the image data of 91 to Q4 by %. This weight is sent to the interpolator 9, which performs an interpolation calculation by weighting the image data.

The memory 4 is configured in detail as shown in FIG. 11, and has the following functions.

First, the two-dimensional addresses 91 to Q4 after perspective transformation are the 10th
As shown in the figure, if the perspective transformation is performed on the memory address (real pixel) S, the actual pixels S included in the grid will vary depending on the transformed position of the grid, from a maximum of 2 to 2 as shown in the grid Q+ lC21Qa, Q9. , lattice Q3+ C4+ Qlo +
Like QH, the number changes until there is no minimum. The state of the calculation in FIG. 10 is shown in the timing chart of FIG. 12.

In FIG. 12, e) is the two-dimensional address Q after perspective transformation, and (b) and (Ct) are the memory addresses S included in the grid. Diagonal lines are cases. This is a case where there is no memory address S contained within the child. (d) is a latch pulse of the serial/parallel conversion circuit, and here, for example,
Since 4-phase serial-parallel conversion is performed, one pulse is output for every four S. The pulse causes latch 16 in FIG.
, 20 latch the four-phase interpolated image data and the four-phase memory address S and write them into the low-speed memory 17.21. When processing of 1 field is completed, low-speed memory 1
From 7.21, both are read out four times each,
Parallel-to-serial conversion is performed, and the interpolated data is written to the memory 4 at the write address S.

Finally, the address generated by the read address generation circuit 7 is
Image data is read out from the memory 4 at a sequential address corresponding to an actual scanning line, converted into a digital image data by a D/A converter, and outputted.

In this embodiment, by performing image conversion processing on the writing side, frame interpolation is possible, sufficient calculation time is obtained, and complex three-dimensional objects can be processed as if two-dimensional input images were pasted in real time. In addition, since addresses and image data are output sequentially, high-density and low-cost low-speed memory can be used by using a serial-to-parallel conversion circuit, making it possible to make devices inexpensive and compact. There are advantages.

Effects of the Invention With the above-described configuration, the present invention provides the following effects: 1.

(a) Real-time three-dimensional image processing allows complex three-dimensional effects to be obtained, making it possible to create unprecedented special effects.

(b) Write side control, serial/parallel conversion for writing,
Since parallel-to-serial conversion can be used for reading, an inexpensive, high-density, low-speed memory can be used, and a low-cost, compact three-dimensional image processing device can be constructed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional three-dimensional image processing device;
The figure is a block diagram of a real-time three-dimensional image processing device according to an embodiment of the present invention, FIG. 3 is a diagram explaining the principle of a three-dimensional address generation circuit, FIG. 4 is a diagram explaining frame interpolation,
The figure is a diagram explaining the principle of this device, Figure 6 is a diagram of the principle of perspective transformation, Figure 7 is a diagram of the principle of hole filling, Figure 8 is a diagram explaining hidden surface removal, and Figure 9 is an explanation of weighting of image data. Figure, 10th
Figure 11 is an explanatory diagram of memory and address generation, Figure 1.
Figure 2 is a memory timing chart. 1...A/D converter, 4...memory,
6...D/A converter, 7...Read address generation circuit, 8...LPF, 9...
・Interpolator, 10... Frame interpolation circuit, 11.
. . . Perspective conversion circuit, 12 . . . Hole filling circuit, 13 . . . Write address generation circuit, 14 .
...Three-dimensional address generation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person
ω To Castle Group R Ward Group

Claims (1)

[Claims] After A/D converting the input video signal, it is written into a memory, read out and returned to a video signal by a D/A converter, and the video signal is mapped to a three-dimensional object by generating the address necessary for writing into the memory. a three-dimensional address generation section, a frame interpolation section for saving the calculation time necessary for three-dimensional address generation, a perspective conversion section, a hole-filling circuit for calculating the pixel address on the actual screen, and a filling circuit for calculating the address of the memory according to the address generated as a result. By using a circuit consisting of a write address generation circuit that calculates the final write address,
A real-time three-dimensional image processing device that attaches the video signal to a three-dimensional object in real time and simultaneously performs three-dimensional coordinate transformation.