JPS61251043A - Compression bonded type semiconductor device - Google Patents
Compression bonded type semiconductor deviceInfo
- Publication number
- JPS61251043A JPS61251043A JP9085685A JP9085685A JPS61251043A JP S61251043 A JPS61251043 A JP S61251043A JP 9085685 A JP9085685 A JP 9085685A JP 9085685 A JP9085685 A JP 9085685A JP S61251043 A JPS61251043 A JP S61251043A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metal plate
- electrode
- stamp
- stamp electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は圧接型半導体装置に係り、特に、ダイオード、
サイリスタ或いはゲートターンオフサイリスタＣ以下、
ＧＴｏｌ等の半導体素子に温度補償金属板を介してスタ
ンプ電極を加圧接触させる圧接型半導体装置の面圧力均
一化構造に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a press-contact type semiconductor device, and in particular to a diode,
Thyristor or gate turn-off thyristor C and below,
The present invention relates to a surface pressure equalization structure of a press-contact type semiconductor device in which a stamp electrode is brought into pressure contact with a semiconductor element such as a GTol via a temperature-compensating metal plate.
一般にダイオード、サイリスタ或いはＧＴＯ等の半導体
素子にスタンプ電極を加圧圧接する圧接型半導体装置は
、電力用として良く知られている。2. Description of the Related Art In general, a pressure contact type semiconductor device in which a stamp electrode is pressure-bonded to a semiconductor element such as a diode, thyristor, or GTO is well known for power use.
そしてこの種の圧接型半導体装置は、第３図に示すよう
に構成されている。すなわち、半導体素子１の両面に、
この半導体素子１の熱膨張係数に近・い値の温度補償金
属板２，３を介して熱および電気伝導率の高い、円柱状
のスタンプ電極４．５で半導体素子１を積層方向に圧接
する構造になっている。さらに、上フランジ１１’、１
２、下フランジ１３．１４と同心円状に位置するセラミ
ック円筒１０等の部材により、窒素ガスおよび不活性ガ
ス中で封じ、半導体素子１に外気の水分が触れないよう
に構成されている。This type of pressure contact type semiconductor device is constructed as shown in FIG. That is, on both sides of the semiconductor element 1,
The semiconductor element 1 is pressed in the stacking direction with a cylindrical stamp electrode 4.5 having high thermal and electrical conductivity through temperature-compensating metal plates 2 and 3 whose coefficient of thermal expansion is close to that of the semiconductor element 1. It has a structure. Furthermore, the upper flanges 11', 1
2. It is sealed in nitrogen gas and inert gas by members such as the ceramic cylinder 10 located concentrically with the lower flanges 13 and 14, so that moisture in the outside air does not come into contact with the semiconductor element 1.
半導体素子１は通常ＰＮ拡散されたシリコン３ｉ板、ス
タンプ電極４．５は銅Ｃｕ円柱、そして温度補償金属板
２． ３ｔｉタングステンＷとかモリブデンＭＯ板等が
一般に用いられている。The semiconductor element 1 is usually a PN-diffused silicon 3i plate, the stamp electrode 4.5 is a copper Cu cylinder, and the temperature-compensating metal plate 2. 3ti tungsten W, molybdenum MO plate, etc. are generally used.
実機稼動時には、停止時に比べ８０ｒ程度温度上昇する
。これら起動停止が長年にわたって行われることになる
。３ｉの熱膨張係数はα：２９×１０−６／Ｃ％Ｃｕの
ａ＝１７ＸＩ Ｏ−’／Ｃとその熱膨張係数の差が大な
ので、半導体素子１とスタンプ電極４．５間には、熱膨
張係数α＝ ４．３ Ｘｌ ０−’／ＣのＷとか、α＝
４９ Ｘ １０−’／ＣのＭｏ板を挿入し、半径方向
の熱伸び対策を行っている。When the machine is in operation, the temperature rises by about 80r compared to when it is stopped. These startups and shutdowns will continue for many years. The thermal expansion coefficient of 3i is α: 29×10-6/C%Cu's a=17XI O-'/C. Since the difference in the thermal expansion coefficient is large, there is a gap between the semiconductor element 1 and the stamp electrode 4.5. Thermal expansion coefficient α= 4.3 Xl 0-'/C of W, α=
A Mo plate of 49 x 10-'/C was inserted to take measures against thermal expansion in the radial direction.
第３図に示した構造及びそれと類似の構造は多くの特許
、登録実用新案の説明図等に表示されており公知である
。第３図中、本発明と関連する重要な部分は、カソード
側スタンプ電極４の圧接面の直径寸法を’１％スタンプ
電極４に加圧される厚みがｈなるカンード側温度補償金
属板３の直径をｄ！とすると、ｄ、）ｄｌのときである
。このようになっている場合、半導体素子１とスタンプ
電極４との熱膨張の差をすべらせて逃がすという温度補
償金属板３の本来の目的の他に、スタンプ電極４，５で
上、下より加圧したとき、半導体素子１にかかる面圧力
を若干均一化させて、機械的強度を向上させるという別
の面の効果もある。こコテ、ｄｓ＞ｄｔとなッテｔｎて
ｄ、＝ｄ１＋２Δｒと温度補償金属板３０半径寸法がス
タンプ電極４の圧接面の寸法よりΔｒだけ大きく、温度
補償金属板３の厚みがｈのとき、上記面圧力均一化に対
し、Δｒとｈの寸法によって効果は大分左右される。し
かし、温度補償金属板３の材料は前記したようにタング
ステンＷとかモリブデンＭｏなので、スタンプ電極４．
５の材料鋼Ｃｕに比べ、温度及び電気伝導率が小であり
、温度補償金属板３の厚みをある値以上にすると性能低
下をもたらすし、さらに、材料費の面でも不経済なので
温度補償金属板３の厚みを充分く確保し、かつ半径寸法
をΔｒだけ大として半導体素子１に作用する面圧力を均
一化させることには問題がある。The structure shown in FIG. 3 and structures similar to it are shown in many patents, explanatory diagrams of registered utility models, etc., and are well known. In FIG. 3, the important part related to the present invention is that the diameter of the pressure contact surface of the cathode side stamp electrode 4 is set to 1%. The diameter is d! Then, when d, )dl. In this case, in addition to the original purpose of the temperature compensating metal plate 3, which is to slide and release the difference in thermal expansion between the semiconductor element 1 and the stamp electrode 4, the stamp electrodes 4 and 5 are Another effect is that when pressurized, the surface pressure applied to the semiconductor element 1 is made somewhat uniform, thereby improving mechanical strength. Here, ds > dt, d, = d1 + 2 Δr, and when the radius dimension of the temperature compensation metal plate 30 is larger than the dimension of the pressure contact surface of the stamp electrode 4 by Δr, and the thickness of the temperature compensation metal plate 3 is h, The effect of the above-mentioned surface pressure equalization largely depends on the dimensions of Δr and h. However, since the material of the temperature compensation metal plate 3 is tungsten W or molybdenum Mo as described above, the stamp electrode 4.
The temperature and electrical conductivity are lower than the material steel Cu in No. 5, and if the thickness of the temperature-compensating metal plate 3 exceeds a certain value, the performance will deteriorate, and furthermore, it is uneconomical in terms of material costs, so temperature-compensating metals are used. There is a problem in ensuring a sufficient thickness of the plate 3 and increasing the radius dimension by Δr to make the surface pressure acting on the semiconductor element 1 uniform.
一方、特開昭５８−７１６３３号公報によると、第４図
に示すように半無限弾性体２１を円柱状のポスト２０で
加圧力ｑをもって圧接すると半無限弾性体２１中に生じ
る圧接面に垂直な方向の応力Ｐ（Ｚ）は圧接周端部で非
常に大となり、半無限弾性体２１内の応力分布は著しく
不均一になる。そこで、特開昭５８−７１６３３号公報
に記述されている内容によれば、圧接型半導体装置の半
導体素子に上記のような著しい応力分布の不均一を解消
するため、第５図に示すように、半導体素子２５を圧接
するスタンプ電極２２の側面に溝２３を設け、加圧時に
その溝２３が弾性変形することを利用して、スタンプ電
極２２の周辺直下での半導体素子２５の応力集中を緩和
するようにしている。さらに、半導体素子２５がシリコ
ンＳｉ％温度補償金属板２４が０．５ｆｉ厚みのモリブ
デンＭｏ板、スタンプ電極２２が半径２５５ｗの銅Ｃｕ
円柱体、温度補償金属板２６がタングステンＷであって
、スタンプ電極２２に総荷重５０００〜ｆを印加したと
きのスタンプ電極２２及び温度補償金属板２４０周辺直
下直下の応力を第６図に示したように、溝２３の深さＬ
と高さＨのパラメータとして算出し、Ｐ点での応力集中
を緩和させる構造を提案し、良い結果が得られたと報じ
ている。しかし、本発明者らの実験によれば、それでも
なお、応力集中が充分緩和されているとは云えない結果
が得られた。On the other hand, according to Japanese Unexamined Patent Publication No. 58-71633, when a semi-infinite elastic body 21 is pressed against a cylindrical post 20 with a pressing force q, as shown in FIG. The stress P(Z) in the direction becomes very large at the press-contact peripheral end, and the stress distribution within the semi-infinite elastic body 21 becomes extremely non-uniform. Therefore, according to the content described in Japanese Patent Application Laid-open No. 58-71633, in order to eliminate the above-mentioned significant unevenness of stress distribution in the semiconductor element of the pressure contact type semiconductor device, as shown in FIG. , a groove 23 is provided on the side surface of the stamp electrode 22 that presses the semiconductor element 25, and by utilizing the elastic deformation of the groove 23 when pressurized, stress concentration in the semiconductor element 25 directly under the periphery of the stamp electrode 22 is alleviated. I try to do that. Further, the semiconductor element 25 is silicon Si% temperature compensation metal plate 24 is a molybdenum Mo plate with a thickness of 0.5fi, and the stamp electrode 22 is a copper Cu plate with a radius of 255w.
The cylindrical body and the temperature compensation metal plate 26 are made of tungsten W, and when a total load of 5000 to f is applied to the stamp electrode 22, the stress immediately below the periphery of the stamp electrode 22 and the temperature compensation metal plate 240 is shown in FIG. As such, the depth L of the groove 23
The authors calculated this as a parameter of height H and proposed a structure that alleviates the stress concentration at point P, and reported that good results were obtained. However, according to the experiments conducted by the present inventors, results were obtained that still did not indicate that the stress concentration was sufficiently alleviated.
本発明の目的は上述したスタンプ電極と半導体素子の圧
接面の境界、いわゆる圧接周辺直下に大きな面圧力が生
じるという欠点を解消して、圧接面の面圧力分布がほぼ
均一となる構造の圧接型半導体装置を提供することにあ
る。The purpose of the present invention is to eliminate the above-mentioned drawback that a large surface pressure is generated at the boundary between the press-contact surfaces of the stamp electrode and the semiconductor element, that is, directly under the press-contact periphery, and to provide a press-contact type having a structure in which the distribution of surface pressure on the press-contact surfaces is almost uniform. The purpose of the present invention is to provide semiconductor devices.
〔発明の概要〕 ゛
本発明は、半導体素子を圧接するスタンプ電極の側面だ
溝をつけ、さらにスタンプ電極と同心円状にある温度補
償金属板の直径寸法をスタンプ電極の圧接面の直径寸法
より大きくして、圧接力の力線の流れと全体の変形及び
その反力により、溝の直下、スタンプ電極周辺直下、さ
らに温度補償金属板の周辺直下での半導体素子の圧縮応
力及び曲げ応力集中を緩和するようにしたものである。[Summary of the invention] ゛The present invention provides a groove on the side surface of the stamp electrode that presses the semiconductor element, and furthermore, the diameter of the temperature compensating metal plate that is concentric with the stamp electrode is made larger than the diameter of the press contact surface of the stamp electrode. As a result, the compressive stress and bending stress concentration of the semiconductor element is alleviated directly under the groove, directly under the periphery of the stamp electrode, and also directly under the periphery of the temperature compensating metal plate due to the flow of force lines of the pressure contact force, overall deformation, and its reaction force. It was designed to do so.
第１図は本発明の一実施例の構成図、第２図は第１図の
要部構成図である。これら２つの図で示すようにダイオ
ード等の半導体素子３１のカンード側を、厚みがｈ２、
直径寸法がＤ ｔ ＝ Ｄｔ ＋２１．ｔである温度補
償金属板３３を介して、圧接面の直径寸法がＤｒのスタ
ンプ電極３４で圧接している。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of the main parts of FIG. As shown in these two figures, the cand side of the semiconductor element 31 such as a diode has a thickness of h2,
The diameter dimension is D t = Dt +21. A stamp electrode 34 having a pressure contact surface having a diameter of Dr is pressed through a temperature compensating metal plate 33 having a diameter of t.
このスタンプ電極３４の側面には全周にわたって圧接面
より高さり、の位置に深さｔｌの溝３５を設けている。A groove 35 having a depth tl is provided on the side surface of the stamp electrode 34 at a position that is higher than the pressure contact surface over the entire circumference.
３２はアノード側の温度補償金属板である。なお、第３
図に示したものと同一部分には同一符号を付けている。32 is a temperature compensating metal plate on the anode side. In addition, the third
The same parts as those shown in the figure are given the same reference numerals.
εのように構成した装置に第５図と同様の軸方向（積層
方向）ＩＣ荷重を加え、加圧接触させる。An IC load in the axial direction (in the stacking direction) similar to that shown in FIG. 5 is applied to the device configured as ε, and the device is brought into pressure contact.
上記本発明構造体に対し、現在一般的になっている有限
要素法によって圧接型半導体装置の応力計算を行うと、
スタンプ電極３４の溝３５の寸法ｈ１ ｖ ｔｌ ｓ
及びカンート°側の温度補償金属板３３の厚みｈ２と半
径当りの突出寸法ｔ、をパラメータとして半導体素子３
１の面圧力分布が得られる。When calculating the stress of a press-contact type semiconductor device using the currently common finite element method for the structure of the present invention, the following results are obtained:
Dimensions of the groove 35 of the stamp electrode 34 h1 v tl s
The semiconductor element 3 is calculated using the thickness h2 of the temperature compensating metal plate 33 on the cant side and the protrusion dimension t per radius as parameters.
A surface pressure distribution of 1 is obtained.
具体例として、シリコンＳｉ半導体素子の直径寸法が８
０ｍのとき、銅Ｃｕボスト電極３４の直径寸法ＤＩ＝６
０ｍ、溝３５の高さｈ１＝１．５ｓａｗ。As a specific example, the diameter of a silicon Si semiconductor element is 8
At 0 m, the diameter dimension DI of the copper Cu boss electrode 34 is 6
0 m, height h1 of groove 35 = 1.5 saw.
＃１３５の深さｔＩ＝１ｍｍ、モリブデンＭ ｏ ｇ温
度補償金属板３３の直径寸法ｉ）２＝６３ｍ、厚みｈ２
＝ｏ、５■とすると、温度補償金属板３３の半径寸法突
出ｔｌ、ｓ ＝１．５ａ＋であり、この構成時における
温度補償金属板３３０周辺直下の圧縮応力は零に近い小
さな値であり、また、ポスト電極３４の周辺直下相当の
半導体素子３１の圧縮応力は全体の平均面圧力の値より
若干小さく、圧縮応力の最大は＃３５の深さｔｌの軸方
向直下より若干内に入った部に生じている。#135 depth tI = 1 mm, molybdenum M o g temperature compensation metal plate 33 diameter dimension i) 2 = 63 m, thickness h2
=o, 5■, the radial dimension protrusion tl,s of the temperature compensation metal plate 33 = 1.5a+, and the compressive stress directly under the periphery of the temperature compensation metal plate 330 in this configuration is a small value close to zero, In addition, the compressive stress of the semiconductor element 31 corresponding to the area immediately below the periphery of the post electrode 34 is slightly smaller than the value of the overall average surface pressure, and the maximum compressive stress is at the portion slightly inside the area directly below the depth tl of #35 in the axial direction. It is occurring in
軸方向加圧だけで、振動等による外力の曲げモーメント
を略して、この圧縮応力を更に詳しく調べてみると、溝
３５を付けること等による圧縮応力集中の低下はポスト
電極３４の方が５０チ以下と顕著であり、半導体素子３
１の応力は溝３５等を付けたことにより、大きな応力の
発生する位置が内部に移るが、そのピーク圧縮応力の低
下は２５憾程度である。このような面圧集中低減の違い
は、材料力学の分野で一般化している材料定数の差によ
って説明がつく。いわゆる、銅Ｃｕスタンプ電極３４の
縦弾性係数Ｅ ＝ １２０００Ｋｇｆ／ｍ”であるのに
対し、シリコンＳｉ半導体素子３１のＥ ＝ １８００
０Ｋｆｆ／■２であることより、スタンプ電極３４の方
が変形しやすいので、それに伴い、対応する部のひずみ
ε（単位長さ当りの伸び）が大きくなり、応力σは材料
力学の基本式、σ＝Ｅεより、ひずみεが縦弾性係数Ｅ
の比より大となれ芦、その部の応力の方が大きくなるの
である。If we examine this compressive stress in more detail by applying only axial pressure and omitting the bending moment due to external forces such as vibrations, we find that the reduction in compressive stress concentration due to the addition of the grooves 35 is 50% lower for the post electrode 34. It is remarkable that the semiconductor element 3
As for the stress in No. 1, the position where a large stress occurs is moved to the inside by adding the groove 35, etc., but the decrease in the peak compressive stress is about 25 degrees. This difference in surface pressure concentration reduction can be explained by the difference in material constants, which is common in the field of materials mechanics. The so-called longitudinal elastic modulus of the copper-Cu stamp electrode 34 is E = 12,000 Kgf/m'', whereas that of the silicon Si semiconductor element 31 is E = 1,800.
Since the stamp electrode 34 is more easily deformed than 0Kff/■2, the strain ε (elongation per unit length) of the corresponding part increases, and the stress σ is expressed by the basic formula of material mechanics, From σ=Eε, the strain ε is the longitudinal elastic modulus E
If the ratio is larger than that, the stress in that part will be greater.
一方、第１図、第２図の構成の各積層面盾にろう何部が
ないオール半田レス構造としたときを考え調べてみると
、本発明の構造は半導体素子３１の曲げ応力集中の低減
に威力を発揮する。いわゆる、前記した圧縮、応力の所
で記述した寸法によれば、本発明の構造のもとて半導体
素子３１の最大曲げ応力は内部に移行し、ピーク値を第
５図に示した従来の溝付構造の物に比べＬ以下と小さく
でき、半導体素子３１の機械的強度を５倍以上とするこ
とかできる。On the other hand, when considering and investigating the case where each laminated face shield of the configuration shown in FIGS. Demonstrates power. According to the so-called dimensions described in the above-mentioned compression and stress section, the maximum bending stress of the semiconductor element 31 shifts to the inside due to the structure of the present invention, and the peak value is compared to that of the conventional groove shown in FIG. It can be made smaller than L or less compared to an attached structure, and the mechanical strength of the semiconductor element 31 can be increased by five times or more.
ダイオードについて本発明の効果を具体的忙説明したが
、その他、サイリスタ、ＧＴＯ’またトランジスタにつ
いても同様の応用効果があるのは当然である。また、ア
ノード側のスタンプ電極４０に溝を設けてもよい。Although the effects of the present invention have been specifically explained with respect to diodes, it is natural that similar effects can be applied to thyristors, GTO's, and transistors as well. Further, a groove may be provided in the stamp electrode 40 on the anode side.
本発明によれば、温度補償金属板を介してスタンプ電極
釦より圧接される半導体素子の部分的なｉできるので、
信頼性の向上を図ることができる。According to the present invention, it is possible to partially press contact the semiconductor element with the stamp electrode button through the temperature compensating metal plate.
Reliability can be improved.
第１図は本発明の一実施例になる圧接型ダイオードを示
す縦断面図、第２図は第４図本発明の要部構成断面図、
第３図は従来の一般に知られている圧接型ダイオードを
示す縦断面図、第４図は半無限板を同性で圧接したとき
の応力分布説明図、第５図、第６図は従来の圧接型半導
体装置の縦断面図である。
３１・・・半導体素子、３２・・・アノード側温度補償
金属板、３３・・・カソード側温度補償金属板、３４・
・・カソード側スタンプ電極、３５・・・スタンプ電極
３４の溝。FIG. 1 is a vertical cross-sectional view showing a press-contact type diode according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the main part configuration of the present invention,
Figure 3 is a vertical cross-sectional view showing a conventional, generally known pressure welding type diode, Figure 4 is an illustration of stress distribution when semi-infinite plates are pressure welded with the same sex, and Figures 5 and 6 are conventional pressure welding. FIG. 2 is a vertical cross-sectional view of a type semiconductor device. 31... Semiconductor element, 32... Anode side temperature compensation metal plate, 33... Cathode side temperature compensation metal plate, 34...
. . . Cathode side stamp electrode, 35 . . . Groove of stamp electrode 34.
Claims (1)
に設けられた該半導体素子の熱膨張係数に近い熱膨張係
数を有する温度補償金属板と、該温度補償金属板を介し
て前記半導体素子を圧接するスタンプ電極とを備えた圧
接型半導体装置において、前記スタンプ電極の側面の圧
接面より離れた位置に溝を付け、さらに、前記スタンプ
電極と同心円状にある前記温度補償金属板の直径を、前
記スタンプ電極の圧接面の直径より大きくしたことを特
徴とする圧接型半導体装置。1. A semiconductor element, a temperature compensating metal plate provided on at least one surface of the semiconductor element and having a coefficient of thermal expansion close to that of the semiconductor element, and a temperature compensating metal plate having a thermal expansion coefficient close to that of the semiconductor element; In a pressure contact type semiconductor device including a stamp electrode that is in pressure contact with each other, a groove is formed on a side surface of the stamp electrode at a position remote from the pressure contact surface, and further, the diameter of the temperature compensating metal plate that is concentric with the stamp electrode is A press-contact type semiconductor device, characterized in that the diameter is larger than the diameter of the press-contact surface of the stamp electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9085685A JPS61251043A (en) | 1985-04-30 | 1985-04-30 | Compression bonded type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9085685A JPS61251043A (en) | 1985-04-30 | 1985-04-30 | Compression bonded type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61251043A true JPS61251043A (en) | 1986-11-08 |
Family
ID=14010203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9085685A Pending JPS61251043A (en) | 1985-04-30 | 1985-04-30 | Compression bonded type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61251043A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5189509A (en) * | 1989-12-15 | 1993-02-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and electrode block for the same |
| US6072240A (en) * | 1998-10-16 | 2000-06-06 | Denso Corporation | Semiconductor chip package |
| US6380622B1 (en) | 1998-11-09 | 2002-04-30 | Denso Corporation | Electric apparatus having a contact intermediary member and method for manufacturing the same |
| US6538308B1 (en) | 1998-07-14 | 2003-03-25 | Denso Corporation | Semiconductor apparatus with heat radiation structure for removing heat from semiconductor element |
| US6693350B2 (en) | 1999-11-24 | 2004-02-17 | Denso Corporation | Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure |
| US6703707B1 (en) | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| US6946730B2 (en) | 2001-04-25 | 2005-09-20 | Denso Corporation | Semiconductor device having heat conducting plate |
| JP2015044350A (en) * | 2013-08-28 | 2015-03-12 | キヤノン株式会社 | Liquid discharge head and recording apparatus |
-
1985
- 1985-04-30 JP JP9085685A patent/JPS61251043A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5189509A (en) * | 1989-12-15 | 1993-02-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and electrode block for the same |
| US6538308B1 (en) | 1998-07-14 | 2003-03-25 | Denso Corporation | Semiconductor apparatus with heat radiation structure for removing heat from semiconductor element |
| US7009284B2 (en) | 1998-07-14 | 2006-03-07 | Denso Corporation | Semiconductor apparatus with heat radiation structure for removing heat from semiconductor element |
| US6072240A (en) * | 1998-10-16 | 2000-06-06 | Denso Corporation | Semiconductor chip package |
| US6448645B1 (en) | 1998-10-16 | 2002-09-10 | Denso Corporation | Semiconductor device |
| US6380622B1 (en) | 1998-11-09 | 2002-04-30 | Denso Corporation | Electric apparatus having a contact intermediary member and method for manufacturing the same |
| US6891265B2 (en) | 1999-11-24 | 2005-05-10 | Denso Corporation | Semiconductor device having radiation structure |
| US6798062B2 (en) | 1999-11-24 | 2004-09-28 | Denso Corporation | Semiconductor device having radiation structure |
| US6703707B1 (en) | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| US6960825B2 (en) | 1999-11-24 | 2005-11-01 | Denso Corporation | Semiconductor device having radiation structure |
| US6967404B2 (en) | 1999-11-24 | 2005-11-22 | Denso Corporation | Semiconductor device having radiation structure |
| US6992383B2 (en) | 1999-11-24 | 2006-01-31 | Denso Corporation | Semiconductor device having radiation structure |
| US6998707B2 (en) | 1999-11-24 | 2006-02-14 | Denso Corporation | Semiconductor device having radiation structure |
| US6693350B2 (en) | 1999-11-24 | 2004-02-17 | Denso Corporation | Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure |
| US6946730B2 (en) | 2001-04-25 | 2005-09-20 | Denso Corporation | Semiconductor device having heat conducting plate |
| US6963133B2 (en) | 2001-04-25 | 2005-11-08 | Denso Corporation | Semiconductor device and method for manufacturing semiconductor device |
| JP2015044350A (en) * | 2013-08-28 | 2015-03-12 | キヤノン株式会社 | Liquid discharge head and recording apparatus |
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