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JPS61251047A - Method and apparatus for linking electrode of semiconductor chip to package lead and electronic package - Google Patents

Method and apparatus for linking electrode of semiconductor chip to package lead and electronic package

Info

Publication number
JPS61251047A
JPS61251047A JP61097803A JP9780386A JPS61251047A JP S61251047 A JPS61251047 A JP S61251047A JP 61097803 A JP61097803 A JP 61097803A JP 9780386 A JP9780386 A JP 9780386A JP S61251047 A JPS61251047 A JP S61251047A
Authority
JP
Japan
Prior art keywords
package
integrated circuit
chip
electrode
circuit chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61097803A
Other languages
Japanese (ja)
Other versions
JPH0658924B2 (en
Inventor
カルロ・コネッティ・デ・マルティース
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Microelettronica SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Microelettronica SpA filed Critical SGS Microelettronica SpA
Publication of JPS61251047A publication Critical patent/JPS61251047A/en
Publication of JPH0658924B2 publication Critical patent/JPH0658924B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は一般には半導体装置の実装に関し、より詳細に
は、半導体装置すなわち集積回路を、該半導体装置すな
わち集積回路を有するパッケージから延びるリードに都
合よく結合することのできる集積回路のような半導体装
置の実装に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to the packaging of semiconductor devices, and more particularly, to a method for conveniently coupling a semiconductor device or integrated circuit to leads extending from a package containing the semiconductor device or integrated circuit. It relates to the mounting of semiconductor devices such as integrated circuits.

半導体チップに組立られた離散型式あるいは集積回路の
半導体装置は、より複雑になり、かつ、成分密度の増加
を達成して来たので、集積回路が組立てられているチッ
プを、集積回路成分を利用する回路に結合することはよ
り困難になって来た。集積回路チップと電子回路との間
にインタフェースを発生させる典型的メカニズムは、先
ず集積回路チップをパッケージに位置ぎめし、次いでチ
ップの選択された部分間の細い導線をパッケージの選択
された部分に結合することである。パッケージはそこか
ら延長するリードを有しており、それは、例えばプリン
ト配線板を利用して、電子回路あるいは装置に結合する
のに適している。例えば、パッケージ（リードによって
）は、プリント配線板の孔を介しであるいは電気回路の
ソケットに、挿入することができる。しかし、集積回路
チップからパッケージリードへの電気的結合は、通常、
細密な導線により達成されて来ている。これらの細密導
線はもろく、かつ、半導体チップの伝導領域とパッケー
ジのリード間を付着させることは比較的困難であるとさ
れて来ている。その上、種々の装置すなわちチップの半
導体領域へ電気的に接触するためのパッドを有するチッ
プの上表面は、チップの大きさが、必要に応じて増減す
る場合に特に重要とされる、各種のリードフレームパッ
ケージ寸法と容易に接触できるための、十分な可撓性を
備えていない。As semiconductor devices, either discrete or integrated circuits assembled on semiconductor chips, have become more complex and achieved increased component densities, chips on which integrated circuits are assembled can be used to utilize integrated circuit components. It has become more difficult to combine into circuits that A typical mechanism for creating an interface between an integrated circuit chip and an electronic circuit is to first position the integrated circuit chip in a package and then couple thin conductive wires between selected portions of the chip to selected portions of the package. It is to be. The package has leads extending therefrom, which are suitable for coupling to electronic circuitry or equipment, for example using a printed wiring board. For example, the package (via the leads) can be inserted through a hole in a printed wiring board or into a socket in an electrical circuit. However, the electrical coupling from the integrated circuit chip to the package leads is typically
This has been achieved by using fine conductors. These fine conductive wires have been found to be brittle and relatively difficult to adhere between the conductive regions of the semiconductor chip and the leads of the package. Moreover, the top surface of the chip, which has pads for electrical contact to various devices, i.e., the semiconductor regions of the chip, has various Not flexible enough to easily contact lead frame package dimensions.

従って、パッケージの導電リードを直接に半導体装置す
なわち集積回路チップに、より確実に、かつ、信頼でき
るように結合し、よって強固な電気的結合を生じ、電気
的相互接続を達成しやすくする技術が必要とされる。Accordingly, techniques are needed to more securely and reliably couple the conductive leads of a package directly to a semiconductor device or integrated circuit chip, thereby creating a strong electrical bond and facilitating electrical interconnection. Needed.

従って本発明の目的は、半導体装置すなわち集積回路を
実装する改良技術ならびに方法を提供することである。Accordingly, it is an object of the present invention to provide improved techniques and methods for implementing semiconductor devices or integrated circuits.

本発明の別の目的は、集積回路チップの電極と実装素子
の伝導リードの間で改良された結合を可能にすることで
ある。Another object of the invention is to enable improved coupling between electrodes of an integrated circuit chip and conductive leads of mounted components.

本発明のより特定目的は、チップの拡張パッド領域とリ
ードフレームパッケージの曲り端リード部分との組合せ
を利用して、リードフレームのリードとチップの拡張パ
ッド領域との間でより信頼できる電気接触をさせる、改
良されたパッケージと方法を提供することである。A more specific object of the present invention is to utilize the combination of a chip's extended pad area and a bent end lead portion of a leadframe package to create more reliable electrical contact between the leadframe leads and the chip's extended pad area. The objective is to provide an improved package and method for achieving this goal.

本発明のなお別の目的は、チップの拡張パッド領域とリ
ードフレームパッケージの曲り端リード部分とを組合せ
、種々の大きさのチップが同じパッケージで利用できる
ようにすることによって、パッケージの価格を低減する
ことである。Still another object of the present invention is to reduce the cost of the package by combining the extended pad area of the chip with the bent end lead portion of the leadframe package to allow chips of various sizes to be utilized in the same package. It is to be.

本発明の別の特定目的は、パッケージリードを集積回路
チップに直接適用する手続きを提供することである。Another specific object of the present invention is to provide a procedure for applying package leads directly to integrated circuit chips.

本発明のなお別の特定目的は、伝導リードと電極が容易
に電気的相互接続のできる材料で被覆され得る場合、パ
ッケージのｊ公法リードと集積回路チップの電極との間
で、直接接触を行なうことである。Yet another particular object of the present invention is to make direct contact between the conductive leads of the package and the electrodes of the integrated circuit chip, where the conductive leads and electrodes can be coated with a material that facilitates electrical interconnection. That's true.

集積回路チップに絶縁体の層を具備し、そして１組の比
較的大きい電極を該絶縁体の層の上に溶着することによ
って、前述のおよび他の目的は、本発明に従って達成さ
れる。より大きい電極は集積回路電極に結合されており
、そしてより大きい電極は、パッケージ素子が組立てら
れる場合に、集積回路チップを支持するパッケージの伝
導リードが機械的に接触するように構成される。パッケ
ージリードと大きい電極は、良好なことに、適切な湿潤
性すなわちはんだ付けタイプの化合物で被覆されて、こ
れらの素子と電極を都合よく電気的かつ、機械的に結合
する。The foregoing and other objects are accomplished in accordance with the present invention by providing an integrated circuit chip with a layer of insulator and depositing a set of relatively large electrodes onto the layer of insulator. The larger electrode is coupled to the integrated circuit electrode, and the larger electrode is configured such that conductive leads of the package supporting the integrated circuit chip come into mechanical contact when the package elements are assembled. The package leads and large electrodes are advantageously coated with a suitable wettable or soldering type compound to provide convenient electrical and mechanical bonding between these components and the electrodes.

本発明の１実施例によれば、半導体チップの電極を、該
半導体チップを含むパッケージのリードに結合する方法
は、半導体チップの前原て選択された電極に電気的に結
合された大きい電極を絶縁層に溶着する工程から成り、
該絶縁層は、絶縁層を通って、パッケージリードに直接
接触する大きい電極と接触するよう延長する電極部分は
別にして、チップの電極上に置かれかつそれを保護する
。パッケージリードおよび大きい電極の少なくとも１つ
は、比較的低温で溶ける合金で被覆されている。パッケ
ージリードは、該合金を加熱してそれを流れさせ、湿潤
させそして大きい電極とパッケージリードに結合させる
ことによって大きい電極に電気的１１機械的に結合され
る。According to one embodiment of the present invention, a method for coupling electrodes of a semiconductor chip to leads of a package containing the semiconductor chip includes insulating large electrodes electrically coupled to selected electrodes on a semiconductor chip precursor. Consists of the process of welding the layers,
The insulating layer is placed over and protects the electrodes of the chip, apart from the electrode portions that extend through the insulating layer into contact with larger electrodes that directly contact the package leads. At least one of the package leads and the large electrode is coated with an alloy that melts at a relatively low temperature. The package lead is electrically 11 mechanically coupled to the large electrode by heating the alloy to cause it to flow, wet and bond the large electrode to the package lead.

本発明の別の実施例によれば、電子パッケージは、チッ
プの半導体領域に接触する第１組の電極を有する集積回
路を備える、と説明されている。より大きい第２組の電
極を有するチップは、第１組の電極から絶縁層を通りで
該より大きい第２組の電極と接触するよう延長する電極
部分を別にして、集積回路チップを被覆する絶縁体上に
位置ぎめされている。パッケージは伝導リードを取付け
られて備えられている。該伝導リードを第２組の電極に
電気的、機械的に接続するはんだ付け手段が設けられて
いる。According to another embodiment of the invention, an electronic package is described comprising an integrated circuit having a first set of electrodes contacting a semiconductor region of a chip. A chip having a second larger set of electrodes covers the integrated circuit chip apart from electrode portions extending from the first set of electrodes through the insulating layer into contact with the second larger set of electrodes. positioned on the insulator. The package is equipped with conductive leads attached. Soldering means are provided for electrically and mechanically connecting the conductive leads to the second set of electrodes.

本発明のなお別の実施例によれば、集積回路チップを電
気回路に結合する装置は、電気回路に電気的に結合する
部分を存する伝導手段と、該伝導手段と集積口・路チッ
プを支持するパッケージ手段を備える、と述べられてい
る。集積回路チップは集積回路チップに電気的に接触で
きる拡張電極手段を与える拡張電極手段を有する。According to yet another embodiment of the invention, an apparatus for coupling an integrated circuit chip to an electrical circuit includes a conductive means having a portion electrically coupled to the electrical circuit, and supporting the conductive means and the integrated circuit chip. It is stated that the package includes packaging means for: The integrated circuit chip has extended electrode means providing extended electrode means that can electrically contact the integrated circuit chip.

伝導手段は、拡張電極手段に電気的、機械的に接触を行
なう他の部分を有する。伝導手段の他の部分を拡張電極
に電気的、機械的に結合するはんだ付け手段が備えられ
ている。The conductive means has other parts that make electrical and mechanical contact with the extended electrode means. Soldering means are provided for electrically and mechanically coupling other parts of the conducting means to the extended electrode.

本発明のなお別の実施例によれば、半導体チップをリー
ドフレーム部分に電気的に結合する方法が開示されてい
る。該方法には、半導体チップに拡張電極を形成する工
程と、リードフレーム部分に曲り端を形成する工程、お
よび半導体チップをリードフレーム部分を有するパッケ
ージに、リードフレーム部分の曲り端と拡張電極が接触
するよう、位置ぎめする工程とから成る。According to yet another embodiment of the present invention, a method of electrically coupling a semiconductor chip to a lead frame portion is disclosed. The method includes the steps of forming an extended electrode on a semiconductor chip, forming a bent end on a lead frame portion, and placing the semiconductor chip in a package having a lead frame portion so that the bent end of the lead frame portion and the extended electrode are in contact with each other. It consists of a step of positioning so that the

本発明のこれらのおよび他の特徴は、図面に従い以下の
説明を読むことにより理解されるであろう。These and other features of the invention will be understood by reading the following description in conjunction with the drawings.

第１図には、本発明による半導体というよりはむしろ集
積回路チップ１０が示されている。集積回路それ自体が
チップ１０に形成されている。1, an integrated circuit chip 10, rather than a semiconductor, according to the present invention is shown. The integrated circuit itself is formed on chip 10.

第ルベルの電極すなわち金属被覆（メモリゼーション）
１１は、集積回路の種々の半導体領域に電気的に接続す
るために利用される複数の導体を有する。第ルベルの金
属被覆の導体すなわち電極１１の幾つかは、リードフレ
ーム型式のパッケージすなわちフレームアセンブリの導
線への電気的結合を必要とする。第ルベルの電極１１の
導体の被覆は、二酸化けい素あるいはいずれの適切な溶
着絶縁体のような絶縁コーティング１２となっている。No. 1 Lebel electrode or metal coating (memoryization)
11 has a plurality of conductors utilized to electrically connect to various semiconductor regions of the integrated circuit. Some of the metallized conductors or electrodes 11 of the second level require electrical coupling to conductors of a lead frame type package or frame assembly. The conductor of the first electrode 11 is covered with an insulating coating 12, such as silicon dioxide or any suitable welded insulator.

次に第２レベルの金属被膜１３が絶縁コーティング１２
に溶着されかつ、パターン化される。第２レベルの金属
被膜１３は１組の拡張電極を含み、さらに絶縁コーティ
ング１２を通過する区域すなわち部分１４を介して、第
ルベルの金属被覆における集積回路の選択されたすなわ
ち所定の電極１１に電気的に結合される。該拡張電極組
によってリードフレームリードへの接触を容易にし、さ
らに、チップの大きさが増減したとしても、リードフレ
ームリードが拡張電極すなわちパッドに接触できるよう
にしている（リードフレームのリードと拡張パッドの間
における接触領域だけが、チップの変化寸法と共に変る
のであり、電気的接触は拡張パッドのために達成された
ままとなっているからである）。半導体チップ１０の互
いに異なる半導体領域（Ｎ形あるいはＰ形）は図示され
てはいないが、電極１１によって接触する。Next, a second level metallization 13 is applied to the insulating coating 12.
and patterned. The second level metallization 13 includes a set of extended electrodes and further electrically connects selected or predetermined electrodes 11 of the integrated circuit in the second level metallization through areas or portions 14 that pass through the insulating coating 12. are combined. The extended electrode set facilitates contact with the lead frame leads and also allows the lead frame leads to contact the extended electrodes or pads even if the chip size increases or decreases (lead frame leads and expansion pads Only the contact area between them changes with varying dimensions of the chip, since the electrical contact remains achieved due to the expansion pads). Different semiconductor regions (N-type or P-type) of the semiconductor chip 10 are in contact with each other through the electrodes 11, although they are not shown.

次に第２図では、集積回路を存するチップ１０の上面図
が示される。８つのピンの各々に対して１つのセクタと
して良好に形成された第２レレベルの金属被覆の拡張電
極１３および下に位置する絶縁コーティング１２が見ら
れる。半導体チップ１０は、タブすなわち基板部分１５
上に位置ぎめされているように示される。Referring now to FIG. 2, a top view of chip 10 containing an integrated circuit is shown. The extended electrode 13 of the metallization of the second level, well formed as one sector for each of the eight pins, and the underlying insulating coating 12 can be seen. The semiconductor chip 10 has a tab or substrate portion 15.
It is shown positioned above.

次に第３図では、パッケージアセンブリにおける基板部
分１５とチップ１０の相対的位置ぎめが、本発明による
相互接続技法を明らかにするためにその部分を描出すこ
とにより示される。パッケージの壁２０は、それを通り
抜ける導電リードすなわちリードフレーム部分２１を有
する。チップ／基板アセンブリがパッケージに位置ぎめ
される場合、パッケージの内側で、該リードは曲げられ
、すなわち曲り端部分によって形成されて、第２レベル
の金属被覆の拡張電極１３と接触する。さらに、第２レ
ベルの金属被覆の拡張電極１３およびパッケージに関連
するリード２１は、両方とも、好ましいことに、そこに
付着したあるいはその上を被覆する鉛／錫の化合物すな
わち合金のコーティングすなわち層２２を有する。Turning now to FIG. 3, the relative positioning of substrate portion 15 and chip 10 in a package assembly is illustrated by depicting the portions to clarify interconnection techniques in accordance with the present invention. The package wall 20 has conductive leads or lead frame portions 21 extending therethrough. When the chip/substrate assembly is positioned in the package, inside the package, the leads are bent or formed by bent end portions to contact extended electrodes 13 of the second level metallization. Additionally, both the second level metallization extension electrode 13 and the package associated leads 21 preferably have a lead/tin compound or alloy coating or layer 22 deposited thereon or overlying. has.

第４図には、完成した゛装置の一部切断した斜視図が示
されている。チップアセンブリおよび基板がパッケージ
フレームに適切に置かれる場合、フレーム２０に取付け
られ、それを通り抜けるリード２１は曲り端部分を有し
て、第２レベルの金属被覆の拡張電極１３と物理的に接
触する。FIG. 4 shows a partially cut away perspective view of the completed device. When the chip assembly and substrate are properly placed in the package frame, the leads 21 attached to and passing through the frame 20 have bent end portions to make physical contact with the extended electrodes 13 of the second level metallization. .

良好なことに、リード２１の曲り端部分はパッケージ内
にチップ１０を位置ぎめする前に形成されるが、所望で
あれば、チップ１０がパッケージ内に位置ぎめされた後
でリード２１の曲り端部分を形成することができる。そ
の上、所望であれば、基板１５をパッケージの一部とす
ることもできるし、チップ１０をその上に置き、そこに
うまく固定することもできる。Advantageously, the bent ends of the leads 21 are formed before positioning the chip 10 in the package, but if desired, the bent ends of the leads 21 are formed after the chip 10 is positioned in the package. can form a part. Moreover, if desired, the substrate 15 can be part of the package, and the chip 10 can be placed thereon and conveniently secured thereto.

集積回路パッケージは、例えば回路板のソケットにおけ
るように、それを利用しようとする回路の伝導領域に取
付けるための耐え得る耐久力のあるリードを持たなけれ
ばならない０代表的をアセンブリでは、集積回路チップ
は、第ルベルの金属被覆に位置ぎめされ電極に電気的に
結合された、およびパッケージの導電リードに電気的に
結合されたワイヤを有する。集積回路チップに取付けら
れた従来技術タイプのワイヤは、通常、もろく、かつ、
取付けにくい。本発明は、この電気的結合問題を、第ル
ベルの金属被覆に位置ぎめされたチップの導体／電極よ
り広い区域を有する導体／電極を含む第２レベルの金属
被覆に形成された拡張電極を利用することによって、解
決する。パッケージのリードは、第２レベルの金属被覆
の拡張導体／電極と直接物理的、電気的に接触して位置
ぎめされる。これらの拡張電極の大きさのために、異な
る大きさのチップが同じパッケージで利用でき、そして
典型的な従来技術によるアセンブリの小さいワイヤリー
ドの電気的結合から生ずるもろい接続問題が回避される
。さらに、第２レベルの金属被覆の電極ならびにフレー
ム内部のフレームリードは、各々の表面に、鉛／錫（例
えば９０％鉛７１０％錫あるいは９５％鉛１５％錫のよ
うな）化合物すなわち合金のコーティングを有する。導
体／電極およびフレームリードが接触する場合、微量の
熱が加えられ（例えば、パッケージを炉に入れ、該炉の
内部を、はんだ付けコーティングの液化を達成するに足
る温度にまで加熱することによって）はんだの流れを生
じ、そしてはんだの冷却および接触領域（拡張電極１３
を有するリード２１の曲り端部分）の湿潤の後、それに
続く良好な電気的接触、ならびに強力な機械的結合を生
ずる。An integrated circuit package must have durable leads for attachment to the conductive area of the circuit in which it is intended to be utilized, such as in a circuit board socket.In a typical assembly, the integrated circuit chip has a wire positioned in the metallization of the first rubel and electrically coupled to the electrode and electrically coupled to the conductive leads of the package. Prior art type wires attached to integrated circuit chips are typically brittle and
Difficult to install. The present invention addresses this electrical coupling problem by utilizing an extended electrode formed in the second level metallization that includes a conductor/electrode that has a larger area than the tip conductor/electrode positioned in the metallization of the second level. Solved by doing. The leads of the package are positioned in direct physical and electrical contact with the extended conductors/electrodes of the second level metallization. Because of the size of these extended electrodes, chips of different sizes can be utilized in the same package, and fragile connection problems resulting from electrical coupling of small wire leads in typical prior art assemblies are avoided. In addition, the second level metallized electrodes as well as the frame leads within the frame are coated with a lead/tin (such as 90% lead 710% tin or 95% lead 15% tin) compound or alloy on each surface. has. When the conductor/electrode and frame lead are in contact, a small amount of heat is applied (e.g., by placing the package in an oven and heating the interior of the oven to a temperature sufficient to achieve liquefaction of the solder coating). causing solder flow and solder cooling and contact area (extended electrode 13
After wetting of the curved end portion of the lead 21 with the following properties, a good electrical contact follows, as well as a strong mechanical bond.

このようにして、効果的でしかも構造上頑強な、半導体
すなわち集積回路チップをパッケージのリードに結合す
る方法が達成され得る。その結果、半導体すなわち集積
回路チップと外部の電気回路との間で、電気的に信錬で
きるインタフェースを行う性能上の改良例となっている
。In this way, an effective and structurally robust method of bonding a semiconductor or integrated circuit chip to the leads of a package can be achieved. The result is a performance improvement that provides an electrically compatible interface between a semiconductor or integrated circuit chip and external electrical circuitry.

前述の説明は好ましい実施例の動作を例示しようとする
ものであって、発明の範囲を限定しようと意図するもの
ではない０発明の範囲は冒頭の特許請求の範囲によって
のみ限定されるべきである。上記の説明から、本発明の
精神および範囲に含まれる多くの変化例が、当業者にと
って明白になるであろう。The foregoing description is intended to illustrate the operation of the preferred embodiment and is not intended to limit the scope of the invention, which is to be limited only by the following claims. . From the above description, many variations within the spirit and scope of the invention will be apparent to those skilled in the art.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は半導体すなわち集積回路チップアセンブリの断
面図、第２図は、好ましくは該チップアセンブリが取付
けられている基板部分を含む第１図のチップアセンブリ
の上面図、第３図は第２図のチップアセンブリ／基板構
成の一部分およびチップアセンブリに取付けられるべき
リードフレーム構成の一部分の断面図、そして第４図は
、完成パッケージの内部構成を示すためその１部を切除
して示す、リードフレーム型式のパッケージフレームお
よびチップアセンブリ／基板構成の斜視図である。 １０・・・半導体チップ、１１・・・電極、１２・・・
絶縁層、１３・・・大きい電極、２０・・・パッケージ
、２１・・・パッケージリード、２２・・・合金コーテ
ィング。1 is a cross-sectional view of a semiconductor or integrated circuit chip assembly; FIG. 2 is a top view of the chip assembly of FIG. 1, preferably including a portion of the substrate to which the chip assembly is mounted; and FIG. 3 is a top view of the chip assembly of FIG. FIG. 4 is a cross-sectional view of a portion of the chip assembly/substrate configuration and a portion of the lead frame configuration to be attached to the chip assembly, and FIG. FIG. 2 is a perspective view of the package frame and chip assembly/substrate configuration of FIG. 10... Semiconductor chip, 11... Electrode, 12...
Insulating layer, 13... Large electrode, 20... Package, 21... Package lead, 22... Alloy coating.

Claims (1)

【特許請求の範囲】 １、半導体チップの電極を該チップを含むパッケージの
リードに結合する方法であって、チップ（１０）の予選
択された電極（１１）に電気的に結合された大きい電極
（１３）を絶縁層（１２）に溶着する工程であって、前
記絶縁層（１２）が、絶縁層（１２）を通って、前記パ
ッケージリード（２１）に直接接触している前記大きい
電極（１３）と接触するように延長する電極（１１）の
部分を別にして、前記集積回路チップ電極（１１）の上
に位置ぎめされ、それを保護するように行う溶着工程と
、前記パッケージリード（２１）および前記大きいリー
ド（１３）の少なくとも１つを比較的低温で溶ける合金
（２２）でコーティングする工程と、前記合金（２２）
を加熱して、それを流れさせ、潤滑させかつ前記大きい
電極（１３）を前記パッケージ（２０）に結合させるこ
とによって、前記パッケージリード（２１）を前記大き
い電極（１３）に電気的、機械的に結合する工程とから
成ることを特徴とする結合方法。 ２、前記コーティングする工程は、前記パッケージリー
ド（２１）と前記大きい電極（１３）の両方を前記合金
（２２）でコーティングする工程から成ることを特徴と
する特許請求の範囲第１項記載の結合方法。 ３、チップ（１０）の半導体領域に接触する第１組の電
極（１１）を有する集積回路チップ（１０）であり、該
チップ（１０）は、第１セットの電極（１１）から前記
絶縁層（１２）を通って第２組のより大きい電極（１３
）と接触するよう延長する電極部分を別にして、前記集
積回路チップ（１０）を覆っている絶縁体（１２）に位
置ぎめされた第２組のより大きい電極（１３）を有して
いるような集積回路チップ（１０）と、伝導リード（２
１）を取付けられたパッケージ（２０）と、前記伝導リ
ード（２１）を前記第２組の電極（１３）に電気的、機
械的に接続するはんだ付け手段（２２）とを備えている
ことを特徴とする電子パッケージ。 ４、前記はんだ付け手段（２２）は鉛／錫はんだ付けで
あることを特徴とする特許請求の範囲第３項記載の電子
パッケージ。 ５、集積回路チップを電気回路に結合する装置であって
、前記電気回路に電気的に結合する部分を有する伝導手
段（２１）と、前記伝導手段（２１）と前記集積回路チ
ップ（１０）を支持するパッケージ手段（２０）であっ
て、前記集積回路チップ（１０）は前記集積回路チップ
（１０）への電気的接触を可能とする拡張電極手段（１
３）を有し、前記伝導手段（２１）は、前記集積回路チ
ップ（１０）が前記パッケージ手段（２０）に結合され
る場合、前記拡張電極手段（１３）に電気的、機械的に
接触を行なう他の部分を有するようなパッケージ手段（
２０）と、前記伝導手段（２１）の前記他の部分を前記
拡張電極手段（１３）に電気的、機械的に結合するはん
だ付け手段（２２）とを備えていることを特徴とする結
合装置。 ６、前記集積回路チップ（１０）は、前記パッケージ手
段（２０）に結合されている基板部材（１５）に結合さ
れていることを特徴とする特許請求の範囲第５項記載の
結合装置。 ７、前記伝導手段（２１）はリードフレームであり、そ
して前記拡張電極手段（１３）は前記リードフレームに
取付けられていることを特徴とする特許請求の範囲第５
項記載の結合装置。 ８、前記リードフレームのリード（２１）は前記パッケ
ージ手段（２０）の内側に延長していることを特徴とす
る特許請求の範囲第７項記載の結合装置。 ９、前記伝導手段（２１）の前記他の部分は曲り端部分
を有し、そして前記曲り端部分の端部分は前記拡張電極
手段（１３）と機械的、電気的に接触していることを特
徴とする特許請求の範囲第５項記載の結合装置。 １０、半導体チップをリードフレーム部分に電気的に結
合する方法であって、半導体チップ（１０）に拡張電極
（１３）を形成する工程と、前記リードフレーム部分（
２１）に曲り端を形成する工程と、前記半導体チップ（
１０）を前記リードフレーム部分（２１）を含むパッケ
ージ（２０）に、前記リードフレーム部分（２１）の前
記曲り端と前記拡張電極（１３）が接触するよう位置ぎ
めする工程とから成ることを特徴とする電気的結合方法
。[Claims] 1. A method for coupling electrodes of a semiconductor chip to leads of a package containing the chip, the method comprising: a large electrode electrically coupled to a preselected electrode (11) of the chip (10); (13) to an insulating layer (12), the insulating layer (12) passing through the insulating layer (12) and directly contacting the package lead (21). A welding process is performed to position and protect the integrated circuit chip electrode (11), apart from the part of the electrode (11) that extends to make contact with the package lead (13). 21) and coating at least one of said large leads (13) with an alloy (22) that melts at a relatively low temperature; and said alloy (22)
The package lead (21) is electrically and mechanically connected to the large electrode (13) by heating to cause it to flow, lubricate and bond the large electrode (13) to the package (20). A joining method characterized by comprising the step of joining. 2. The combination according to claim 1, characterized in that said step of coating comprises the step of coating both said package lead (21) and said large electrode (13) with said alloy (22). Method. 3. an integrated circuit chip (10) having a first set of electrodes (11) in contact with a semiconductor region of the chip (10), the chip (10) having a first set of electrodes (11) to said insulating layer; (12) through a second set of larger electrodes (13
) having a second set of larger electrodes (13) positioned on an insulator (12) covering said integrated circuit chip (10), apart from an electrode portion extending into contact with said integrated circuit chip (10). integrated circuit chip (10) and conductive leads (2
1) and a soldering means (22) for electrically and mechanically connecting the conductive lead (21) to the second set of electrodes (13). Features an electronic package. 4. Electronic package according to claim 3, characterized in that said soldering means (22) is lead/tin soldering. 5. A device for coupling an integrated circuit chip to an electric circuit, comprising a conductive means (21) having a portion electrically coupled to the electric circuit, and a conductive means (21) and the integrated circuit chip (10). Packaging means (20) supporting said integrated circuit chip (10), said integrated circuit chip (10) having extended electrode means (1) enabling electrical contact to said integrated circuit chip (10).
3), said conductive means (21) being in electrical and mechanical contact with said extended electrode means (13) when said integrated circuit chip (10) is coupled to said packaging means (20). packaging means (such as having other parts carrying out
20); and soldering means (22) for electrically and mechanically coupling the other portion of the conductive means (21) to the extended electrode means (13). . 6. A device according to claim 5, characterized in that the integrated circuit chip (10) is connected to a substrate member (15) which is connected to the packaging means (20). 7. The conductive means (21) is a lead frame, and the extended electrode means (13) are attached to the lead frame.
Coupling device as described in section. 8. The coupling device according to claim 7, characterized in that the leads (21) of the lead frame extend inside the packaging means (20). 9. The other part of the conducting means (21) has a bent end part, and the end part of the bent end part is in mechanical and electrical contact with the extended electrode means (13). A coupling device according to claim 5, characterized in that: 10. A method for electrically coupling a semiconductor chip to a lead frame portion, the method comprising: forming an extended electrode (13) on the semiconductor chip (10);
21) forming a bent end on the semiconductor chip (
10) in a package (20) including the lead frame portion (21) so that the bent end of the lead frame portion (21) and the extended electrode (13) are in contact with each other. electrical coupling method.
JP61097803A 1985-04-26 1986-04-26 Semiconductor device package and manufacturing method thereof Expired - Fee Related JPH0658924B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT20504A/85 1985-04-26
IT8520504A IT1215268B (en) 1985-04-26 1985-04-26 APPARATUS AND METHOD FOR THE PERFECT PACKAGING OF SEMICONDUCTIVE DEVICES.

Publications (2)

Publication Number Publication Date
JPS61251047A true JPS61251047A (en) 1986-11-08
JPH0658924B2 JPH0658924B2 (en) 1994-08-03

Family

ID=11167929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61097803A Expired - Fee Related JPH0658924B2 (en) 1985-04-26 1986-04-26 Semiconductor device package and manufacturing method thereof

Country Status (6)

Country Link
JP (1) JPH0658924B2 (en)
DE (1) DE3614087C2 (en)
FR (1) FR2581247B1 (en)
GB (1) GB2174543B (en)
IT (1) IT1215268B (en)
NL (1) NL193513C (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959706A (en) * 1988-05-23 1990-09-25 United Technologies Corporation Integrated circuit having an improved bond pad
DE69420841T2 (en) * 1994-07-13 2000-01-05 United Microelectronics Corp., Hsinchu Method of eliminating the antenna effect during manufacturing
EP0693782B1 (en) * 1994-07-13 2000-11-15 United Microelectronics Corporation Method for reducing process antenna effect
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US7071024B2 (en) 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
DE50212872D1 (en) * 2002-11-29 2008-11-20 Infineon Technologies Ag Semiconductor chip with terminal pads and arrangement of such a semiconductor chip on a support

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4870476A (en) * 1971-12-23 1973-09-25
JPS5091269A (en) * 1973-12-12 1975-07-21
JPS5445574A (en) * 1977-09-17 1979-04-10 Tdk Corp Connection method of integrated circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3458925A (en) * 1966-01-20 1969-08-05 Ibm Method of forming solder mounds on substrates
FR1569479A (en) * 1967-07-13 1969-05-30
NL169122C (en) * 1970-02-26 1982-06-01 Toyo Electronics Ind Corp SEMICONDUCTOR ELEMENT COMPRISING SEMICONDUCTOR PLATE BY AN INSULATION COATED HEAD FLAT WITH PADS extending unbroken OVER PARTS OF THE INSULATION LAYER AND ADJACENT PARTS faces of the semiconductor wafer, AND METHOD FOR FIXING THE SEMICONDUCTOR ELEMENT ON A TERMINAL PROVIDED MOUNTING PLATE.
CA954635A (en) * 1972-06-06 1974-09-10 Microsystems International Limited Mounting leads and method of fabrication
JPS5851425B2 (en) * 1975-08-22 1983-11-16 株式会社日立製作所 Hand tie souchi

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4870476A (en) * 1971-12-23 1973-09-25
JPS5091269A (en) * 1973-12-12 1975-07-21
JPS5445574A (en) * 1977-09-17 1979-04-10 Tdk Corp Connection method of integrated circuit

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GB2174543A (en) 1986-11-05
IT1215268B (en) 1990-01-31
IT8520504A0 (en) 1985-04-26
NL193513B (en) 1999-08-02
JPH0658924B2 (en) 1994-08-03
FR2581247B1 (en) 1991-03-29
NL8601073A (en) 1986-11-17
DE3614087C2 (en) 1999-05-06
FR2581247A1 (en) 1986-10-31
GB8609260D0 (en) 1986-05-21
GB2174543B (en) 1988-11-16
DE3614087A1 (en) 1986-10-30
NL193513C (en) 1999-12-03

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