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JPS61225829A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61225829A
JPS61225829A JP60068282A JP6828285A JPS61225829A JP S61225829 A JPS61225829 A JP S61225829A JP 60068282 A JP60068282 A JP 60068282A JP 6828285 A JP6828285 A JP 6828285A JP S61225829 A JPS61225829 A JP S61225829A
Authority
JP
Japan
Prior art keywords
chip
semiconductor chip
silicon
support plate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60068282A
Other languages
English (en)
Other versions
JPH0682715B2 (ja
Inventor
Masahiro Sugimoto
杉本　正浩
Kunihiko Wada
邦彦 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60068282A priority Critical patent/JPH0682715B2/ja
Publication of JPS61225829A publication Critical patent/JPS61225829A/ja
Publication of JPH0682715B2 publication Critical patent/JPH0682715B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
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    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/102—Material of the semiconductor or solid state bodies
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    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に係わり、特に大口径半導体ウェ
ハで形成された半導体チップをパフケージングする際に
、半導体チップ材料とパッケージ材料とが膨張係数が等
しく、且つ熱放散の良好なパッケージ構造に関するもの
である。
大口径であろウェハから形成したり、又はウェハそのも
のを用いた半導体チップは、数インチの大きさとなる場
合がある。
この半導体チップには、マイクロコンピータ等の比較的
大規模の回路が形成され、パンケージの配線本数も数千
率に達することになる。
従って、それぞれの配線の接続部の信頼性が必要であり
、叉上記のごとく半導体チップが大きいので、パフケー
ジング後の実際の動作状態で温度が上昇した際に、チッ
プが破損しないような高信頼で安全な構造が要望されて
いる。
〔従来の技術〕
第２図は、従来の半導体装置のパッケージ構造を示す主
要断面図である。
大口径半導体チップ１　　（Ｆｕｌｌ　Ｗａｆｅｒ　５
ｉｚｅ　Ｉｎｔｅｇｒａｔｉｏｎ　Ｃｈｉｐ）があり、
この大口径半導体チップはアルミナ材料で形成された支
持板２に収納されていて、大口径半導体チップと外部配
線が行われる支持板２との接続は、アルミニウム線又は
金線等を使用したボンデングワイヤ３によって、それぞ
れの接続がなされている。
支持板２の上部に取りつけられる封着蓋４は、材料がア
ルミナ又はコバール等で形成されており、支持板２とレ
ジン又は半田付けによって気密封着が行なわれている。
支持板の内部からの外リードピン５はパフケージの壁面
を貫通して、所定部分から外部に引き出されている。
このような大口径の半導体チップでは、ウェハ゛の材料
であるシリコンの膨張係数が、３．９ｘｌＯ−６であり
、一方、支持板の材料であるアルミナの膨張係数は７ｘ
ｌＯ−６であって、両者が大きく異なるために、パッケ
ージが高温になると、それぞれの熱膨張の差によって、
強度の弱い大口径の半導体チップが破損することがある
他、従来は半導体チップと支持板との配線が、一本ごと
にワイヤボンデングによって行っていたため、多ピンの
場合は長時間の工数を要し、信頼性も劣るという欠点が
ある。
〔発明が解決しようとする問題点〕
上記の半導体装置のパッケージの構造では、チップの膨
張係数と、チップを収納するパッケージ材料との膨張係
数の差のためにチップが破損する恐れがあることと、多
数の配線がワイヤボンデングで行われるために多大の時
間を要し、コストアップの原因になる。
〔問題を解決するための手段〕
本発明は、上記問題点を解消した半導体装置を提供する
もので、その手段は、半導体チップがシリコンカーバイ
ドの支持板の収納部に固着され、半導体チップ表面上に
設けられた電極パッドと、該支持板に接着される接続用
基板に設けられたバンプとが接続されてなることを特徴
とする半導体装置よって達成できる。
〔作用〕
本発明は、大口径のウェハ等から形成される半導体チッ
プの材料とパッケージ材料との膨張係数の差によるチッ
プの破損を防止するため、半導体チップへの電気的接続
を短時間に行うために、熱伝導の良好なシリコンと極め
て類似の膨張係数を有するシリコンカーバイドを使用し
て、半導体チップの底部をパンケージに固着し、一方、
配線は半導体チップの表面上に設けられた電極パッドに
よって、上部蓋部の配線とバンプ接続をする。
従って、半導体チップの破損が防止できると共に、配線
の強度を強化して信頼度を高めるようにしたものである
。
〔実施例〕
第１図は、本発明の一実施例を示す半導体装置のパフケ
ージングされた状態での主要断面図を示している。
シリコンウェハから形成された半導体チップ１１は、シ
リコンの膨張係数と殆ど同様の値を有するシリコンカー
バイドで形成された支持板１２の内部の収納部１８に固
着され、半導体チップ１１と支持板１２は、半田、又は
レジンのようなソルダ１３によって固定されている。
半導体チップには、例えば大きさが４インチ乃至６イン
チのウェハを用い、その周辺部分には配線用の電極パッ
ド１４が設けてあり、それに対応する接続用基板１５に
も外部配線用の配線１６と連結されるバンプ１７が設け
てあり、バンプの材料は例えば金等で製作されている。
接続用基板は、シリコンカーバイドにポリイミド等を用
いて形成され、この接続用基板にはシリコンカーバイド
の他に、二酸化シリコンとアルミナの化合物よりなるム
ライト・セラミックスや、ガラスセラミックスを用いる
ことができる。
パッドとバンプの接合は、両者の位置合わせを厳重に行
った後、支持板１２と接続用基板１５を接合して矢印の
ように圧着することにより確実に接続されるが、更に支
持板１２に接続用基板１５を捻子止め又はバネ止めを行
ってもよい。
この配線用のバンプの数は半導体チップの寸法によって
、数十個に達することがあり、高精度に配列されること
が必要である。
このような構造からなる半導体装置は、半導体チップと
パッケージの材料である支持板や接続用基板との膨張係
数の差から発生する半導体ウェハの破損がなく、又接続
用基板と半導体ウェハとのバンプ接続も確実に行われて
、動作中に発熱するための膨張係数の差による歪力がな
（なり、安定なパッケージ構造が実現できる。
又、アルミナに比較してシリコンカーバイドは熱伝導が
優れており、半導体装置が動作中に発生する熱を放散す
る効果にも大となり、高信願性のパフケージングを行う
ことができる。
〔発明の効果〕
以上、詳細に説明したように、本発明の半導体装置は、
半導体チップの破損防止と配線の信頼性の向上及び発熱
を低下させる効果があり、高信頼性の半導体装置を供し
得るという効果大なるものがある。
【図面の簡単な説明】
第１図は、本発明の一実施例を示す半導体装置のバフケ
ージの主要断面図、 第２図は、従来の半導体装置のパンケージ構造を示す主
要断面図である。 図において、 １１は半導体チップ、　　１２は支持板、１３はソルダ
、　　　　　　１４は配線用のバンド、１５は接続用基
板、　　　１６は配線、１７はバンプ、　　　　　１８
は収納部、をそれぞれ示している。

Claims (1)

    【特許請求の範囲】
  1. 半導体チップがシリコンカーバイドの支持板の収納部に
    固着され、半導体チップ表面上に設けられた電極パッド
    と、該支持板に接着される接続用基板に設けられたバン
    プとが接続されてなることを特徴とする半導体装置。
JP60068282A 1985-03-29 1985-03-29 半導体装置 Expired - Lifetime JPH0682715B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60068282A JPH0682715B2 (ja) 1985-03-29 1985-03-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60068282A JPH0682715B2 (ja) 1985-03-29 1985-03-29 半導体装置

Publications (2)

Publication Number Publication Date
JPS61225829A true JPS61225829A (ja) 1986-10-07
JPH0682715B2 JPH0682715B2 (ja) 1994-10-19

Family

ID=13369251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60068282A Expired - Lifetime JPH0682715B2 (ja) 1985-03-29 1985-03-29 半導体装置

Country Status (1)

Country Link
JP (1) JPH0682715B2 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US5103290A (en) * 1989-06-16 1992-04-07 General Electric Company Hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5135890A (en) * 1989-06-16 1992-08-04 General Electric Company Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5315486A (en) * 1991-12-16 1994-05-24 General Electric Company Hermetically packaged HDI electronic system
JP2015207747A (ja) * 2014-04-17 2015-11-19 政宏 星野 ワイドバンドギャップ半導体デバイス

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4868170A (ja) * 1971-12-20 1973-09-17
JPS5146874A (en) * 1974-10-18 1976-04-21 Mitsubishi Electric Corp Handotaisochino seizohoho
JPS55143042A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4868170A (ja) * 1971-12-20 1973-09-17
JPS5146874A (en) * 1974-10-18 1976-04-21 Mitsubishi Electric Corp Handotaisochino seizohoho
JPS55143042A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5103290A (en) * 1989-06-16 1992-04-07 General Electric Company Hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5135890A (en) * 1989-06-16 1992-08-04 General Electric Company Method of forming a hermetic package having a lead extending through an aperture in the package lid and packaged semiconductor chip
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US5315486A (en) * 1991-12-16 1994-05-24 General Electric Company Hermetically packaged HDI electronic system
JP2015207747A (ja) * 2014-04-17 2015-11-19 政宏 星野 ワイドバンドギャップ半導体デバイス

Also Published As

Publication number Publication date
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