JPS61224427A - Package for high frequency integrated device - Google Patents
Package for high frequency integrated deviceInfo
- Publication number
- JPS61224427A JPS61224427A JP60065191A JP6519185A JPS61224427A JP S61224427 A JPS61224427 A JP S61224427A JP 60065191 A JP60065191 A JP 60065191A JP 6519185 A JP6519185 A JP 6519185A JP S61224427 A JPS61224427 A JP S61224427A
- Authority
- JP
- Japan
- Prior art keywords
- package
- frequency integrated
- integrated device
- main part
- cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- H01—ELECTRIC ELEMENTS
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は高周波集積デバイス用パッケージに関し、より
特別にはＩｎＰ、 ＧａＡｓ等化合物半導体を用いた高
周波集積デバイス用のパッケージの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a package for a high frequency integrated device, and more particularly to an improvement of a package for a high frequency integrated device using a compound semiconductor such as InP or GaAs.
（従来の技術）
従来、化合物半導体を用いた高周波集積デバイス用のノ
々ツケージとして、第２図（ａ）に上面図（但し、内部
構造が見えるようにキャップを外しである）を、また同
図（ｂ）に中央断面図を示すように、導電性パッケージ
の主要部１に形成したステージ２上に複数の半導体チッ
プ３，５と絶縁性回路基板７とをマウントし、これらを
ワイヤ９にて結合するとともにそれらの内部端子をガラ
スＩＩＫて封止された！ｊ −ト’１３を介して引き出
したものを導電性のキャップ１５にてカバーしてなるパ
ッケージ構造は公知である。(Prior Art) Conventionally, a top view of a node cage for high-frequency integrated devices using compound semiconductors is shown in FIG. As shown in the central cross-sectional view in FIG. The internal terminals were sealed with glass IIK! A package structure in which an electrically conductive cap 15 covers an electrically conductive cap 15 is known.
（発明が解決しよウレする問題点）
しかしながら、上記騰貴のものは複数の半導体チップ３
，５が空間を介して直接隣接する構造となっているため
、例えばチップ３を第１段増幅器、チップ５を第２段増
幅器として使用した場合、大出力に増幅された高周波信
号は空間や寄生容量を介して前段へ影響を及ぼすことに
なる。すなわち、両増幅段相互間に電磁結合を生じ、寄
生発振等の異常動作を引き起すことになり、このため回
路の性能不良や効率低下の原因となり、また甚しい場合
には寄生発振による発熱のため半導体チップを破損させ
ることになる。(Problems that would be solved by the invention) However, the above-mentioned Toki's has multiple semiconductor chips 3
, 5 are directly adjacent to each other with a space in between. For example, when chip 3 is used as a first-stage amplifier and chip 5 as a second-stage amplifier, the high-frequency signal amplified to a large output is This will affect the previous stage through the capacitance. In other words, electromagnetic coupling occurs between both amplifier stages, causing abnormal operation such as parasitic oscillation, which causes poor circuit performance and reduced efficiency, and in severe cases, heat generation due to parasitic oscillation. Therefore, the semiconductor chip will be damaged.
（問題点を解決するための手段）
本発明は上記従来の欠点を除去すべくなされたものであ
って、このため本発明は、導電性パッケージの主要部上
に半導体チップと絶縁性回路基板とを含む複数の回路ユ
ニットをマクントし、これを導電性のキャップにてカバ
ーしてなる高周波集積デバイス用パッケージにおいて、
前記パッケージ主要部が各回路ユニット間にて前記絶縁
性回路基板の主面より突出する部分を有し、該突出部分
の上端が前記キャップの内側面に密着しかつ電気的に導
通していることを特徴とする。(Means for Solving the Problems) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and for this reason, the present invention provides a method for disposing a semiconductor chip and an insulating circuit board on the main part of a conductive package. In a high-frequency integrated device package that includes multiple circuit units including
The main part of the package has a part protruding from the main surface of the insulating circuit board between each circuit unit, and the upper end of the protruding part is in close contact with the inner surface of the cap and is electrically conductive. It is characterized by
（作 用）
各回路ユニット間にて導電性のパッケージ主要部より突
出した部分の上端が導電性のキャップ内側面と接触し、
電気的に導通しているため、各回路ユニットはそれぞれ
電気的に遮蔽された部分に分割され、各回路ユニット間
の電磁的結合が突出部分によって遮断される。したがっ
て、電磁結合 １による寄生発振や異常動
作はな（、Ｓ／Ｎ、Ｒの増大や回路性能の安定化などの
点で改善を図ることができる。(Function) The upper end of the part protruding from the main part of the conductive package between each circuit unit comes into contact with the inside surface of the conductive cap.
Because they are electrically conductive, each circuit unit is divided into electrically shielded parts, and electromagnetic coupling between each circuit unit is interrupted by the protruding parts. Therefore, parasitic oscillations and abnormal operations due to electromagnetic coupling 1 can be avoided (improvements can be made in terms of increases in S/N and R, stabilization of circuit performance, etc.).
（実施例） 以下、本発明の好適な実施例につき説明する。(Example) Hereinafter, preferred embodiments of the present invention will be described.
第１図は本発明の一実施例を示すもので、第２図と同一
参照番号は同一構成部品を示す。該実施例では、まずパ
ッケージ主要部１を銅−タングステン合金を用いて作製
した。該合金材料はタングステ／に銅を重量ＣＣで１８
％の割合で含有させ、溶浸法によって形成した。この合
金の線膨張率は６．８刈０−６ａｎ／ｃｙｒｒ℃とＧａ
Ａｓの線膨張率とほぼ一致しており、また同合金の熱伝
導率は０．６５／ｓａｃ・α・ｄｅｇであった。この合
金母材を研削加工により第１図に示すような形状とした
。すなわち、半導体チップ３，５を装着するステージ２
と１回路基板７を装着する凹部８と、突出部１０と、リ
ード線１３を引出す穴とを設ける。次に、該主要部に鉄
ニツケルメッキを約２μｍはどこしたあと融着用ガラス
１１を用いて鉄ニツケル合金からなるリード線１３を上
記穴に融着形成した。さらに、金メッキを約１μｍはど
こし、これで主要部１を完成した。FIG. 1 shows an embodiment of the present invention, and the same reference numerals as in FIG. 2 indicate the same components. In this example, first, the main part 1 of the package was manufactured using a copper-tungsten alloy. The alloy material is tungsten/copper with a weight CC of 18
% and was formed by an infiltration method. The coefficient of linear expansion of this alloy is 6.8 0-6an/cyrr℃ and Ga
The coefficient of linear expansion almost matched that of As, and the thermal conductivity of the alloy was 0.65/sac·α·deg. This alloy base material was formed into the shape shown in FIG. 1 by grinding. In other words, the stage 2 on which the semiconductor chips 3 and 5 are mounted
A recess 8 into which a circuit board 7 is mounted, a protrusion 10, and a hole through which a lead wire 13 is drawn out are provided. Next, after approximately 2 μm of iron-nickel plating was applied to the main portion, a lead wire 13 made of an iron-nickel alloy was fused into the hole using a fusing glass 11. Furthermore, approximately 1 μm of gold plating was applied to complete the main part 1.
次に、アルミナセラミックの基板７の裏面全体をメタラ
イズし１表面に増幅回路のパターン７′をスクリーン印
刷法により形成したあと、該セラミック基板７をパッケ
ージ主要部１の凹部８にロウ付けした。次いで、共晶合
金法によりＧａＡｓからなる高周波増幅用のＦＥＴチッ
プ３，５をステージ２に装着し、金のワイヤ９を用いて
セラミック基板γ上の所定の接合パット“と結線すると
同時にリード線１３との接続および突出部により分離さ
れた回路基板間の接続も行った。さらに、セラミック基
板７上にチップ抵抗、チップ容量を乗せてはんだ付けす
ることにより回路網を完成する。最後に、銅−コバール
積層板からなるキャップ１５を主要部１上にロウ付けす
ることにより高周波集積デバイスの一つである第１段お
よび第２段増幅器を備えた高周波増幅器が完成する。Next, the entire back surface of the alumina ceramic substrate 7 was metallized and an amplifier circuit pattern 7' was formed on one surface by screen printing, and then the ceramic substrate 7 was brazed into the recess 8 of the main part 1 of the package. Next, the FET chips 3 and 5 for high frequency amplification made of GaAs are mounted on the stage 2 by the eutectic alloy method, and connected to a predetermined bonding pad "on the ceramic substrate γ using the gold wire 9, and at the same time the lead wire 13 Connections were also made between the circuit boards separated by the protrusions.Furthermore, a chip resistor and a chip capacitor were placed on the ceramic substrate 7 and soldered to complete the circuit network.Finally, the copper - By brazing the cap 15 made of a Kovar laminate onto the main part 1, a high frequency amplifier including first and second stage amplifiers, which is one of the high frequency integrated devices, is completed.
このよう忙して作製した増幅器は、突出部１０により電
磁結合を遮断しであるため入力段の雑音が減少し、最小
検出感度を従来のものに比べて約１０倍に改良すること
ができた。また、このように電磁結合を遮断する構造と
したため、抵抗や容量の配置は自由に選定することがで
き、特に各増幅段相互の関係を考慮せずに各増幅段ごと
に各素子のレイアウトを決定したが、所定の性能を発揮
することができた。The amplifier thus produced was able to block electromagnetic coupling by the protrusion 10, thereby reducing input stage noise and improving the minimum detection sensitivity by about 10 times compared to the conventional amplifier. In addition, because the structure is designed to block electromagnetic coupling, the placement of resistors and capacitors can be freely selected, and the layout of each element can be changed for each amplification stage without considering the relationship between each amplification stage. However, we were able to achieve the desired performance.
また、パッケージ主要部１に用いた銅−タングステン合
金は線膨張率がＩｎＰないしＧａＡｓにほぼ一致してい
るため、半導体チップ３，５とステージ２との間に線膨
張率差による応力の発生がなく、しかも熱伝導率が良好
であるため半導体チップの信頼性を向上させることがで
きる。加速劣化試、験のデータを用いて素子３，５の寿
命を推定したところ、従来の１０倍以上の寿命が得られ
ることがわかった。また、上記の合金材料は放熱特性が
良好であり、通常のコバールや鉄製のパッケージと比較
して約１０倍以上の熱伝導率を有する。従って熱特性の
点でも優れており、このため素子の電力容量の増大乃至
小型化を図ることができる。本発明の一実施例によれば
、従来半導体チップ当りの消費電力の上限が１００ｍｗ
程度であったものが１５０ｍＷ程度まで耐えられること
がわかった。なお、パッケージ主要部１の材料は、上記
の合金材料の他に、タングステン、モリブデンまたはタ
ングステン・モリブデン合金に均一に銅を含有させた合
金であってかつ４．０×１Ｏ−６ｃｒＩＬ／ｃｒｌＬ℃
乃至７．ＯＸｌ、Ｏ−６ｃｍ／ＣｒｒＬ℃の線膨張率を
もつ合金であれば同様な効果を得ることができる。さら
に、キャップ１５の材料として、通常用いられる鉄、ニ
ッケル、コバール等に代えて上記のように銅−コメール
積層板を用いることにより、キャップ部分の導電率を主
要部と同様に高くすることができ、これによって遮蔽効
果を著るしく向上させることができる。Furthermore, since the coefficient of linear expansion of the copper-tungsten alloy used for the main part 1 of the package is almost the same as that of InP or GaAs, stress is not generated between the semiconductor chips 3 and 5 and the stage 2 due to the difference in coefficient of linear expansion. Moreover, since the thermal conductivity is good, the reliability of the semiconductor chip can be improved. When the lifespan of elements 3 and 5 was estimated using data from the accelerated deterioration test and test, it was found that the lifespan was ten times longer than that of the conventional device. Furthermore, the above-mentioned alloy material has good heat dissipation properties, and has a thermal conductivity that is about 10 times higher than that of ordinary Kovar or iron packages. Therefore, it has excellent thermal characteristics, and therefore the power capacity of the device can be increased or the device can be made smaller. According to an embodiment of the present invention, the upper limit of power consumption per semiconductor chip is 100 mw.
It was found that it could withstand up to about 150 mW. In addition to the above-mentioned alloy materials, the material of the main part 1 of the package is tungsten, molybdenum, or an alloy of tungsten-molybdenum alloy containing copper uniformly, and has a temperature of 4.0×1O-6crIL/crlL°C.
to 7. A similar effect can be obtained with an alloy having a coefficient of linear expansion of OXl, O-6cm/CrrL°C. Furthermore, by using a copper-komel laminate as described above instead of the normally used iron, nickel, Kovar, etc. as the material for the cap 15, the conductivity of the cap part can be made as high as that of the main part. , which can significantly improve the shielding effect.
（発明の効果）
以上のように、本発明によれば高周波用集積デバイスパ
ッケージにおいて各回路ユニット間の電磁結合による異
常動作をなくすことができるので、通信用中継器やデー
タリンク等高周波を扱う機器の小型化、高信頼性化を図
ることができる。また、パッケージ内のチップや部品の
配置は電磁的にシールド′された各ユニットごとに考え
ればよいので、設計、製作が容易となり、コスト低減に
もつながる。(Effects of the Invention) As described above, according to the present invention, it is possible to eliminate abnormal operation due to electromagnetic coupling between circuit units in a high-frequency integrated device package. It is possible to achieve smaller size and higher reliability. Furthermore, since the arrangement of chips and components within the package can be considered for each electromagnetically shielded unit, design and manufacture are facilitated, leading to cost reduction.
第１図（ａ）は本発明の高周波集積デバイス用パッケー
ジの上面図（但しキャップを外しである）、第１図（ｂ
）は同パッケージの中央断面図、第２図（ｍｌは従来パ
ッケージの第１図（ａ）と同様な図、第２図（日は同従
来パッケージの中央断面図である。
１・・・パッケージ主要部、３，５・・・半導体チップ
７・・・回路基板、 １０・・・突出部分１５
・・・キャップ
（外５名）
第１図
１ ： パ・ソケージ缶委仰
３．５： チ導伴チップ
７ ：回％幕根
１０ ：に憔師分
１５： キャップFIG. 1(a) is a top view of the high-frequency integrated device package of the present invention (with the cap removed), FIG.
) is a central cross-sectional view of the same package, FIG. Main part, 3, 5...Semiconductor chip 7...Circuit board, 10...Protruding part 15
...Cap (5 people outside) Figure 1 1: Pa Socage Can Commission 3.5: Chi-doban Chip 7: Times % Makune 10: Nisushishi Min 15: Cap
Claims (3)
縁性回路基板とを含む複数の回路ユニットをマウントし
、これを導電性のキャップにてカバーしてなる高周波集
積デバイス用のパッケージにおいて、前記パッケージ主
要部が各回路ユニット間にて前記絶縁性回路基板の主面
より突出する部分を有し、該突出部分の上端が前記キャ
ップの内側面に密着しかつ電気的に導通していることを
特徴とする高周波集積デバイス用パッケージ。(1) In a package for a high-frequency integrated device, which includes a plurality of circuit units including a semiconductor chip and an insulating circuit board mounted on the main part of a conductive package and covered with a conductive cap, the above-mentioned The main part of the package has a part protruding from the main surface of the insulating circuit board between each circuit unit, and the upper end of the protruding part is in close contact with the inner surface of the cap and is electrically conductive. A package for high-frequency integrated devices with special features.
デンまたはタングステン・モリブデン合金に均一に銅を
含有させた合金であつてかつ４．０×１０＾−＾６ｃｍ
／ｃｍ℃乃至７．０×１０＾−＾６ｃｍ／ｃｍ℃の線膨
張率をもつ合金よりなることを特徴とする特許請求の範
囲第１項の高周波集積デバイス用パッケージ。(2) The main part of the package is made of tungsten, molybdenum, or a tungsten-molybdenum alloy containing copper uniformly, and has a size of 4.0 x 10^-^6 cm.
The package for a high frequency integrated device according to claim 1, characterized in that the package is made of an alloy having a linear expansion coefficient of /cm°C to 7.0×10^-^6cm/cm°C.
層複合材料からなることを特徴とする特許請求の範囲第
１項または第２項の高周波集積デバイス用パッケージ。(3) The package for a high frequency integrated device according to claim 1 or 2, wherein the cap of the package is made of a laminated composite material of copper and Yuval.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60065191A JPH0622250B2 (en) | 1985-03-29 | 1985-03-29 | Package for high frequency integrated devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60065191A JPH0622250B2 (en) | 1985-03-29 | 1985-03-29 | Package for high frequency integrated devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61224427A true JPS61224427A (en) | 1986-10-06 |
| JPH0622250B2 JPH0622250B2 (en) | 1994-03-23 |
Family
ID=13279782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60065191A Expired - Fee Related JPH0622250B2 (en) | 1985-03-29 | 1985-03-29 | Package for high frequency integrated devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622250B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2838915B1 (en) * | 2002-04-22 | 2005-09-30 | Cit Alcatel | IMPROVED METHOD FOR ASSEMBLING COMPONENTS ON A RADIOFREQUENCY TERMINAL UNIT BASE PLATE |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5522183U (en) * | 1978-07-31 | 1980-02-13 | ||
| JPS5844853U (en) * | 1981-09-19 | 1983-03-25 | 三菱電機株式会社 | semiconductor equipment |
-
1985
- 1985-03-29 JP JP60065191A patent/JPH0622250B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5522183U (en) * | 1978-07-31 | 1980-02-13 | ||
| JPS5844853U (en) * | 1981-09-19 | 1983-03-25 | 三菱電機株式会社 | semiconductor equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0622250B2 (en) | 1994-03-23 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |