JPS61212120A - A/d converter - Google Patents

Abstract

PURPOSE:To reduce spike-like noise by fetching a comparison result from an output of an inverting circuit by turning on/off the first - the third switches in a prescribed period in a digital video chroma processing circuit of a color television receiver, using it as a digital conversion output through an encoder, and also interposing a capacitor between an analog input to be converted and a ground. CONSTITUTION:The titled converter is constituted of comparing circuits 11, 12... whose number corresponds to the resolution, and an encoder 10, and on chips of the comparing circuits 11, 12... which are formed by a C-MOS process; a capacitor 9 is provided between an input terminal 2 and a ground. In such a way, a charge/discharge current to a floating capacity existing across a capacitor 8 is compensated by a charge/discharge current from the capacitor 9, and the influence of an error voltage by spike-like noise to an input signal is reduced. Accordingly, even if a sampling frequency (clock frequency) of an A/D converter goes to high, an A/D conversion is executed with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an AD converter in a digital video chroma processing circuit of a color television receiver.

Conventional technology Digital video chroma circuits convert analog composite video signals into digital signals and convert them into Y by digital signal processing.
- After processing such as C separation and color demodulation, analog conversion is performed to obtain a color difference or primary color signal of an analog signal.

Conventionally, the sampling frequency for AD conversion has been selected to be three or four times the carrier frequency. Generally, a parallel comparison type is used as an AD converter system that uses a sampling frequency of this order of magnitude. The parallel comparison type converts the analog signal into a digital code by comparing the magnitude of the comparison voltage generated by the comparison voltage generation circuit and the input signal using the comparison circuit. A comparison circuit of the configuration could be used. In recent years, chopper type comparison circuits using MO8 type transistors have become the M of the entire integrated circuit.
It is being used as an OS. -C-MOS as an example
FIG. 2 shows the configuration of the comparison circuit according to the process.

An analog input signal is input to an input terminal (2) of an integrated comparator circuit (1). The comparator circuit (1) includes a 1-inversion circuit (3), a first switch (4) connected between its input and output terminals, and first and second voltage dividers (5□) that divide the reference voltage ( 5□) and the first and second voltage dividers (51) (
A series circuit of second and third switches (6) and (7) connected in series between connection point P1 of 52) and the input terminal (2); switch (7
) and a capacitor (8) connected between the connection point P2 and the input terminal of the inverting circuit (3).

Next, the operation shown in FIG. 2 will be explained. The same clock CK is applied to the first switch (4) and the second switch (6), and the clock 107 having the opposite phase to the above clock CK is applied to the third switch (7). As a result, during the period when the first switch (4) and the second switch (6) are "OFF", the third switch (7) is "ON", and during the first period, the third switch (7) is "OFF". The second switch (6) is “ON”
L, the third switch (7) turns LIQFF.
During the period when the switch (4) and the second switch (6) are “ON”, the input and output of the inverting circuit (3) are short-circuited, so the inverting circuit (3) side of the capacitor (8) The potential of is one half of the power supply voltage. Capacitor (
The potential on the input terminal (2) side of 8) is connected to the voltage divider (5,) (5 m
) becomes the potential divided by voltage. Therefore, capacitor (8)
The difference voltage between the divided voltage of the reference voltage and one-half of the power supply voltage is held. Next, during the period when the third switch (7) is "ON", the analog input signal from the input terminal (2) passes through the third switch (7) and is applied to the input terminal side of the capacitor (8). . Since the aforementioned differential voltage is already held in the capacitor (8), the inverting circuit (3
) is inputted with the sum voltage of the voltage of the input analog input signal and the differential voltage. The threshold voltage at the input of the inverting circuit (3) is one-half of the power supply voltage, so if the divided voltage of the reference voltage is higher than the input voltage, the output of the inverting circuit (3) will have a high voltage (in logic). #J11j), if the divided voltage of the reference voltage is lower than the input voltage, a lower voltage (“O” in logic) appears. The operating principle of the comparison circuit (1) is as described above.

To configure an AD converter using this comparison circuit (1), arrange the comparison circuits (1) in the required number of stages.

Applying a divided voltage to each comparison circuit and converting the resulting output signal into a binary signal or the like using an encoder is similar to a bipolar parallel comparison type AD converter.

Problems to be Solved by the Invention However, in such a chopper-type comparator circuit using MO8 type transistors, a charging/discharging current flows into the stray capacitance of the capacitor (8) from the input terminal (2) side when switching the clock. spike-like noise appears in the input signal voltage. For example, when the sampling time becomes shorter, the spike-like noise continues to flow until the next sampling time.
There was a problem that this resulted in an error voltage of the input signal.

An object of the present invention is to provide an AD converter with less error by reducing spike-like noise during clock switching using a simple configuration.

Means for Solving the Problems The AD converter of the present invention connects a first switch between the input and output of the 1-inversion circuit, and connects the second switch between the analog input to be converted and the output of the comparison voltage generation circuit. A series circuit of a third switch is connected, and a first capacitor is interposed between the connection point of the second switch and the third switch and the input of the inverting circuit to configure each comparison circuit. , the first to third switches are opened and closed at regular intervals to take out the comparison result from the output of the inverting circuit, which is converted into a digital output via an encoder, and a second switch is connected between the analog input to be converted and the ground. It is characterized by having a capacitor inserted therein.

Since the second capacitor is interposed between the analog input to be converted and the ground, the spike-like charging/discharging current that flows to the stray capacitance of the first capacitor when switching the clock is absorbed by the second capacitor, and noise is added to the input signal. Overlapping can be reduced.

Example An embodiment of the present invention will be described below with reference to FIG.

Components having the same functions as those in FIG. 2 are given the same reference numerals and their explanations will be omitted.

FIG. 1 shows the AD converter of the present invention, in which the number of comparison circuits (1,) (1,) according to the resolution and the encoder (10
), and a capacitor (9) is formed between the input terminal (2) and ground on the chip of the comparison circuit (1□) (1□)... formed by C-MOS process. has been done.

In this way, the charging/discharging current from the capacitor (9) does not compensate for the charging/discharging current to the stray capacitance existing at both ends of the capacitor (8), and the influence of error voltage due to spike-like noise on the input signal is reduced. Become.

Therefore, even if the sampling frequency (clock frequency) of the AD converter is increased, AD conversion can be performed with higher accuracy.

Note that the capacitance value of the capacitor (9) must be selected such that its impedance is sufficiently high compared to the sampling frequency.

In addition, noise can be reduced by providing the capacitor (9) outside the chip of the comparison circuit (1), but noise can be reduced more reliably by providing the capacitor (9) on the same chip as in the above embodiment. can.

Effects of the Invention As described above, in the AD converter of the present invention, the first switch is connected between the input and output of the inversion circuit, and the second and second switches are connected between the analog input to be converted and the output of the comparison voltage generation circuit. A series circuit of three switches is connected, and a first switch is connected between the connection point of the second switch and the third switch and the input of the inverting circuit.
A capacitor is inserted to configure each comparison circuit, and the first to third switches are opened and closed at a constant clock cycle to extract the comparison result from the output of the inverting circuit, and the result is digitalized via an encoder. In addition to the conversion output, a second capacitor is inserted between the analog input to be converted and the ground, which eliminates spike-like noise caused by charging and discharging current flowing through the stray capacitance of the first capacitor when switching tack. This can be absorbed by the second capacitor, which greatly helps improve the sampling frequency.

Furthermore, if the comparison circuit is integrated and the second capacitor is formed on the same chip as the comparison circuit, a more reliable noise reduction effect can be expected, and if the second capacitor component is placed externally, The number of parts can be reduced in comparison.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the AD converter of the present invention,
FIG. 2 is a configuration diagram of a comparison circuit of a conventional AD converter. (1,) (1□)... Comparison circuit, (2)...
Input terminal, (3)... Inverting circuit, (4)... First switch, (51) (5□)... Voltage divider, (6
)...Second switch, (7)...Third switch, (8)...Capacitor [first capacitor], (9
)...Capacitor [second capacitor], (10)
...Encoder agent Yoshihiro Morimoto/

Claims (1)

[Claims] 1. A first switch is connected between the input and output of the inversion circuit, and a series circuit of second and third switches is connected between the analog input to be converted and the output of the comparison voltage generation circuit. are connected, and a first capacitor is interposed between the connection point of the second switch and the third switch and the input of the inverting circuit to configure each comparison circuit, and the first to third The AD converter opens and closes a switch at regular intervals to take out the comparison result from the output of the inverting circuit, converts it into a digital exchange output via an encoder, and interposes a second capacitor between the analog input to be converted and ground. converter. 2. The AD converter according to claim 1, wherein the comparison circuit is integrated and the second capacitor is formed on the same chip as the comparison circuit.