JPS6120893B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an advance control unit with a base register and an index register for address expansion,
The present invention relates to an information processing device capable of pipeline processing of instructions.

Conventionally, in this type of information processing device, inter-register transfer instructions have been executed in the arithmetic control unit like a general arithmetic control unit, so the timing at which the result of the operation is finalized in the base register or index register depends on the addition or This had to be delayed to the same timing as instructions such as subtraction. Therefore, if there is a transfer to the base register and index register that should be used for the address expansion of the preceding instruction, there is a drawback that the address expansion of the preceding instruction always has to wait until the transfer is completed. .

It is an object of the present invention to eliminate the drawbacks of the prior art by executing an inter-register transfer instruction in a pre-control unit in advance of an arithmetic control unit and to accelerate the determination of registers in the pre-control unit. An object of the present invention is to provide an information processing device that can eliminate the need for queuing for address expansion of a command following a command.

According to the present invention, in an information processing apparatus that performs pipeline processing of instructions and includes a base register group for address expansion and an index register group, an inter-register transfer instruction detection circuit and a transfer source of the inter-register transfer instruction are provided. A match detection circuit between the register number and the register number waiting for register confirmation before the transfer instruction, and instructions from both detection circuits, determine whether advance processing of inter-register transfer can be performed. control means for instructing the transfer, thereby speeding up the determination of the address development base register group and the index register group in the case of an inter-register transfer instruction prior to execution in the arithmetic control unit. An information processing device having a proactive control function is obtained.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an advance control section constituting an embodiment of the present invention. In this advance control section,
The instruction code portion of the instruction register 1 that holds the prefetched instruction is passed to the inter-register transfer instruction detection circuit 3 via the line 2, and when the detection circuit 3 determines that it is an inter-register transfer instruction, the instruction code portion is passed to the inter-register transfer instruction detection circuit 3 via the line 2. 4, the inter-register transfer control circuit 5 is notified. Further, the portion displaying the transfer source register number of the instruction register 1 is connected to a match detection circuit 7 between the transfer source register number and the finalized register number via the line 6.
and is sent to the register confirmation wait control circuit 8, the read address section of the base register group 9, and the read address section of the index register group 10.
Further, the portion of the instruction register 1 that displays the transfer source register number is connected to the register confirmation wait control circuit 8, the write address portion of the base register group 9, and the write address portion of the index register group 10 through a line 11. sent to. Further, the register number that requires a definite wait is notified from the definite wait control circuit 8 to the coincidence detection circuit 7 through the line 12, and
Address expansion is activated from line 13 to address expansion control circuit 14 . The register transfer control circuit 5 issues a registration inhibition instruction to the confirmation waiting control circuit 8 via a line 15, and an instruction to transfer between registers in the base register group 9 or index register group 10 via a line 16. In this transfer between registers, when the selection circuit 19 receives register read data from lines 17 and 18, the transfer source register side is selected, and the data is transferred to the base register group 9 (hereinafter abbreviated as BR) or the index via line 20. This is achieved by writing the corresponding data to the Tx register group 10 (hereinafter abbreviated as IR). Note that the base register group 9 and index register group 10 in FIG. 1 are commonly used in the advance control section and the arithmetic control section, as will be described later.

The execution of an instruction program as shown in Fig. 2 will be explained below with reference to the time chart shown in Fig. 3, taking as an example the case where basic instructions (addition/subtraction instructions, transfer instructions, etc.) are realized in two machine cycles. do. In FIG. 2, program example 1 shows a case where there is no confirmation of the transfer source register number IR3 of the transfer instruction immediately before the inter-register transfer instruction, and program example 2 shows the case where the transfer source register number IR3 of the transfer instruction is not waited for immediately before the inter-register transfer instruction. This shows the case where there is a waiting list for number IR1.

First, in the case of program example 1, the instruction shown in FIG. 1 is stored in instruction register 1 at timing A.
When confirmed, pipeline processing is started, and an instruction to start the calculation operation is given to the calculation control unit.
The register number in instruction register 1 is sent out.
At timing B, reading of IR1 and IR2 is performed in the arithmetic control section, and at timing C, each read data is read out from the arithmetic registers R1 and R2.
(not shown in the figure). Then, at timing D, the result of the operation is held in the operation result register, and at timing E, IR1 is determined and the instruction ends. In parallel, in the advance control section,
At timing B, a report is sent to the register confirmation wait control circuit 8 that advance processing using IR1 cannot be performed until IR1 is updated by the instruction. After receiving the report, the fixed waiting control circuit 8 registers the fixed waiting register number IR1 at timing C, and at timing D.
Retained until IR1 is updated.

However, IR1 is required for preprocessing of the instruction following the instruction.
is unnecessary, so the preceding processing proceeds as follows.
The advance control unit learns from the output of the detection circuit 3 at timing C that the instruction is an inter-register transfer instruction, and detects the mismatch output (IR1≠IR3 ), the inter-register transfer control circuit 5 operates. This control output reads IR3 from IR group 10 (the read address has already been given by line 6). Selection circuit 19
The result of selecting the line 18 side is that through line 20
A write instruction is given to BR1 of BR group 9 (the write address has already been given through line 11), and registration of waiting for BR1 confirmation at timing E is suppressed. Therefore, BR1 in the advance control unit is determined at timing D by the inter-register transfer instruction.
BR1 confirmation of the instruction result in the arithmetic control section is as follows:
This is done at timing G by pipeline processing similar to the instruction, but since the instruction is an inter-register transfer instruction, there is no need to register BR1 to be confirmed at timing E. And BR1 for instruction address expansion
At the required timing E, BR1 has already been determined to be in the BR group in the advance control unit, and therefore, the pipeline processing of the instruction can proceed without waiting, and the address expansion control circuit 14 is activated. do.

In the case of program example 2, the waiting register number match detection circuit 7 at timing C matches (IR1
=IR1) output, and the process is the same as in program example 1, except that the preceding processing of the instruction is delayed until a mismatch output occurs at timing E.

According to the above program example, it can be seen that the waiting time for establishing a register for address expansion of an instruction following a conventional register-to-register transfer instruction is reduced by two machine cycles.

As is clear from the above description, according to the present invention, it is possible to quickly determine the address expansion base register group and index register group in an inter-register transfer instruction prior to execution in the arithmetic control unit. Therefore, the effect of improving processing performance is significant in that there is no need to wait for address expansion processing immediately after an inter-register transfer instruction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a preceding control unit constituting an embodiment of the present invention, FIG. 2 is a block diagram of two program examples for explaining the operation of the embodiment in FIG. 1, and FIG. This is a time chart explaining the operation for executing the program. In the figure, 1 is an instruction register, 3 is an inter-register transfer instruction detection circuit, 5 is an inter-register transfer control circuit, 7 is a coincidence detection circuit, 8 is a register confirmation wait control circuit, 9 is a base register group, and 10 is an index register. group 14 is an address expansion control circuit;
19 is a selection circuit.

Claims (1)

[Scope of Claims] 1. An information processing device that performs instruction pipeline processing and includes a preceding control section, an arithmetic control section, and a base register group for address expansion and an index register group shared by these control sections. Transfer means for transferring data between the registers at high speed without going through the arithmetic control unit; an inter-register transfer instruction detection circuit; and a transfer source register number of the inter-register transfer instruction and confirmation of the register before the transfer instruction. A matching detection circuit with the waiting register number and instructions from both of the detection circuits determine whether advance processing of the inter-register transfer instruction is possible, and if advance execution of the inter-register transfer instruction is possible, the transfer destination register number of the transfer instruction is determined. the preceding control section having a control means for suppressing the registration of the data into a register waiting for confirmation and for causing the transfer means to transfer data, An information processing device having a advance control function, characterized in that by executing the transfer instruction in a advance control unit, the execution timing of an instruction subsequent to the transfer instruction can be brought forward.