JPS61198746A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a minute element isolating region in a short time, by forming may elements on the surface of a semiconductor substrate, projecting electron beams on the substrate region between the elements, and forming the highly resistive element isolating region. CONSTITUTION:On the surface of a P-type Si substrate 1, gate oxide films 2, gate electrodes 3 and N<+> type source and drain regions 5 are formed, and MOS transistor Trs are formed. Then, interlayer insulating films 6 and wirings 7 are formed. Thereafter, electron beams are selectively projected on the substrate 1 between the MOS Trs under the condition of a dose amount of 1X10<15>cm<-2> or more. As a result, in the region, where the electron beams are projected, a highly resistive element isolating region 8 is formed. In this method, a minute element isolating region, having the size approximately close to the size of a mask can be formed. Since the resistance value does not become so large in the dose amount of the electron beams of less than 1X10<15>cm<-2>, the region cannot be utilized as the element isolating region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to improvements in element isolation technology.

[Technical background of the invention and its problems]

Conventionally, as an element isolation technology for semiconductor devices, for example, PN
Junction separation techniques are known. However, since this PN junction isolation technique uses impurity diffusion, there is a problem that the width of the element isolation region increases.

In addition, selective oxidation technology is also known, but due to the occurrence of so-called bird's beak, etc. It is difficult to form a 111I element isolation region.

Furthermore, in recent years, trench isolation, in which a trench is formed in a semiconductor substrate and an insulator is buried in the trench, has also been practiced. Although this method allows the formation of fine element isolation regions, there is a problem in that it takes a long time to process the grooves and bury the insulator or the like in the grooves.

(Object of the Invention) The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can easily form a fine element isolation region.

(Summary of the Invention) The method for manufacturing a semiconductor device of the present invention includes forming a large number of elements on the surface of a semiconductor substrate, and then selectively irradiating the substrate region between the elements with an electron beam at a dose of 1×10 cm or more. This structure is characterized by forming a high-resistance element isolation region.

In other words, when an electron beam is irradiated onto a substrate region between elements, the crystal structure of the silicon substrate in that region is disturbed, resulting in a high resistance region similar to that of an insulator, which makes it impossible to use that region as an element isolation region. can. In the present invention, the reason why the dose of the electron beam is set to 1×10 15 IJ4 or more is as follows. In other words, the dose of the electron beam irradiated onto silicon and the resistance value of the area irradiated with the electron beam have a relationship as shown in Figure 2, and the resistance value is not so large when the dose is less than 1X101S゛2. This is because the region cannot be used as an element isolation region even if it is irradiated with an electron beam. However, when the region that has become highly resistive due to electron beam irradiation is subjected to a thermal process, the disorder of the crystal structure is gradually alleviated. The region forming process needs to be performed after the element forming process. According to such a method, a fine element isolation region can be formed in a short time.

[Embodiments of the Invention] Hereinafter, embodiments in which the present invention is applied to manufacturing a MOS type semiconductor device will be described with reference to FIGS. 1(a) to 1(C).

First, a gate oxide film 2 is formed on the surface of a P-type silicon substrate 1, and then an impurity-doped polycrystalline silicon film is deposited on the entire surface and patterned to form electrodes 1 to 3 (as shown in FIG. 1(a)). . Next, after forming a resist pattern (not shown) covering the element isolation region, ions of, for example, arsenic are implanted using this resist pattern and the gate electrode 3 as masks, and annealing is performed to form N+ type source and drain regions 4.5. Then, a MOS transistor is formed (as shown in FIG. 3(b)). Next, after removing the resist pattern, an interlayer insulating film 6 is formed, a contact hole is formed, and then, for example, a 2-layer film is deposited on the entire surface and patterned to form a wiring 7. After that, an electron beam is selectively applied to the substrate 1 between the MOS transistors with an acceleration energy of 2
More than MeV, dose 11X1015c! Irradiate under conditions of R4 or higher.

As a result, the area irradiated with the electron beam has a sheet resistance of 10
An element isolation region 8 having a high resistance of 000 Ω/region or more is formed (as shown in FIG. 3(C)).

According to such a method, depending on the method of converging the electron beam or the degree of spreading due to diffraction of the electron beam, extremely fine element isolation regions 8 with dimensions close to those of the mask can be formed.
can be formed.

Additionally, the time required to form the element isolation region 8 also depends on the equipment used, but with the Pandegraaf type, the dose amount can be reduced to approximately 1×1015 CI114 with an irradiation time of about 10 minutes, which makes the manufacturing time extremely short. It can be done.

In the above embodiments, the method of the present invention is applied to the manufacture of MOS type semiconductor devices, but it goes without saying that it can be similarly applied to the manufacture of MOS type semiconductor devices such as bipolar type semiconductor devices.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, it is possible to form a fine element isolation region in a short time, and as a result, it is possible to achieve remarkable effects such as miniaturization of semiconductor devices.

[Brief explanation of drawings]

FIGS. 1(a) to (C) show MOS in the embodiment of the present invention.
FIG. 2 is a diagram showing the relationship between the dose of the electron beam and the resistance value of the region irradiated with the electron beam. 1...P-type silicon substrate, 2...gate oxide film, 3
... Gate electrode, 4.5... N+ type source, drain region, 6... Interlayer insulating film, 7... Wiring, 8...
Element isolation area. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 F゛-Z゛do (Cm-2)

Claims (1)

[Claims] After forming a large number of elements on the surface of a semiconductor substrate, an electron beam is selectively irradiated onto the substrate region between the elements at a dose of 1×10^1^5 cm^-^2 (or more). A method of manufacturing a semiconductor device, comprising forming a high-resistance element isolation region.