JPS6118021A - Data processor - Google Patents

Abstract

PURPOSE:To prevent a data error due to an abnormal oscillation produced immediately after the start of oscillation, by forming an action clock with a delay of a prescribed time for a data processing system which is capable of intermittent actions. CONSTITUTION:A clock producing circuit 4 to which the output of an oscillation circuit 3 containing an oscillator 7b produces an action clock of a system. A latch circuit 8 latches a halt instruction and stops the oscillation of the circuit 3 to interrupt the working of the system. Then a start signal A is delivered from a counter 6 for restart of the system. Thus the circuit 3 starts oscillations. While the signal A outputted from the counter 6 is applied to the circuit 4 via a delay circuit 9 for control of the working of the circuit 4. Therefore the system action clock is produced from the circuit 4 when a fixed period of time passed after the start of oscillation of the oscillator 7b. This prevents a data error due to an abnormal oscillation produced immediately after the start of oscillation.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data processing technique and a technique particularly effective when applied to oscillation stop processing in a data processing device.
For example, the present invention relates to a technique that is effective when used in a microcomputer system having a mode for stopping primary oscillation in order to reduce power consumption.

[Background Art j] In computers using microcomputers and ICs, an oscillation circuit using an oscillator such as a crystal oscillator is provided in order to generate an operating clock signal for the system. In such a data processing system, for example, when the system operates intermittently, power consumption can be reduced by stopping the primary oscillation and temporarily stopping the state of the microprocessor, memory, etc. .

Therefore, some devices have a halt function that stops the system by stopping the clock in response to an external signal or a command from the CPU (for example, Hitachi 4, which was published by Hitachi, Ltd. in September 1980 Bit 1 chip microcomputer system, HMC840 series,
LCD-IV [(See pages 29 and 37 of the D6139001 user's manual).

In a microcomputer system having such a halt function, the operation of the system is restarted by an interrupt from a timer or the like.

However, in a system that has an oscillation circuit using an oscillator, the period from when oscillation starts due to power supply when restarting the system until a predetermined time elapses;
The oscillation operation of the oscillator becomes unstable, and abnormal oscillation may occur at a very high frequency.

In particular, ceramic resonators, which are cheaper than crystal resonators, are sometimes used as resonators these days, but ceramic resonators have higher impedance than crystal resonators, so they are unstable immediately after oscillation starts. It takes longer.

When an original oscillation signal with such an abnormal frequency is supplied to the system, an erroneous write control signal is generated and applied to a RAM (random access memory) etc. that holds the necessary data, causing the data to be lost. There is a risk that it may be destroyed.

[Object of the Invention] The object of the present invention is to reduce power consumption in a data processing system that can operate intermittently and has a mode in which the oscillation of an oscillator is stopped. The object of the present invention is to prevent data errors that would destroy data being stored, thereby ensuring stable intermittent operation of the system.

Another object of the present invention is to enable inexpensive construction of a data processing system having a mode in which oscillation of one oscillator is stopped.

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, in addition to an oscillation circuit that includes an oscillator that oscillates at a high frequency to generate a reference signal that forms the system's operating clock signal, an oscillator circuit that includes an oscillator that oscillates at a low frequency is provided to control system operation. When stopped, the operation of the high frequency oscillator is stopped to reduce power consumption, and the oscillation signal from the low frequency oscillator is divided to operate a timer, and the output from this timer is used to control the system. An interrupt signal for restarting the operation is formed to start oscillation of a high frequency oscillator, and a delay circuit is provided to delay this interrupt signal, and the delayed signal is used as the operating clock signal of the system. The system operation clock signal is supplied to the forming circuit and its operation is controlled so that the system operating clock signal is formed after a certain period of time has elapsed after the oscillator starts oscillating. This achieves the above objective of preventing data errors caused by.

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to a 4-bit single-chip microcomputer (hereinafter referred to as a single-chip microcomputer).

In the figure, each circuit block surrounded by a chain line A is formed on a single semiconductor substrate such as single crystal silicon.

The single-chip microcomputer MPU includes a microprocessor 1 that controls each part of the system according to programs stored in an internal ROM (read-only memory), and a microprocessor 1 that controls each part of the system according to a program stored in an internal ROM (read-only memory). RAM (memory that can be read and written at any time) 2, a first oscillation circuit 3 that generates a clock that serves as a reference for the system operating clock signal, and a system based on the clock supplied from the first oscillation circuit 3. A clock pulse generator 4 that forms various internal clock pulses, a second oscillation circuit 5 that forms a reference clock for realizing the clock function built into the system, and a clock supplied from this oscillation circuit 5. It is composed of a counter 6 and the like that counts and forms a timer interrupt signal.

The microprocessor 1 also includes, but is not limited to, a ROM in which a program is stored, a program counter into which the address of the next instruction to be read is loaded, and an R
An instruction decoder that decodes instruction codes read from the OM to form internal control signals, registers such as accumulators and address registers, ALU (arithmetic logic unit) and I1 that perform arithmetic operations and logical operations.
It consists of 0 boats, etc.

In this embodiment, although not particularly limited, in order to realize an accurate clock function, an oscillator 7a of 32 kHz (32.768 kHz to be exact) is used as an oscillator 7a externally attached to the chip to configure the second oscillation circuit 5. A crystal resonator that oscillates at a relatively low frequency is used, and a clock for a watch is obtained by frequency-dividing this 32 kHz original oscillation signal by a counter 6.

On the other hand, a ceramic resonator that oscillates at a high frequency such as 400 kHz is used as the oscillator 7b constituting the first oscillation circuit 3 that mainly generates a reference clock for forming the operating clock signal of the system. has been done. As a result, a system clock signal with a higher frequency than the clock is generated, enabling high-speed operation of microprocessors and the like.

For example, when the system is to be operated intermittently, the microprocessor 1 is configured to be able to stop the oscillation operation of the first oscillation circuit 3 by a program by executing a halt command. For this purpose, a latch circuit 8 is provided to latch the halt command output from the microprocessor 1.

When this latch circuit 8 latches the halt command, it cuts off the voltage supply to the oscillator 7b to stop the oscillation, and after stopping the oscillation, it immediately supplies the voltage to the oscillator 7b by the timer interrupt signal supplied from the counter 6. The voltage is applied to start oscillation.

In this embodiment, the timer interrupt signal output from the counter 6 is used to detect the unstable period of the oscillator 7b when the stopped first oscillation circuit 3 is restarted by the timer interrupt signal. A delay circuit 9 is provided to delay the process by a sufficient amount of time.

This delay circuit 9 receives, for example, a starting clock signal A supplied from the counter 6 to the latch circuit 8, and signals B and C at the previous stage having a higher frequency than this starting clock signal A, as shown in FIG. , and an AND gate circuit that takes a logical product between the outputs A, B, and C of the AND gate and the clock signal A, and the like. As a result, the second
As shown in the figure, a delayed signal E delayed by one cycle from the first rise of the starting clock signal A is output.

This delayed signal E is applied to the clock pulse generator 4.
By being supplied to and operated by the system, a clock pulse is formed as an operating clock signal to be supplied to each part in the system.

Therefore, according to this embodiment, when the microprocessor 1 enters the hibernation state, the first
The oscillation operation of the oscillation circuit 3 is stopped. by this,
The supply of clock pulses to each part of the system is interrupted, and the operation of the circuits except the timer circuit (second oscillation circuit 5 and counter 6) is stopped. By the way, when each of the circuit blocks described above is constituted by an 0MO8 (complementary MO8FET) circuit, the current consumption thereof is proportional to the operating frequency. However, since the circuit portions other than the timer circuit are operated by clock pulses having a higher frequency than the timer circuit, the power consumption of the entire system is significantly reduced by stopping the clock pulses. Specifically, the current consumption in the timer circuit section is about 2 μA, while the current consumption in the first oscillation circuit 3 and the circuit section operated by clock pulses is about 1 mA. This makes it possible to significantly reduce power consumption.

Furthermore, in the above embodiment, when the timer circuit (counter 6) outputs the starting clock signal A to restart the system, the first oscillation circuit 3 is immediately activated and the oscillation signal is sent to the clock pulse generator. However, the clock pulse generator 4 is operated by a delay signal E that is generated with a delay of one cycle of the starting clock signal. Therefore, after the unstable period immediately after the oscillation of the oscillator 7b starts, clock pulses are formed and supplied to each part.

As a result, in a system that has an oscillation stop mode to reduce power consumption, an abnormal oscillation signal immediately after the oscillator starts oscillating can cause a write control signal to be erroneously supplied to a RAM, etc., causing internal data to be destroyed. Accidents such as accidents can be prevented.

In the above embodiment, the delay circuit 9 is constituted by a gate circuit whose input signal is the clock supplied from the timer circuit (counter 6).

Examples include, but are not limited to, a time constant circuit that slows the rise of the start signal supplied from a timer circuit, and a Schmitt circuit with a high logic threshold voltage that uses the output of this time constant circuit as an input signal. The delayed signal may be formed by

Further, in the above embodiment, a halt state is generated by a program to stop oscillation and system operation, but a dedicated terminal for inputting a halt request signal supplied from the outside is provided on the chip, and this external terminal The configuration may also be such that oscillation and system operation can be stopped by a halt request signal to.

Furthermore, the timer interrupt signal for canceling the halt state and activating the system can also be configured to be supplied from the outside instead of being generated by the internal timer circuit.

[Effects] (1) In addition to an oscillation circuit that includes an oscillator that oscillates at a high frequency to generate a reference signal that forms the operating clock signal of the system, an oscillation circuit that includes an oscillator that oscillates at a low frequency is provided. When the system stops operating, the oscillation of the high-frequency oscillator is stopped to reduce power consumption, and the oscillator is immediately activated by an interrupt signal that restarts system operation, and this interrupt signal is A delay circuit is provided, and the delayed signal is supplied to the circuit that forms the operating clock signal (clock pulse generator) to control its operation. After that, the system's operating clock signal is formed.

This has the effect of preventing data errors due to abnormal oscillation immediately after the oscillator starts oscillating, and ensuring stable intermittent operation of the system.

(2) In addition to an oscillation circuit that includes an oscillator that oscillates at a high frequency to generate a reference signal that forms the system's operating clock signal, it also includes an oscillator that oscillates at a low frequency to generate a watch clock. Since an oscillation circuit is provided and the oscillation of the high frequency oscillator is stopped when the system stops operating, an inexpensive ceramic resonator can be used as the oscillator that oscillates at a high frequency. This has the advantage that a data processing system that has an oscillation stop mode and is capable of intermittent operation can be constructed at low cost.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the delay circuit that delays the signal for activating the oscillation circuit that is stopped in the halt state and supplies the delayed signal to the clock pulse generator is not limited to the configuration of the embodiment described above, and various modifications are possible.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a 4-bit single-chip microcontroller, which is the field of application that formed the background of the invention, but is not limited thereto. It can be used in all systems that have a stop mode and are designed to perform intermittent operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing device according to the present invention, and FIG. 2 is a waveform diagram showing an example of a method of forming a signal by the delay circuit. ■・・・Microprocessor, 2・・・RAM (
random access memory), 3...first oscillation circuit, 4...clock formation circuit (clock pulse generator), 5...second oscillation circuit, 6...counter, 7a , 7b... Oscillator (crystal oscillator, ceramic oscillator), 8... Latch circuit. 9...Delay circuit.

Claims (3)

[Claims] 1. a control unit that generates a control signal to control the system;
In a data processing system that is equipped with memory that holds data necessary for system operation and is capable of intermittent operation,
A first oscillation circuit includes an oscillator that oscillates at a high frequency to generate a reference signal that forms a system operation control signal, and a second oscillator includes an oscillator that oscillates at a low frequency to generate a clock for intermittent operation. a signal forming circuit for forming a system operation control signal based on the oscillation signal from the first oscillating circuit; a delay circuit that delays the activation signal, the activation signal causes the first oscillation circuit to operate immediately, and the signal delayed by the delay circuit causes the signal to be formed later than the activation signal. A data processing device characterized in that the circuit is operated. 2. A patent claim characterized in that the activation signal is formed by a timer circuit that counts the intermittent operation clock supplied from the second oscillation circuit and outputs an appropriate signal at predetermined intervals. The data processing device according to item 1. 3. The oscillator constituting the first oscillation circuit is a ceramic resonator, and the oscillator constituting the second oscillation circuit is a crystal resonator. The data processing device according to item 2.