JPS61170027A - Manufacture of group iii-v semiconductor device - Google Patents

Abstract

PURPOSE:To realize the extremely thin active layer having a high activation rate, a high mobility, a deep level, and a low concentration by implanting an inert gas after covering the surface of a semiconductor substrate with specified silicon oxide film (SiNx) during the process of ion implantation of N-type impurity. CONSTITUTION:An SiNx film 2 of 50nm thick having an N composition of 2/3 is spread over a semi-insulating GaAs substrate 1 and further a CVD SiO2 film 3 is deposited on that to 200nm. Only the SiO2 film 3 of the region for forming a device is removed selectively, after which Ar ions 10 is implanted into the overall surface to 1.2X10<13>cm<-2> by 40 keV. Consequently the Si atoms only in the device forming region are recoil-implanted to form an active layer 4. Then it is possible to realize the thickness of an active layer of 30nm which is extremely thin.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a ■-v group semiconductor device using an ion implantation method.

(Prior art and its problems) In recent years, with the aim of increasing the speed of semiconductor integrated circuits, GaA, which uses gallium arsenide (abbreviated as GaAs) semiconductor in the active layer, has been developed.
s Integrated circuits are being actively developed. Field effect transistors are generally used as the basic elements of GaAs integrated circuits, and ion implantation is widely used as a method for forming such elements from the viewpoints of uniformity, controllability, and mass production.

In the recent development of integrated circuits, it has become essential to increase the mutual conductance (gm) of field effect transistors in order to increase the speed of the circuits. ! it
Although n can be increased by increasing the carrier concentration of the active layer, increasing the carrier concentration simultaneously causes a shift of the threshold voltage of the field effect transistor to the negative side. Therefore, in order to increase 9m while keeping the threshold voltage constant, it is necessary to form a shallow active layer with high carrier concentration.

Two methods have been reported to date for forming a shallow active layer with high carrier concentration.

In Proceedings of the 31st Annual Conference of the Japan Society of Applied Physics, Spring 1980, page 535, Sano et al. reported that the implantation energy of Sl ions was increased from the conventional 60 keV to 20 keV, as shown in Figure 4.
A shallow operating layer is obtained by reducing the This method reduces the projected range of implanted ions by reducing the acceleration energy. This method has the advantage of a simple process, but since the acceleration energy value of 20 keV corresponds to the lowest energy value that can be obtained with current ion implanters, the acceleration energy will be lowered further in the future to obtain an even shallower active layer. is difficult. In addition, in this method, since the implanted impurity distribution has a nearly Gaussian distribution, a low carrier concentration region exists on the surface side of the active layer, and therefore a remarkable photoresponse occurs in this region.
It has the disadvantage that strong hysteresis tends to occur in transistor characteristics due to the influence of deep units.

Another method for forming a shallow active layer is the through injection method, which is reported by Onomae et al. in Proceedings of the 30th Japan Society of Applied Physics, Spring 1980, page 461. FIG. 5 shows a comparison of the implanted ion concentration distributions of an active layer formed by through implantation and an active layer formed by direct ion implantation. As shown in the figure, in through implantation, the depth of the ion concentration distribution becomes shallower by the thickness of the implanted into the insulating film provided on the substrate surface. In this case, since the thickness of the insulating film is usually set near the projected range of the implanted ions, half of the total number of implanted ions are implanted into the insulating film and the other half into the semiconductor substrate. The thickness of the active layer obtained by direct ion implantation is expressed as approximately 2R, where RP is the projected range of ions, so the thickness of the active layer in the case of the above-mentioned through implantation is approximately R. From this, in order to form an active layer with a thickness of BP, it is necessary to set the thickness of the insulating film according to the formula, and the controllability and uniformity of the active layer thickness depends on the controllability of the thickness of the deposited insulating film. , highly dependent on uniformity. The CVD method and sputtering method are used to form insulating films, but today the minimum film thickness that can be obtained with good reproducibility and uniformity using these methods is about 50 nm, and film thicknesses thinner than this value are In this case, the controllability of the film thickness and the uniformity within the wafer are significantly reduced. Therefore, the minimum value of the active layer thickness that can be obtained with good controllability by the through injection method is also 50
It remains at about nm. As mentioned above, the first method using low-energy implantation requires a minimum operating layer thickness due to the structure of the ion implanter, and the second method using through implantation requires a minimum operating layer thickness due to limitations on the thickness of the insulating film to be deposited. is limited, and it is difficult to realize even thinner active layer thicknesses (eg, 20-30 nm).

In contrast to the two conventional methods listed above, the recoil injection method can be considered as a method that can realize an even thinner active layer thickness. This is 1. This method utilizes ion implantation using recoil atoms that occur when ions are implanted into a target material made of a multilayer film. As an example, consider the case where argon (Ar) ions are implanted into a two-layer structure of silicon nitride film/GaAs, and silicon (8i) atoms generated by nuclear collision with human r ions are recoil-injected into GaAs.

In addition to silicon nitride film (83Nx), silicon oxide film (8i0
t) and an amorphous silicon film (a-8i), but the latter two cannot be used for the following reasons. That is, 8i0. In the method using recoil S
In addition to a single atom, polycarboxylic coil oxygen atoms are introduced into GaAs to form a deep level, which traps free electrons generated from 8+ donors, thereby hindering effective carrier generation.

In addition, in the method using 1-84, after the beam coil is implanted, it cannot be selectively removed using hydrofluoric acid as in the case of a-8i, 8iNx, and 8i01 that are no longer used, so from the viewpoint of device manufacturing. As a result, its application range is largely limited.On the other hand, even when 81Nx is used as a recoil Si source, there are the following problems. Third
The figure shows the stoichiometry composition (i.e. 5tsNa
) was deposited on an insulating GaAs substrate.
After nm deposition, human r ions were exposed to IX at 40 keV.
This figure shows the atomic placement distribution of Sl and N that are recoil-injected into GaAs when implanted at 10''cm-1.

The moat distribution of recoil S1 atoms takes an excessive value on the surface of the GaAs substrate and decreases almost linearly with depth. The depth when the atomic concentration decreases by two orders of magnitude from the surface is about 30 a.
m, and an extremely thin active layer is formed. However, in the case of FIG. 3, the recoil N atomic concentration is two to three times higher than the beam coil 8i atomic concentration. W,
M. Duncan et al. Journal of Applied Physics (J8 pp1. Phys,) 198
In Year 4, Volume 56, Page 1059, nitrogen (5) is Ga
It has been reported that N implanted at the same time as 8i substantially reduces the activation rate of 8i ions and at the same time causes movement of the active layer. This may cause the condition to worsen. Therefore, when the n-type layer formed by the above method is used as the active layer of a field effect transistor, a low activation rate deteriorates the controllability of the threshold voltage of the field effect transistor, and a decrease in mobility deteriorates the transistor characteristics. In addition, the existence of deep levels causes photoresponse and hysteresis, so the advantages of a shallow active layer with high carrier concentration are not necessarily fully utilized (Objective of the invention) The purpose of the present invention is to improve the problems that occur when a shallow active layer is formed using the S + NX film as a recoil Si source, and to form an extremely thin active layer with high activation rate and mobility and low concentration of deep levels. The object of the present invention is to provide a method for realizing an active layer (for example 20-30 nm).

(Structure of the Invention) According to the present invention, in the step of ion-implanting a type 1 impurity into a -V group semiconductor single crystal substrate, the surface of the semiconductor substrate is covered with a silicon nitride film having a nitrogen to silicon composition ratio of less than 4/3. A method for manufacturing a (1)-V group semiconductor device is obtained, which is characterized in that after covering with (SiNx), ions of an inert gas are implanted.

(Detailed description of the structure) The present invention is characterized in that the injection amount and injection distribution of recoil 81 atoms and coil NU elements into GaAs, which are generated when an inert gas is ion-implanted into a two-layer structure of 8iNx/GaAs, are different from those of the SiNx film. This takes advantage of the fact that the N composition varies greatly depending on the N composition X. - The inert gas atoms introduced into G5As as secondary ions are electrically inactive and do not contribute to the generation of carriers. The ratio of the implanted amount of recoil-implanted N atoms and St atoms has a positive correlation with the N composition X of the surface film 3iNx. For example, when Ar ions are implanted into GaAs at 40 keV through a 50 nm 8iNx film, , the N composition X of the 8iNz film is reduced from 4/3 to 2
73, the ratio of recoil-implanted N atoms to 8i atoms in GaAs is reduced to about 1/3 of the original value, and 8iN is required to reduce the recoil N-atom implantation amount.

It can be seen that it is effective to reduce the N composition X of the film. However, since a decrease in the N composition X of the 8iNK film causes a decrease in the etching rate of the 8iNx film with hydrofluoric acid, the N composition X cannot be reduced unnecessarily if the 8iNx film needs to be removed in a later process. The etching rate for hydrofluoric acid is approximately 5 nm when the N composition X is 0.6.
/min, and in practice the lowest value of N composition X is 0.68.
(Examples) The present invention will be explained below using examples together with experimental facts. Figure 1 shows the surface orientation (100) L B C (Li q
u idBncapsulmted Cxochrs
lski) method undoped As substrate with N composition x = 2
The samples were deposited with 50 nm of SiNx film with 3/3 ions, followed by room temperature implantation of 5 X 10" ions at 40 keV, and then the surface 8iNx layer was removed using hydrofluoric acid. We show the results of measuring the atomic concentration distribution of recoil N atoms by secondary ion mass spectrometry (l] IM8). 5INxVIX was formed using the thermal decomposition CVD method of monosilane (8iH,) and ammonia (NHs). , N composition X can be reduced by decreasing the flow rate of NH, while keeping the flow rate of 81H constant.

As shown in FIG. 1, even when the N composition X is reduced to 2/3, the concentration distribution of recoil 8i atoms takes a maximum value at the surface of the GsAa substrate and decreases almost linearly with depth. Further, the depth when the atomic concentration is reduced by two orders of magnitude from the surface concentration is approximately 30 nrn, and an extremely thin active layer thickness is realized. Further lζ, the 8i atom concentration is higher than the N atom concentration over 15 am from the surface;
When using 5iNz with composition X of 4/3 (Figure 3)
It can be seen that the influence of the deep level caused by N atoms can be greatly reduced compared to the above. Next, in order to investigate the effectiveness of the ultra-thin active layer according to the present invention in device applications, a self-line field effect transistor using a W8ix gate was fabricated. The device manufacturing procedure is as shown in FIG.

First, a layer of N with a thickness of 50 nm was placed on a semi-insulating GaAs substrate 1.
A 5iNz film 2 having a composition of 2/3 is deposited over the entire surface, and a CVD 5tO film 3 is further deposited to a thickness of 200 nm thereon. (
FIG. 2(a)) Sio of the area where the device will be formed next
@llX3 only is selectively removed, and then human r ions 10 are implanted over the entire surface at 40 keV with 1.2XlO"Cl71". As a result, only 81
The active layer 4 is formed by recoil injection of atoms. (Fig. 2(b)) After Ar ion implantation, S i O! membrane 3
and 8iNx film 2 and newly annealed
CVD 5ioxN with refractive index 1.75 as k film
, deposit 90 nm of film 5. Operation +4 annealing is performed by infrared flood annealing at 950° C. for 4 seconds. (Fig. 2 ←)) After that, the anneal protection film is removed, and 500 nm of WSlx is deposited as a gate metal. 8F,
After forming a gate electrode 6 with a gate length of 1 μm by dry etching with gas (@2 (d)), St ions 11 were added as a layer for the source and drain regions at 100 keV l×10”CI+!- ``Inject n
+Contact layer 8 is formed. (Figure 2(e)) -
The layer is annealed at 900°C for 4 seconds using the same <5IOxN a protective film (Fig. 2(f)). Next, AuGe/Ni is used as the source and drain ohmic electrodes 9.
After an alloying process at 420° C., Ti/Au is deposited as a pad electrode to complete the device. (Figure 2 (g)) The threshold voltage of the obtained field effect transistor is approximately -0.3V, and the l1m value is 250 m8/a on average and 310 m8/a as the maximum value.
A high value of m was obtained, demonstrating the effectiveness of the present invention.

(Effects of the Invention) By using the method of the present invention, an extremely thin active layer thickness of 30 nm can be achieved, and a 300 ms
It becomes possible to fabricate a field effect transistor having a high pm of more than /ml. In addition, 8iN whose N composition is 2/3
8 by using hydrofluoric acid after use by using Z membrane.
The iNx film can be easily peeled off, and the influence of deep levels caused by recoil N atoms can be suppressed to obtain good transistor characteristics with little photoresponse and hysteresis.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the recoil atom concentration distribution according to the present invention,
Figures 2 (a) to (g) are cross-sectional views showing the implementation rows of the present invention in process order; Figure 3 is a diagram showing the glue coil atomic concentration distribution when recoil implantation is performed using an 8i1N4 film; Figure 4
This figure shows an ion implantation distribution according to a conventional example, and FIG. 5 is a diagram showing an ion implantation distribution according to another conventional example. 1... Semi-insulating GaAs substrate, 2 ・SiNX film (
x=2/3) 3...8i01 film, 4...
Operating layer 5...S i OxNyl odor, 6...
・Gate electrode 7...photoresist, 8...n
4 Contact layer 9...Ohmic polarization, 1o.
・・Iion 11...8i ion, Dai 7 Ben two master Susumu Uchihara 1st figure 0O11: Idensa (μ笥), 41! Z diagram Figure 2 Figure 3 Figure 0 0.1
5 children 2 Cpm) Fig. 4 5 light 2 (Mejo) Fig. 5 0 0, l 0.2 Ukasa (l 笥)

Claims (1)

[Claims] In the step of ion-implanting n-type impurities into a III-V group semiconductor single crystal substrate, the surface of the semiconductor substrate is covered with a silicon nitride film (SiN_
1. A method for manufacturing a III-V semiconductor device, which comprises covering the device with x) and then ion-implanting an inert gas.