JPS61162896A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain a sense amplifier circuit that reconciles high speed operation with noise proof property by combining and constituting MOSFETs. CONSTITUTION:Just before starting amplification, an MOSFET3 is cut off, and MOSFETs 4, 5 and 8, 9 become continuity, and consequently, MOSFETs 6, 7 are cut off. At the time of amplification, potential of a clock terminal 20 and a clock terminal 26 is changed, MOSFETs 4, 5 and 8, 9 are cut off, and the MOSFET3 is made continuity. During amplification, MOSFETs 6, 7 are kept cut off and do not give influences on amplification. Accordingly, potential difference which was in output terminals 17, 18 at first is amplified. As the value of resistance of resistances 13, 14 is large, only floating capacity of output terminals 17, 18 has connection during amplification in a short time. Accordingly, amplification at high speed can be made by making the floating capacity small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier circuit suitable for a memory circuit constituted by MISFETs.

[Prior art]

In a memory circuit using a MOS FET, a circuit based on a flip-flop circuit is usually used as a so-called sense amplifier circuit that amplifies a minute potential difference read from a memory cell. An example of such a circuit is shown in FIG. 2 (for example, Nikkei Electronics, January 8, 1979, pages 110-133).

In the sense amplifier circuit shown in FIG. 2, immediately before the amplification operation, the clock terminal 19 and the clock terminal 2
Due to the potential of clock 1 and clock 2 applied to MOSFET 0, MOSFET 3 is in a cut-off state and MO3F
ET4 and 5 are in a conductive state. Therefore input terminals 15 and 1
The potentials of input 1 and input 2 applied to output terminal 6 are transmitted to output terminals 17 and 18 as output 1 and output 2, respectively, and the stray capacitances present at output terminals 17 and 18 are charged to the input potential.

During amplification, first, the potential of the clock terminal 20 is changed to cut off the MO3FETs 4 and 5. Next, the potential of the clock terminal 19 is changed to make the MO3FET 3 conductive. As a result, MISFET I and 2 form a flip-flop circuit, and due to positive feedback, output terminals 17 and 1
Immediately before the amplification operation is performed, the terminal near the potential VSS of the power supply 21 is discharged to the potential VSS, and the potential of the other output terminal remains almost unchanged. The difference in potential between the output terminals 17 and 18 is amplified and obtained at output terminals 17 and 18.

[Problems with conventional technology]

In the amplification operation of the sense amplifier circuit described above, since the output terminals 17 and 18 are charged with stray capacitance, a change in potential cannot occur rapidly and takes a certain amount of time. Therefore, if the potential at the connection point 22 is suddenly changed, MO3F
Both ETI and 2 become conductive, and correct amplification operation cannot be expected. To explain this in detail, suppose that the potential applied to the input terminal 15 is higher than the potential applied to the input terminal 16 at the potential v of the power supply 21.
Suppose that it is close to s. In this state, MO3FET4 and 5
When the potential of the connection point 22 is gradually brought closer to VSS by cutting off MO3FET3 and making it conductive, MO3FETI becomes conductive first. As a result, even if the potential of the output terminal 17 approaches VSS and the potential of the connection point 22 approaches vSS, M
O5FET2 is kept in the cut-off state. In this way, only the potential of the output terminal 17 eventually reaches vSS. However, if the potential at the connection point 22 changes too rapidly and the change in the potential at the output terminal 17 cannot catch up, the M
The gate-source voltage of ISFET2 is also MO5FET2.
The voltage exceeds the dark value voltage and becomes conductive. Then, the potential of the output terminal 18 also changes toward VSS.

For this reason, correct amplification operation cannot be expected.

As explained above, in order for the sense amplifier circuit shown in FIG. 2 to operate correctly, the voltage waveform applied to the clock terminal 19 must be adjusted so that the potential at the connection point 22 changes sufficiently slowly.

Further, the potential at the output terminals 17 and 18 changes more slowly as the stray capacitance increases, so the potential at the connection point 22 must be changed more slowly.

Generally, it is desired that the time required for amplification be short, and for this purpose it is necessary to reduce the stray capacitance of the output terminals 17 and 18. However, in the holding state after amplification, if the stray capacitance of the output terminals 17 and 18 is too small, even a small amount of current noise added to these terminals will cause a large change in the potential of the terminals. As a result, the MO which was in the conductive state
If S F ETl becomes cut off, the held contents will be destroyed.

As described above, in conventional sense amplifier circuits, in order to speed up the amplification operation, the stray capacitance of the output terminal must be made small, but if it is made too small, the resistance to noise in the holding state is reduced. There was a problem that it could not be made very small because it would become weak, and therefore a sufficient increase in speed could not be achieved.

[Purpose of the invention]

In view of this point, it is an object of the present invention to provide a sense amplifier circuit that does not reduce its resistance to noise in the holding state even when the amplification operation is increased in speed.

[Structure of the invention]

The present invention has a first output terminal connected to a first input terminal via a first MISFET, and a second output terminal connected to a second input terminal via a first MISFET.
a second output terminal connected via a MISFET, a drain electrode connected to the first output terminal, a source electrode connected to the first power supply, and a gate electrode connected to the second output terminal. a third MISFET, a drain electrode connected to the second output terminal and a source electrode connected to the first
a flip-flop circuit having a fourth (7) MISFET connected to a power source and having a gate electrode connected to the first output terminal; In the sense amplifier circuit that outputs between the first and second output terminals, first and second load elements are respectively connected between the first and second output terminals and a second power supply. and a fifth MISFET whose drain electrode is connected to the drain electrode of the third MISFET, whose source electrode is connected to the source electrode of the third MISFET, and whose gate electrode is connected to a third power supply, and whose drain electrode is connected to the third MISFET. Said fourth MI
a sixth MISFET connected to the drain electrode of the SFET, a source electrode connected to the source electrode of the fourth MISFET, and a gate electrode connected to the third power supply; a third load terminal connected between the gate electrode of the MISFET; and a fourth load element connected between the first output terminal and the gate electrode of the sixth MrSFET, Immediately before amplification, the second power supply and the third power supply are turned on to charge the gate capacitances of the fifth and sixth MISFETs, and during amplification, the third power supply is turned off and the voltage is the same as that of the third power supply. The first power source that supplies voltage is turned on so that the fifth or sixth MISFET connected to the third or fourth (f7) MISFET that is in the conducting state of the flip-flop circuit in the holding state becomes in the conducting state. It is characterized by the fact that

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, elements having the same functions as those in FIG. 2 are labeled with the same numbers.

One MISFETI that constitutes a flip-flop circuit
The drain electrode of is connected to the output terminal 17, the gate electrode is connected to the output terminal 18, and the source electrode is connected to the connection point 22. The drain electrode of the other MISFET 2 constituting the flip-flop circuit is connected to the output terminal 18, the gate electrode is connected to the output terminal 17, and the source electrode is connected to the connection point 22. The connection point 22 is M
Connected to the drain electrode of O3FET3, MO3FET
The gate electrode of No. 3 is connected to the clock terminal 19, and the source electrode is connected to the power source 21. The output terminal 17 is the M.O.
Connected to the source electrode of S FET 4, MOS F
The drain electrode of ET 4 is connected to input terminal 15,
The gate electrode is connected to a clock terminal 20. The output terminal 18 is connected to the source electrode of MO3FET5,
The drain electrode of the MO3FET 5 is connected to the input terminal 16, and the gate electrode is connected to the clock terminal 20.

The above configuration is the same as that of the sense amplifier circuit shown in FIG. The sense amplifier circuit of this embodiment further includes the following circuit.

Between the output terminals 17 and 18 and the power supply 25, MISFETs II and 12, which function as two-terminal load elements, are connected with their source electrodes on the output terminal side and their drain electrodes on the power supply side, and the gate electrodes of these MOSFETs is power supply 25
are connected to each. The drain electrode of the MOS FET 6 is connected to the output terminal 17 , the source electrode is connected to the connection point 22 , and the gate electrode is connected to the connection point 23 .

The drain electrode of MOSFET 7 is connected to output terminal 18 , the source electrode is connected to connection point 22 , and the gate electrode is connected to connection point 24 . Output terminal 18 and connection point 2
A resistor 13 is connected between the output terminal 17 and the connection point 24, and a resistor 14, which functions as a two-terminal load element, is connected between the output terminal 17 and the connection point 23. is connected to the drain electrode of MOSFET8, and MOSFET8 is connected to the drain electrode of MOSFET8.
The source electrode of SFET 8 is connected to power supply 21, and the gate electrode is connected to clock terminal 26.

The connection point 24 is connected to the drain electrode of the MOSFET 9, the source electrode of the MOSFET 9 is connected to the power supply 21, and the gate electrode is connected to the clock terminal 26.

Next, the operation of this embodiment will be explained. Immediately before starting amplification, MOSFET 3 is cut off by the potentials of clock 1 and clock 2 applied to clock terminal 19 and clock terminal 20, and MOSFETs 4 and 5 are conductive. Furthermore, due to the potential of the clock 3 applied to the clock terminal 26, MOSFETs 8 and 9 are brought into conduction.
As a result, MO3FETs 6 and 7 are cut off. MOSF
ET6 and ET7 are large-area transistors, and because of their gate capacitances, the stray capacitances at connection points 23 and 24 are quite large, and therefore these stray capacitances are charged to the potential VSS of power supply 21. Works as a 2-terminal load element <MO3FETI
The resistance values of I, 12 and resistors 13, 14 are sufficiently high, and the potentials of output terminals 17 and 18 are approximately equal to the potentials of input terminals 15 and 16, respectively. If input cannot be applied to input terminals 15 and 16 with sufficiently low DC resistance as in the case of normal dynamic memory, MOS FET 4
and 5, and immediately before starting the amplification operation, MOSF
This condition can be satisfied by making ET4 and ET5 conductive.

During amplification operation, the potentials of the clock terminal 20 and the clock terminal 26 are changed to
SFET8 and 9 are cut off. After that, clock terminal 1
The potential of MOSFET 9 is changed to make MOSFET 3 conductive. As mentioned above, the MOSFETs 6 and 7 are large-area transistors, and because of their gate capacitances, the stray capacitances at the connection points 23 and 24 are quite large, and the resistance values of the resistors 13 and 14 are very large. Therefore, even if the potentials at the output terminals 17 and 18 change, the potential VSS at the connection points 23 and 24 is hardly affected in a short period of time. Therefore, during amplification operation, MOSFETs 6 and 7 remain cut off.
Does not affect amplification operation. Therefore, initially output terminal 17
The potential difference between and 18 is amplified in the same manner as in the sense amplifier circuit of FIG. During short-term amplification operation, since the resistance values of resistors 13 and 14 are large, the stray capacitance at connection points 23 and 24 has no effect, and during amplification operation, only the stray capacitance at output terminals 17 and 18 will be involved. Therefore, by reducing this stray capacitance, high-speed amplification operation can be performed. The potential of one output terminal after amplification is the potential VSS of the power supply 21, while the potential of the other output terminal is a constant potential determined by the load elements 11 and 12 in this embodiment.

As shown in FIG. 1, when enhancement type MO3FETs are used as these load elements, when the threshold voltage of MO3FET II and 12 is VT, the potential of the other output terminal becomes VDD - VT. However, VDD is the potential of the power supply 25.

In the holding state, for the sake of explanation, MOSFET1 is in a conductive state and MOSFET2 is in a cutoff state, and after amplification,
Assume that the potentials of the output terminals 17 and 18 become VSS and VD low VT, respectively. As mentioned above, since the potential of the connection points 23 and 24 is held at vSS by the stray capacitance, MOSFET 7 remains in the cut-off state, but the MOSFET 7 remains in the cut-off state.
In the SFET 6, current flows into the stray capacitance at the connection point 23 through the resistor 13, and after a sufficient period of time has passed, the current flows into the stray capacitance at the connection point 23.
The potential of M becomes VDD -VT, which is the same as that of the output terminal 18.
OSFET6 becomes conductive. When the potentials of the output terminals 17 and 18 are opposite, on the other hand, the MOSFET 6 remains cut off and the MOSFET 7 becomes conductive. In this state, output terminal 1
Even if the potential of 7 or 18 changes due to noise, the MOSFET
The state of the circuit does not change due to the actions of 6 and 7. for example,
If MO3FETI is in a conductive state and MOSFET2 is in a cutoff state, and the potential of the output terminal 17 rises due to noise, the gate-source voltage of the MOSFET 2 increases, and the potential of the output terminal 18 decreases. M
The gate-source voltage of O3FETI becomes smaller.

As mentioned above, since the MOS FET 6 is in a conductive state, the gate-source voltage of MO3FETI is prevented from falling below the threshold voltage of MO3FETI, and the MOS FET 6 is in a conductive state.
O3FETI will never be in a blocked state. Therefore, since the state of the circuit does not change, the held contents are not destroyed. Furthermore, the potentials at the connection points 24 and 23 are the potential VSS of the output terminal 17 and the potential VSS of the output terminal 18, respectively.
DD -VT, the large stray capacitance at the connection points 23 and 24 becomes effective, and the output terminals 17 and 18
Since changes in potential are suppressed even if current noise is added to the circuit, the influence on the circuit state is reduced, and the changed potentials of the output terminals 17 and 18 quickly return to their original potentials.

As explained above, according to the sense amplifier circuit of this embodiment, only the stray capacitance of the output terminals 17 and 18 is relevant during amplification operation, and high-speed operation can be achieved by reducing this stray capacitance. On the other hand, in the holding state, the large stray capacitances at the connection points 23 and 24 have an effect, making it resistant to noise.

In this embodiment, the source electrodes of the MOSFETs 8 and 9 are connected to the power supply 21, but they may be connected to the connection point 22. In this case, immediately before starting the amplification operation, MOSFET 3.8.9 is made conductive by the potential applied to the clock terminal 19 and the clock terminal 26,
The connection points 23 and 24 will be charged to the potential vSS of the power supply 21. The subsequent operations are similar to those in the previous embodiment,
A similar effect can be achieved.

Although the above embodiments have been described using MOSFETs as MISFETs, it goes without saying that other MISFETs can also be used.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a sense amplifier circuit that is compatible with high-speed operation and noise resistance and is suitable for use in MIS integrated circuits such as dynamic memories.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional sense amplifier circuit. 1.2.3.4.5,6,7.8,9,11゜12...
... MOSFET 13.14 ... Resistor 15.16 ... Input terminal 17.18 ... Output terminal 19.20.26 • Clock terminal 21.25 ... Power supply Figure 1 70・Vri2 $28

Claims (1)

[Claims] (1) A first output terminal connected to the first input terminal via the first MISFET, a second output terminal connected to the second input terminal via the second MISFET, and a drain. a third MISFET having an electrode connected to the first output terminal, a source electrode connected to the first power supply, and a gate electrode connected to the second output terminal; and a drain electrode connected to the second output terminal. connected and the source electrode is connected to the first
a fourth MISFET connected to the power supply of the first output terminal and having a gate electrode connected to the first output terminal; In a sense amplifier circuit that outputs between first and second output terminals, first and second load elements respectively connected between the first and second output terminals and a second power supply; a fifth MISFET whose drain electrode is connected to the drain electrode of the third MISFET, whose source electrode is connected to the source electrode of the third MISFET, and whose gate electrode is connected to a third power supply; 4 MI
a sixth MISFET connected to the drain electrode of the SFET, a source electrode connected to the source electrode of the fourth MISFET, and a gate electrode connected to the third power supply; a third load terminal connected between the gate electrode of the MISFET; and a fourth load element connected between the first output terminal and the gate electrode of the sixth MISFET, Immediately before amplification, the second power supply and the third power supply are turned on to charge the gate capacitances of the fifth and sixth MISFETs, and during amplification, the third power supply is turned off and the voltage is the same as that of the third power supply. Turning on the first power supply that supplies a voltage so that a fifth or sixth MISFET connected to a third or fourth MISFET in a conductive state of the flip-flop circuit in a holding state becomes conductive. A sense amplifier circuit characterized by: