JPS6115345A - Manufacture of semiconductor ic device - Google Patents

Abstract

PURPOSE:To obtain the structure of element isolation in self-alignment by a method wherein a thin film having the characteristic of Si etching resistance is formed on the region outside the field region and on the field region at a required distance from the above-mentioned region, then being made as a mask for groove etching. CONSTITUTION:After an Si oxide film 2, an Si nitride film 3, and an Si oxide film 5 having the characteristic of Si etching resistance, and a resist 6 are formed on an Si substrate 1, an Si oxide film 7 is formed by etching the film 5. Thereafter, after deposition of aluminum films 8 and 9 having the characteristic of Si etching resistance, grooves 14 are formed under the regions of the films 9 and 7 by leaving Si nitride films 10, 12 and Si oxide films 11, 13. Next, the films 9, 10, and 11 are removed, and after formation of an Si oxide film 16 in the grooves 14 and the field region 15, a polycrystalline film 17 is formed in the air gap of the groove 14, and an Si oxide film 18 on the film 17; then, the films 12 and 13 are removed, thus obtaining an element region 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor integrated circuit device suitable for forming fine element isolation regions.

[Background of the invention]

As shown in FIG. 1, this type of conventional device performs oxidation using a laminated film consisting of a silicon oxide film 2 and a silicon nitride film 3 patterned on a silicon substrate 1 as a mask to selectively oxidize the device isolation region. Since a thick silicon oxide film 4 was formed, lateral oxidation below the laminated film region,
A so-called bird's beak A is formed, narrowing the device area.
There is a drawback that fine element isolation regions cannot be formed with good controllability.

Furthermore, in order to effectively perform isolation in the epitaxial layer of a bipolar LSI or isolation around the well of a complementary MO8LSI, it is necessary to achieve a deeper isolation than the thickness of the epitaxial layer or the depth of the well. It is technically difficult to obtain this deep isolation structure with a silicon oxide film that has been oxidized.

On the other hand, there is an isolation method that uses trenches to achieve the above-mentioned deep isolation, but this method only forms a narrow isolation region, and in order to reduce the wiring capacitance, photolithography is required again to form a thick silicon oxide film in the field region. This creates problems such as complicating the manufacturing process and reducing pattern alignment accuracy.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks and provide a method for manufacturing a semiconductor integrated circuit device with simple steps that can realize a fine element isolation structure.

[Summary of the invention]

In order to achieve this object, the present invention forms a first etching-resistant thin film that is resistant to silicon etching on a region other than the field region on a silicon substrate, and forms the first etching-resistant thin film on the field region. a first step of forming a second etching-resistant thin film that is resistant to silicon etching at a predetermined distance from an edge of the etching-resistant thin film;

a second step of etching the silicon substrate in areas where the first and second etching-resistant thin films are not formed to form grooves; and a second step of etching the silicon substrate in areas where the first and second etching-resistant thin films are not formed, and etching the grooves after removing the second etching-resistant thin films. The method is characterized in that it includes a third step of forming a silicon oxide film in the field region.

[Embodiments of the invention]

Hereinafter, two embodiments of the present invention will be described in detail with reference to the drawings.

Example 1 First, as shown in FIG. 2, a silicon substrate 1 is oxidized to form a silicon oxide film 2 with a thickness of 100 to 500 layers, followed by chemical vapor deposition using silane and ammonia. method (hereinafter referred to as CVD method) to achieve a film thickness of 00lIs.
A silicon nitride film 3 with a thickness of 1 to 0.2 cm is deposited, and then a first etching-resistant thin film resistant to etching of the silicon nitride film and silicon substrate is deposited by CVD to a film thickness of 1 to 2 cm. A silicon oxide film 5 is formed, and a patterned resist 6 is formed on the CVD silicon oxide film 5.

Next, the CVD silicon oxide film 5 is etched by reactive ion etching (RIE) using CF4 and hydrogen, and then the CVD silicon oxide film 5 under the resist 6 area is side-etched using a buffered hydrofluoric acid solution. A patterned CVD silicon oxide film 7 is formed as shown in FIG.

Next, as a second etching-resistant thin film resistant to etching of the silicon nitride film and the silicon substrate, aluminum films 8 and 9 are formed by sputtering or vapor deposition, as shown in FIG.

They are deposited with directionality on the resist 6 and silicon nitride film 3, respectively. By making the aluminum atoms sputtered from the aluminum target or the aluminum atoms evaporated from the crucible enter the main surface of the silicon substrate 1 almost perpendicularly, it is possible to prevent the aluminum atoms from being deposited in the side etching region.

Next, remove the resist 6 with acetone, and at the same time,
The aluminum film 8 on the resist 6 is lifted off, leaving the aluminum film 9 only on the silicon nitride film 3, as shown in FIG.

Next, as shown in FIG. 6, a silicon nitride film 10 and a silicon oxide film 11 are left under the area of the aluminum film 9, and a silicon nitride film 1 is left under the area of the CVD silicon oxide film 7.
The silicon nitride film and the silicon oxide film were etched by RIE using CF4 and hydrogen, leaving the silicon oxide film 13 and the silicon nitride film 13.

Subsequently, silicon substrate 1 was formed by RIE using CBrF3.
A groove 14 is formed by etching.

Next, after removing the aluminum film 9 using phosphoric acid, the silicon nitride film 10 and the silicon oxide film 11 are removed by RIE using CF4 and hydrogen, and the silicon substrate 1 is placed in the field region 15 shown in FIG. expose.

Next, the CVD silicon oxide film 7 is removed using a buffered hydrofluoric acid solution to obtain a cross-sectional structure as shown in FIG.

Next, oxidation is performed using the silicon nitride film 12 as a mask.
As shown in FIG. 9, a silicon oxide film 16 is formed on the surface of the trench 14 and field region 15. The above oxidation is carried out at 1000° C. for 200 minutes in a combustion hydrogen atmosphere, resulting in a film thickness of 0.6 to 0.7. A silicon oxide film is obtained.

Next, as shown in FIG. 10, a polycrystalline silicon film 17 is filled in the void remaining after the trench 14 has been oxidized by CVD method.The thickness of the polycrystalline silicon film 17 is as follows.

The width should be approximately the same as the width of the gap above.

Next, RIE or CC using y CB r F 3
The polycrystalline silicon film 17 on the silicon nitride film 12 and on the field region 15 excluding the trench is removed by plasma etching using n, F2, and the polycrystalline silicon film is removed only in the trench as shown in FIG. Then, the polycrystalline silicon surface is oxidized to form a silicon oxide film (polycrystalline silicon oxide film) 18 on the polycrystalline silicon filled in the trench.

Next, the silicon nitride film 12 and the silicon oxide film 1 are
3 is removed to obtain device regions 19 separated by trenches and field regions as shown in FIG.

Note that in the embodiments described above, a CVD silicon oxide film was used as the first etching-resistant thin film, and an aluminum film was used as the second etching-resistant thin film, but both the first and second etching-resistant thin films were made of silicon nitride. Resistant to etching of films and silicon substrates, and
As long as the first etching-resistant thin film has resistance to the etching of the second etching-resistant thin film, a thin film of another material may be used in place of the thin film shown in the above embodiment. A molybdenum film can be used as the etching thin film and an aluminum film can be used as the second etching resistant thin film. In this case, a potassium ferricyanide-based etching solution is used for side etching of the molybdenum film.

Further, when an aluminum film is used as the first etching-resistant thin film and a molybdenum film is used as the second etching-resistant thin film, phosphoric acid may be used for edge etching of the aluminum film.

Embodiment 2 In Embodiment 1, the case where the silicon oxide film formed in the field region and the silicon oxide film formed on the inner surface of the trench were formed at the same time was shown, but in this embodiment, the case where they are oxidized separately will be explained. Following the step of FIG. 8 shown in Example 1, a second silicon nitride film 20 is formed as shown in FIG.
is deposited by CVD to be 500 to 1000 times thinner than the first silicon nitride film 12, and a resist 21 is applied so that the resist surface is flat. For example, when using 0FPR800 (trade name; manufactured by Tokyo Ohka ■) as a resist, the film thickness in the area other than the groove is 1 to 2 μs.
When applied in such a manner, it is possible to completely fill a groove of 1 width IIM and 4 depths, and to flatten the resist surface.

Next, as shown in FIG. 14, the resist in the area other than the groove is removed, and etching is performed by RIE using oxygen so that the resist 22 remains in the groove, and then the groove is etched. The silicon nitride film on the field region 15 except for
Etching is performed by RIE using F4 and hydrogen, leaving the silicon nitride film 23 in the trench.

Next, as shown in FIG. 15, the resist 22 in the trench is removed by oxygen plasma, and then oxidized in a combustion hydrogen atmosphere to form a silicon oxide film 22 on the field region excluding the trench.
form 4.

Next, the silicon nitride film 23 in the trench is removed using phosphoric acid at about 160°C. At this time, the surface of the silicon nitride film 12 other than the field region is also etched, but the silicon nitride film 12 is etched by 50° from the silicon-occupied nitride film 23 in the trench.
The rounded silicon nitride film 12, which is 0 to 1000 times thicker, can be left on the silicon oxide film I3 by simply reducing the film thickness.

Next, as shown in FIG. 16, oxidation is performed in a combustion hydrogen atmosphere to form a silicon oxide film 25 in the trench.

In this embodiment, the thickness of the silicon oxide film 25 can be set to any thickness within a range that is thinner than the thickness of the silicon oxide film 24 and the width of the groove.

The subsequent steps can be performed as shown in FIG. 10 and subsequent figures of Example 1.

Example 3 In Examples 1 and 2, the grooves were filled with polycrystalline silicon, but in this example, a case where the grooves are filled with an insulator will be described.

Following the step shown in FIG. 9 shown in Example 1, a CVD silicon oxide film 26 is deposited as shown in FIG. 17 by the CVD method using, for example, silane and N20 at a substrate temperature of 700° C. to 900° C.

Next, the CVD was performed by RIE using CF4 and hydrogen.
The silicon oxide film 26 is etched and CV is formed only in the groove.
D so that the silicon oxide film 27 remains.

Note that a silicon nitride film formed by a CVD method can also be used as the insulator instead of the CVD silicon oxide film.

Further, as long as there is no cavity above the groove when filling the insulator by the above-mentioned CVD method, there is no problem even if there is a cavity in the groove.

Example 4 In Example 1, a trench etching mask was formed using side etching of the first etching resistant thin film and lift-off of the second etching resistant thin film, but in this example, the first etching resistant thin film A method of forming a groove etching mask by selectively removing the second etching-resistant thin film in a region near the end of the groove will be described.

First, as shown in FIG. 19, a silicon oxide film 2 is formed on a silicon substrate 1 by thermal oxidation. A silicon nitride film 3 and a molybdenum thin film 28 are deposited in this order as a first etching-resistant thin film by a CVD method and a sputtering method or a CVD method, and patterned by a known method.
An ECR silicon oxide film 29 is deposited as an etching-resistant thin film.

In the deposition of this silicon oxide film, the silicon oxide film 29 (
It is important to make sure that the etching rate of the portion indicated by B) is sufficiently faster than the etching rate of the silicon oxide film deposited in the region other than the vicinity of the end (portion other than B). For example, by depositing a silicon oxide film using electron cyclotron resonance (ECR), the etching rate of the portion B of the ECR silicon oxide film 29 deposited near the end with respect to the buffered hydrofluoric acid solution can be changed near the end. B of
50-1 of the silicon oxide film deposited on the area other than the
It can be multiplied by 50 times.

Next, as shown in FIG. 20, the ECR silicon oxide film 30t! is placed on the molybdenum thin film 28! :lpi, leaving the ECR silicon oxide film 31 on the silicon nitride film 3, and applying the ECR to the B part near the end of the molybdenum thin film 28.
The silicon oxide film is removed using a buffered hydrofluoric acid solution. In addition,
The amount of etching of the ECR silicon oxide film in portion B near the end is determined by the etching time of the silicon oxide film with the buffered hydrofluoric acid solution.

Next, follow the steps explained in FIG. 6 of Example 1.

Grooves 14 are formed as shown in FIG. Next, the silicon oxide films 30 and 31 were removed using a buffered hydrofluoric acid solution, and then the silicon nitride film 10 and silicon oxide film 11 that were under the silicon oxide film 31 were removed, and the molybdenum thin film 28 was then removed using sulfuric acid and sulfuric acid. The cross-sectional structure shown in FIG. 8 of Example 1 is obtained by removing with a mixture of hydrogen peroxide and water.

The subsequent steps are as described in Example 1 or 2.

〔Effect of the invention〕

As explained above, in the present invention, an element isolation structure having grooves around the field region can be obtained in a self-aligned manner.
(1) Since the element isolation region does not expand due to the bird's beak as in the conventional case, a fine element isolation structure can be realized. (2) Even when forming a wide element isolation region, isolation can be achieved with a single element isolation structure by forming a groove around the wide area, simplifying the process compared to conventional isolation methods using grooves. Therefore, the yield can be improved. (3) Since device isolation is performed using trenches, deep isolation can be achieved around the epitaxial layer or well, and excellent isolation characteristics can be obtained. (4) Since a thick silicon oxide film can be formed in the field region, the wiring capacitance of the integrated circuit can be reduced. As described above, the effects of the present invention are remarkable.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the conventional element isolation method, and Figures 2 to 1.
2 is a sectional view showing each step of the first embodiment of the present invention, FIGS. 13 to 16 are sectional views showing each step of the second embodiment of the invention, and FIGS. FIG. 18 is a sectional view showing each step of the third embodiment of the present invention, and FIG.
9 to 21 are sectional views showing each step of the fourth embodiment of the present invention. Silicon substrate 2.4, 11.13.16.1.8.24.25 Silicon oxide film 3, 10.12.20.23...Silicon nitride film 5, 7.26.27...CVD silicon oxide Film 6, 21.22...Resist 8.9...Aluminum film 14...Trench 15...Field region 17...Polycrystalline silicon film 19...Element region 28...Molybdenum thin film

Claims (1)

[Claims] 1. A first etching-resistant thin film that is resistant to silicon etching is formed on a region other than the field region on the silicon substrate, and the first etching-resistant thin film is formed on the field region. a first step of forming a second etching-resistant thin film that is resistant to silicon etching at a predetermined distance from the edge of the silicon etching-resistant thin film; a second step of etching the silicon substrate to form a groove;
1. A method of manufacturing a semiconductor integrated circuit device, comprising a third step of forming a silicon oxide film in the field region including the trench after removing the etching-resistant thin film. 2. In the first step, a patterned third thin film is formed on the first etching-resistant thin film deposited on the silicon substrate, and the third thin film is patterned to a predetermined depth from the edge of the third thin film. side-etching the first etching-resistant thin film using the thin film as a mask, depositing the second etching-resistant thin film on the third thin film and the silicon substrate, and removing the third thin film and simultaneously etching the first etching-resistant thin film. The second etching-resistant thin film deposited on the thin film of No. 3 is removed, and the second etching-resistant thin film is formed at a predetermined distance from the end of the first etching-resistant thin film. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 3. In the first step, forming the first etching-resistant thin film patterned on the silicon substrate,
The second etching-resistant thin film is deposited on the first etching-resistant thin film and the silicon substrate, and a predetermined region of the second etching-resistant thin film near the end of the first etching-resistant thin film is selectively deposited. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second etching-resistant thin film is formed at a predetermined distance from an end of the first etching-resistant thin film. .