JPS61150525A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To execute quickly and exactly an initial phase acquisition by providing the first phase locked loop for using a prescribed reference frequency signal as a reference signal, and providing the second phase looked loop for using a prescribed input signal being an object of a phase synchronization, as a reference signal, after a phase acquisition. CONSTITUTION:In a state before a phase acquisition, a phase error signal is sent to a voltage control oscillator 15 through a phase error signal selector 12 and a loop filter 14. In this state, when a control signal set in advance is applied to the voltage controlled oscillator 15 through the loop filter 14, for the purpose of an initial phase acquisition, a phase error signal 117 outputted from the second phase detector 11 is sent out to the loop filter 14 through a switching operation in the phase error signal selector 12, and the second phase locked loop is formed. In this case, the first phase locked loop is converted to the second phase locked loop smoothly and quickly, and the desired phase synchronization to a receiving signal 107 is attained.

Description

Detailed Description of the Invention (Field of Sedentary Application) The present invention relates to a phase-locked circuit, and in particular, in a phase-locked circuit formed by a phase-locked loop with a narrow loop bandwidth, initial phase compensation for a predetermined input signal is performed. This invention relates to a phase-locked circuit that improves time characteristics.

(Useful technology) In general, a reception f7ct1t corresponding to a relatively narrow band information signal or beacon signal is equipped with a phase-locked circuit having a phase-locked loop with a narrow loop bandwidth for the carrier signal or beacon signal. Demodulation of the signal or detection of the beacon signal is performed normally. An example of such a receiving device is, for example, a receiving device in a telemetry system intended for outer space.

In the above-mentioned receiving device that uses a phase-locked circuit with a narrow loop bandwidth, the phase compensation for the received input signal is performed by the voltage-controlled oscillator included in the phase-locked circuit.
Manual or fc is performed through an automatic frequency sweep function. What is shown in FIG. 3 is a conceptual block diagram of a phase-locked loop forming a conventional phase-locked circuit, in which, as is well known, a phase detector 25. Loop filter 26
and a voltage controlled oscillator 27 as main components. In FIG. 3, when performing initial phase compensation on the input signal 123, for example, the frequency sweep signal 124 is manually inputted via the loop filter 26 to control the oscillation frequency of the voltage controlled oscillator 27. Input signal 123
An auxiliary action is performed so that the 0 frequency can be captured by the four-phase law loop. −When phase compensation is performed,
The phase error signal 125 output from the phase detector 25 is
Voltage controlled oscillator 2 via loop filter 26'ft
7, the low frequency of the voltage controlled excavator 270 is controlled to maintain the phase synchronization state in the phase synchronization circuit.

(Problems to be Solved by the Invention) When the above-described conventional phase-locked circuit is applied to a receiving device that handles the loop bandwidth of a phase-locked loop, for example, it is applied to a telemetry receiving device that targets outer space. In some cases, the loop bandwidth is often operated in a narrow band state of several Hz below 10Hz or 1oHz,
A problem arises with the initial phase compensation described above. In the case of the above-mentioned telemetry receiving device, especially in the case of a telemetry receiving device targeting deep space gold, the frequency of the received signal is received as a nearly constant frequency due to the correlation with the signal transmitted from the ground. Ru. On the other hand, the oscillation frequency of the voltage controlled oscillator itself is affected by the supply voltage, ambient temperature, etc. 1ltl, and at the stage of initial phase compensation, the frequency is normally distributed over a frequency range of several hundred Hz (hertz) to several kHz (kilohertz). but,
Generally, the oscillation frequency value is completely uncertain.

In this state, a frequency sweep action is performed on the voltage-controlled excavator for initial phase compensation in the phase-locked circuit as described above.
Since the oscillation frequency of the pressure-controlled oscillator itself is uncertain, the accuracy of frequency acquisition must be low.

Furthermore, on the m side 7h, as mentioned above, the loop bandwidth of the phase locked circuit is a narrow band of about several klZ, so the frequency sweep speed for the above-mentioned '1 pressure controlled oscillator is severely restricted. This is clear from the correspondence between the time TL (s) during which phase locking occurs in the phase-locked loop and the sweep speed [F (Hz/s)] of the frequency sweep signal.

Assuming that the loop bandwidth of the phase-locked circuit is B (Hz), in an approximate sense, (B/F)>TL is an essential condition for phase compensation to be performed reliably. Therefore, the frequency sweep speed F is limited by the following formula: F<(B/TL) and V). Here, the phase pull-in time Tt becomes a larger value as the loop bandwidth B becomes smaller, so the frequency sweep speed F is rapidly suppressed to a lower sweep speed as the loop bandwidth becomes smaller.

Originally, in order to quickly restore the above-mentioned receiving device to a normal operating state, in response to the frequency deviation, the initial phase compensation should be completed within as short a time as possible by the frequency sweep action on the voltage control excavator, and the desired phase should be achieved. However, due to the above-mentioned constraints on frequency capture accuracy and frequency sweep speed, it actually takes a considerable amount of time for phase compensation, which makes it difficult to operate the receiver. This has become a problem. That is, the conventional phase-locked circuit has the drawback that it takes a long time for initial phase compensation when the loop bandwidth is narrow.

(Means for Solving the Problems) In order to solve the above problems, the phase synchronization circuit of the present invention uses a predetermined reference frequency signal as a reference signal in a state before initial phase compensation, and uses a 10th frequency signal as a reference signal. a phase detector, a phase error signal selector that selects and outputs a tenth phase error signal output from the tenth phase detector in accordance with a predetermined selection signal, and a loop corresponding to the tenth phase error No. 1d.
a tenth phase-locked loop formed by comprising a filter and a voltage-controlled oscillator;
The reference signal is shared with the second phase detector and the tenth phase-locked loop that selects and outputs the second phase error signal output from the second phase detector according to a predetermined selection signal. the phase error signal selector, and the loop filter and voltage controlled oscillator shared with the tenth phase-locked loop corresponding to the second phase error signal;
A second phase-locked loop is formed with a gold bias.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1(a) is a conceptual block diagram showing the main components of the present invention, including a tenth phase detector 1 and a second phase detector 2.
, a phase error signal selector 3, a loop filter 4,
A voltage-controlled excavator 5 is provided. Also, Figure 1 tb)
and tc) respectively indicate the state before the initial phase compensation and the state after the initial phase compensation of the phase-locked circuit shown in FIG. 1 tal. In the previous state, the tenth phase detector 1 and the second phase detector 2 have
A human power 1fi1 102 to be phase synchronized with a predetermined reference frequency signal 101 is manually powered, and the voltage controlled oscillator 5
are mixed with the feedback signals sent from the first
0 phase error signal 103 and second phase error signal 104
is output and input to the phase error signal selector 3. In this state before phase compensation, phase synchronization with respect to the input signal 102 is not established, so the phase synchronization determination signal 105 input to the phase error selector 3 acts as a status signal indicating asynchrony. , the switching circuit in the phase error signal selector 3 operates so that the tenth phase error signal 103 is sent to the loop filter 4. Therefore, the first
0 phase detector 1. Phase error signal selector 3. A tenth phase locked loop consisting of loop filter 4 and voltage controlled oscillator 5 is formed, and the voltage controlled oscillator 50 oscillation wave number and phase are regulated by reference frequency 101. That is, in the state before initial phase compensation, the oscillation frequency of the voltage controlled oscillator 5 is regulated by the frequency of the reference frequency signal 1010 and does not vary arbitrarily. Therefore, the oscillation frequency of the voltage controlled oscillator 5 has a predetermined correlation with the input signal 1020 having a predetermined expected frequency, and the preset frequency control signal 106
is input to the voltage controlled oscillator 5 via the loop filter 4, and the oscillation frequency of the voltage controlled oscillator 5 is controlled so that the input signal 1020 frequency falls within the loop bandwidth.
1 will be adjusted. In this state, the phase synchronization determination signal 105 manually input to the first phase error signal selector 3 acts as a state signal indicating synchronization, and the switching circuit in the phase error signal selector 3 detects that the second phase error signal 104 is It operates so that the signal is sent to the loop filter 4. Therefore, at this point, the second phase detector 29 phase error signal selector 3.
A second phase-locked loop consisting of loop filter 4 and voltage controlled oscillator 5 is formed to obtain the desired phase-locked state for n1 input signal 102. FIG. 1tc) shows the state in which the second phase-locked loop is formed.

Next, one embodiment of the present invention will be described. FIG. 2 is a block diagram showing the components of this embodiment. As shown in the figure, the frequency mixer 6.8.23, intermediate frequency amplifier 7.10, local oscillator 9, 2 phase detector 11, phase error signal selector 12, phase rule discriminator 13, loop filter 14, and voltage controlled oscillator 15
, a branching unit 16, 19, a π/2 phase shifter 17, an amplitude detector 18, a tenth phase detector 2o, a reference frequency oscillator 21, a frequency synthesizer 22, and a frequency multiplier 2.
4.

In FIG. 2, the received signal 107 is input to the frequency mixer 6, mixed with the local oscillation signal 108 sent from the frequency aa multiplier 24, outputted as an intermediate frequency signal, and amplified by the intermediate frequency amplifier 7. Frequency mixer 8vc is input. In this case, the local oscillation signal 108 is the oscillation output signal 109 of the voltage controlled oscillator 15, which is generated by the frequency mixer 23.
and a feedback signal for phase synchronization outputted through the frequency multiplier 24t; in this example, the received signal 1070
The frequency value is selected to be higher by the corresponding intermediate frequency. In the frequency mixer 8, the received signal inputted from the intermediate frequency amplifier 7 is mixed with a local oscillation signal manually input from the local oscillator 9, output as a predetermined intermediate frequency signal, and then outputted as a predetermined intermediate frequency signal. It is amplified and sent as a received signal 110 to the second phase detector 11 and amplitude detector 18 . The amplitude detector 18 receives a reference signal 1110, π/
A reference signal 112 phase-shifted by the 2 phase shifter 17 is input manually, and the reference signal 111 described above is input manually to the second phase detector 11. Received signal 110
The intermediate frequency corresponding to is set to be the same as the frequency of the reference signals 111 and 112 in the phase synchronization state, and the ice width detector 18 and the 20th phase detector 11 are set to be the same as the frequency of the reference signals 111 and 112 in the phase synchronization state. Each has amplitude detection and phase detection functions. Therefore, in the state before the initial phase compensation, the vibration @ transverse wave generator 18 outputs,
The detection output signal 113 sent to the phase synchronization discriminator 13 is
A predetermined standard level is never reached. Therefore, the phase synchronization determination signal 118 output from the phase synchronization discriminator 13
is sent to the phase error signal selector 12 as an asynchronous state signal.

In the phase error signal selector 12, the phase synchronization discrimination signal 118 corresponding to non-synchronization is manually input, and as a switching action, instead of the second phase error signal 1170 sent from the second phase detector 11, It is set so that the first tenth phase error signal 116 sent from the tenth phase detector 20 is sent to the Lou filter 14. This tenth phase error signal 116 is input to the voltage controlled oscillator 15 as a control signal 120 via the loop filter 14, and its oscillation output signal 109 is sent to the frequency converter 23 as described above.
and the locally generated fIi signal 1 via the frequency multiplier 24.
08 to the frequency mixer 6, and the feedback signal 115 is sent to the tenth phase detector 20 via the divider 16.
It is man-powered as follows.

In the tenth phase detector 20, the reference signal oscillator 21
Reference signal 1 is output from the station and divided by the divider 19.
14 and the feedback signal 115 are mixed and phase detected,
A phase error signal 116 is generated. This phase error signal is sent to the voltage controlled oscillator 15 via the phase error signal selector 12 and loop bow router 14 in a state before phase compensation. That is, 11410 phase detector 2
0° phase error signal selector 12. A tenth phase-locked loop is formed by the loop filter 14° voltage-controlled oscillation 615 and the frequency divider 16, and the oscillation frequency of the voltage-controlled oscillator is regulated by the frequency of the reference signal 114, and is always a steady frequency before phase compensation. Shares are held in value.

In this state, a preset control signal 119 is sent to the loop filter 1 for initial phase compensation.
4 to the voltage controlled oscillator 15 and fed back to the frequency mixer 6, the frequency mixer 6, the intermediate frequency amplifier 72, the frequency mixer 8. Intermediate frequency amplifier 10. Second phase detector 119 phase error signal selector 12. Loop filter 141'# is connected to pressure controlled oscillator 15. The second phase-locked loop formed by the frequency mixer 23, the frequency multiplier 24, and the like starts phase compensation and phase synchronization on the received signal 107, and the amplitude detector 18 outputs a detected output at a predetermined level. A signal 113 is output, and the phase synchronization discriminator 13
A phase synchronization determination signal 118 corresponding to synchronization is generated at i and inputted to the phase error signal selector 12 . As a result, through the switching action in the phase error signal selector 12,
Phase error signal 11 output from second phase detector 11
7 is sent to the loop φ filter 14 so that ζ becomes K, forming the aforementioned second phase-locked loop. In this case, the reference signal 1140 frequency and the control signal 119 are selected to have appropriate values that suit the initial phase compensation effect with respect to the frequency value of the received signal 107 that is expected in advance,
Coupled with the potential holding action in the loop filter 14 and the circuit switching action in the phase error signal selector 12, the tenth phase-locked loop is smoothly and quickly switched to the second phase-locked loop, and the received signal The intended phase synchronization for 107 is overacided. In addition, in FIG. 2, the frequency synthesizer 22 has a function of manually setting the frequency of the local oscillation signal to the frequency mixer 6 by manually inputting the reference signal 121 of a specific frequency output from the reference frequency signal generator 21. The reference signal 122 output from the synthesizer 22 and the oscillation output signal 109 output from the voltage controlled oscillator 15 are mixed in the frequency mixer 23,
A feedback signal with a frequency corresponding to the sum or difference of both frequencies is sent to the frequency multiplier 24.

(Effects of the Invention) As described above in detail, the present invention provides a phase-locked circuit formed by a phase-locked loop with a narrow loop bandwidth, in which a predetermined reference frequency signal is used as reference No. 15 before phase compensation. After phase compensation, a second phase-locked loop that uses a predetermined input signal to be phase synchronized as a reference signal is provided, so that initial phase compensation can be performed quickly and efficiently. This has the effect of being able to be carried out accurately.

[Brief explanation of drawings]

FIGS. 1(a), (b) and lc) are conceptual block diagrams showing the main parts of the present invention, FIG. 2 is a block diagram showing the mounting part of an embodiment of the present invention, and FIG. , which is a conceptual block diagram showing the main parts of a conventional phase-locked circuit, 1.20...10th phase detector,
2.11... Second phase detector, 3.12...
...Phase error signal selector, 4, 14.26...
... Loop filter, 5, 15.27 ... Voltage controlled oscillator, 6°8.23 ... Frequency mixer, 7.10 ... Intermediate frequency amplifier, 9・・・・・・
・Local oscillator, 13... Phase synchronization discriminator, 16
, 19... Frequency divider, 17... π/2 phase shifter, 18... Amplitude detector, 21...
Reference frequency oscillation, 22...- Frequency synthesizer, 24... Frequency multiplier. Agent Patent Attorney Susumu Uchihara 1. . /!・, τ1゜1241. −〜． /1・1. + Figure 1 Figure 3

Claims (1)

[Claims] In a state before initial phase compensation, a predetermined reference frequency signal is used as a reference signal, and a predetermined selection signal is output from the first phase detector and the first phase detector according to a predetermined selection signal. 1st
a first phase error signal selector that selects and outputs a phase error signal; a loop filter and a voltage controlled oscillator corresponding to the tenth phase error signal;
In the state after the initial phase compensation, the second phase detector uses a predetermined input signal to be phase synchronized as a reference signal and a predetermined selection signal to detect the second phase. the phase error signal selector shared with the first phase-locked loop that selects and outputs a second phase error signal output from a wave detector; and the first phase error signal corresponding to the second phase error signal. A phase-locked circuit comprising: a second phase-locked loop formed by comprising the loop filter and the voltage-controlled oscillation, which are shared with the phase-locked loop.