JPS61154172A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing an MO8 type semiconductor device.

[Technical background of the invention]

In MO8 type semiconductor devices, in order to avoid electric field concentration at the end of the drain region due to higher breakdown voltage and miniaturization, LDD (LDD) provides a channel region at the end of the gate region with a lower concentration than the drain region. L i!1lht
D0DedDrain) structure is under development. MO8 semiconductor devices having such an LDD structure, such as n-channel MOS transistors, have conventionally been manufactured by the method shown in FIGS. 2(a) to 2(e) described below.

First, a field oxide film 2 with a thickness of approximately 1 μm is formed on the surface of a p-type silicon substrate 1 by selective oxidation, and then thermal oxidation treatment is performed to form a thick film on the surface of island-shaped substrate 1 regions separated by field oxide film 2. An oxide film 3 of 500 layers is formed. Subsequently, channel implantation for threshold control is performed through the oxide film 3. Subsequently, a gate electrode material film, such as a polycrystalline silicon film, is deposited on the entire surface, and phosphorus is diffused in the POCffi atmosphere to dope phosphorus into the polycrystalline silicon film to lower its resistance. The gate electrode 4 is formed by patterning the film using a photoetching technique (as shown in FIG. 2(a)).

Next, using the gate electrode 4 and the field oxide film 2 as a mask, the oxide 1113 is selectively etched away to form a gate oxide [15], and then phosphorus is ion-implanted using the gate electrode 4 and the field oxide film 2 as a mask to form phosphorus ions. Form injection layers 61 and 62 (as shown in the same figure (b))
.

Next, annealing is performed in an N2 atmosphere to activate phosphorus and form low concentration n-type diffusion regions 71 and 72. Subsequently, a post-oxidation treatment is performed to form a thin post-oxidation film 8 on the gate electrode 4 and the exposed surface of the substrate 1, and then a CVD-8i02 film 9 is deposited on the entire surface (as shown in FIG. 4C). Subsequently, the entire surface is etched by reactive ion etching (RIE) to form a post-oxide film 8 on the side surface of the gate electrode 4.
After forming a wall 10 made of SiO2, arsenic is ion-implanted into the substrate 1 using the field oxide film 2, gate electrode 4, and wall 10 as a mask to form an arsenic ion-implanted layer 111.
112 (as shown in FIG. 11(d)).

Next, annealing is performed in an N2 atmosphere to activate arsenic and form highly concentrated n+ type diffusion regions 121 and 122. As a result, an n-type diffusion region 71 is formed on the surface of the substrate 1.
and a source region 13 consisting of an n+ type diffusion region 121 and an n-
A drain region 14 consisting of a type diffusion region [72] and an n" type diffusion region 122 is formed. Subsequently, a CVD-8i02 film 15 as an interlayer insulating film is deposited on the entire surface, and a contact hole 16 is opened by photoetching. After making a hole,
By vapor deposition and patterning of the A2 film, Aj2 wirings 17 and 18 which are connected to the source and drain regions 13 and 14 through the contact hole 16 are formed, respectively, to manufacture an n-channel MOS transistor (as shown in FIG. 12(e)).

[Problems with background technology]

However, in the conventional method described above, there is a phosphorus ion implantation step for forming the n-type diffusion regions 71, 72, a deposition step of the CVD-8i02 film 9, a step of forming the wall body 10, and a step of forming the n+-type diffusion region. Since it is manufactured through complicated processes such as an arsenic ion implantation process to form 121 and 122, it poses a problem in terms of productivity. Furthermore, if positive mobile ions (e.g., Na'', K'') are contained in the gate oxide film 5 above the n- type diffusion regions 7 and 72, the surface becomes accumulated and becomes an n+ region, forming an LDD structure. It no longer fulfills its role, leading to deterioration in pressure resistance. On the other hand, n-channel MOS
In the case of an LDD structure of a transistor, when positive mobile ions are included in the gate oxide film above the p-type region, the surface enters a depletion layer state, a depletion layer is formed above the p-type region, and the p- This reduces the effective thickness of the mold region and increases the resistance, resulting in reliability problems such as a reduction in the driving force of the transistor and destruction due to Joule heat generation.

(Objective of the Invention) The present invention provides a method for manufacturing a semiconductor device such as a MOS transistor having a highly reliable LDD structure through simple steps.

[Summary of the invention]

The present invention includes a step of forming a gate electrode material film on the surface of a first conductivity type semiconductor substrate via an oxide film, and after patterning this material film to form a gate electrode, using the gate electrode as a mask, A process of selectively etching the oxide film to form a gate oxide film, a process of performing thermal oxidation treatment to form a thin oxide film on the exposed substrate surface, and a process of forming a glass doped with second conductivity type impurities on the entire surface. After depositing the film, etching is performed to form walls made of the glass on the side surfaces of the gate electrode, and etching is performed on the exposed substrate surface using the gate electrode and walls as masks.
The method is characterized by comprising a step of forming a conductivity type diffusion region and diffusing a second conductivity type impurity from the wall into the substrate to form a low concentration second conductivity type diffusion region. . According to the present invention, a semiconductor device such as a MOS transistor having a highly reliable LDD structure can be obtained through a simple process as described above.

[Embodiments of the invention]

Hereinafter, the present invention will be described as an n-channel MOS having an LDD structure.
Figure 1(a) shows an example of application to transistor manufacturing.
This will be explained with reference to (d).

First, a field oxide film 22 with a thickness of about 1 μm is formed on the surface of a p-type silicon substrate 21 by selective oxidation, and then a thermal oxidation process is performed to form a thick film on the surface of the island-shaped substrate 21 separated by the field oxide film 22. An oxide film 23 of 500 layers is formed. Subsequently, channel implantation for threshold control was performed through the oxide film 23. Subsequently, a gate electrode material film, for example, a polycrystalline silicon film, is deposited to a thickness of 4000 μm over the entire surface, and phosphorus is diffused in an atmosphere of POCl2 to dope phosphorus into the polycrystalline silicon film to lower its resistance. Then, the polycrystalline silicon film was patterned using photoetching technology to form a gate electrode 24 (second
Figure (a) shown).

Next, using the gate electrode 24 as a mask, the oxide film 23 was selectively etched away to form a gate oxide film 25. Subsequently, after performing post-oxidation treatment to form a thin post-oxidation film 26 on the gate electrode 24 and the exposed surface of the substrate 21, a phosphorus-doped glass film (PS) is formed on the entire surface including the gate electrode 24.
G film) 27 was deposited (as shown in FIG. 3(b)).

Next, the entire surface is etched by reactive ion etching (RIE) to deposit P on the post-oxide film 26 on the side surface of the gate electrode 24.
After forming the wall 28 made of SG, field oxidation [
122, arsenic is ion-implanted into the substrate 21 using the gate electrode 24 and the wall 28 as a mask to form an arsenic ion-implanted layer 29t.
, 292 (as shown in FIG. 2C).

Next, annealing was performed in an N2 atmosphere. At this time, the arsenic ion implantation layer 29! , 292 is activated ^
At the same time, n+ type diffusion regions 301 and 302 with a high concentration were formed, and phosphorus was diffused into the substrate 21 from the wall body 28 made of PSG to form n− type diffusion regions 311 and 312. As a result, the n- type diffusion region 311 and the n+
A source region 32 consisting of a type diffusion region 301, a drain region 33 consisting of an n- type diffusion region 312, and an n+ type diffusion region 302 were formed. Subsequently, a CVD-8i02 film 34 as an interlayer insulating film is deposited on the entire surface, and a contact hole 35 is opened using photoetching technology.
The contact hole 3 is formed by film deposition and patterning.
A2 wirings 36 and 37 connected to the source and drain regions 32 and 33 through 5 are formed respectively to form n-channel MO
An S transistor was manufactured (as shown in the same figure (d)).

According to the present invention, the wall body 28 made of PSG is
By also using it as a diffusion source for forming the - type diffusion regions 311 and 312, the phosphorus ion implantation process and annealing process for forming the n - type diffusion region can be omitted. n with
A channel MOS transistor can be obtained. Further, by forming the wall body 28 made of PSG near the gate oxide film 25, it is possible to prevent positive mobile ions from accumulating in the gate oxide film 25 due to the passivation effect of the PSG. As a result, gate oxidation [125
The withstand voltage can be improved, and a highly reliable MOS transistor can be obtained.

Note that the present invention is not limited to the manufacture of n-channel MOS transistors as explained in the above embodiments, but is also applicable to LDDs.
The present invention can be similarly applied to an n-channel MOS transistor having the same structure, 0MO8, etc. having the same structure.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device such as a MOS transistor having a highly reliable LDD structure through simple steps.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) show LDDs in embodiments of the present invention.
2(a) to 2(e) are cross-sectional views showing the manufacturing process of an n-channel MOS transistor having the structure of a conventional LDD.
FIG. 3 is a cross-sectional view showing the manufacturing process of an n-channel MOS transistor having the structure. DESCRIPTION OF SYMBOLS 21... P-type silicon substrate, 22... Field oxide film, 24... Gate electrode, 25... Gate oxide film, 28 ・Wall body made of PSG, 30t, 302
- n1 type diffusion region, 311.312... n- type diffusion region, 32... source region, 33... drain region,
36.37...A2 wiring.

Claims (1)

[Claims] A step of forming a gate electrode material film on the surface of a first conductivity type semiconductor substrate via an oxide film, and after patterning this material film to form a gate electrode, selecting the oxide film using the gate electrode as a mask. The first step was to perform thermal oxidation treatment to form a gate oxide film, the second step was to perform thermal oxidation treatment to form a thin oxide film on the exposed substrate surface, and the second step was to deposit a glass film doped with second conductivity type impurities over the entire surface. After that, etching is performed to form a wall made of the glass on the side surface of the gate electrode, and a highly concentrated second conductivity type diffusion region is formed on the exposed substrate surface using the gate electrode and the wall as a mask. A method of manufacturing a semiconductor device, further comprising the step of diffusing second conductivity type impurities from the wall into the substrate to form a low concentration second conductivity type diffusion region.