JPS61131476A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61131476A JPS61131476A JP59252905A JP25290584A JPS61131476A JP S61131476 A JPS61131476 A JP S61131476A JP 59252905 A JP59252905 A JP 59252905A JP 25290584 A JP25290584 A JP 25290584A JP S61131476 A JPS61131476 A JP S61131476A
- Authority
- JP
- Japan
- Prior art keywords
- type
- diffusion layer
- substrate
- well
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims description 25
- 230000000295 complement effect Effects 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
、本発ｉは半導体装置、より詳しくはエピタキシャル層
を用いてｐウェルのツース電位を基板からとり、Ｖｓｓ
線をなくした構造の０ＭＯＳに関する。Detailed Description of the Invention [Industrial Application Field] The present invention is a semiconductor device, more specifically, an epitaxial layer is used to take the tooth potential of a p-well from a substrate, and
This relates to 0MOS with a structure that eliminates lines.
従来のＣＭＯＳインバータは第２図に示され、同図にお
いて、２１はｎ型シリコン基板、２２はｐウェル、２３
と２４はｎ＋型トドレインソース、２５と２６はｐ“型
とｎ＋型のストッパ、２７はｐ＋型型数散層２８と２９
はｐ１型のソースとドレイン、３０はｎ＋型広拡散層３
１は５ｔ０２ Ｉｌｌ、 ３２はゲート電極（入力）、
３３は出力端子、３４はｎチャンネルＭＯＳ 、 ３５
はｐチャンネ７Ｌ／ ＭＯＳ、 ３６はＶｓｓ線、３７
はＶｄｄ線、をそれぞれ示す、 ・
□（発明が解決しようとする問題点〕
従来は、第２図に示すｃＦｉｏｓインバータにおいてＶ
ｓｓ線を基板の上に設□ける必要があり、それにはコン
タクトホールの形成を伴った。しかし、集積回路（ＩＣ
）の集積度を高めるためには、ＩＣ上を延在する配線数
を減らす必Ｑｆｉ＜ 、％る。また、回路設計上、Ｖｓ
ｓ線を設けることが場所とか既に形成されたデバイス、
配線などの関係で難しくなる問題もある。A conventional CMOS inverter is shown in FIG. 2, in which 21 is an n-type silicon substrate, 22 is a p-well, and 23 is an n-type silicon substrate.
and 24 are n+ type drain sources, 25 and 26 are p" type and n+ type stoppers, and 27 are p+ type scattered layers 28 and 29.
are p1 type source and drain, 30 is n+ type wide diffusion layer 3
1 is 5t02 Ill, 32 is the gate electrode (input),
33 is an output terminal, 34 is an n-channel MOS, 35
is p channel 7L/MOS, 36 is Vss line, 37
indicate the Vdd line, respectively.
□ (Problem to be solved by the invention) Conventionally, in the cFios inverter shown in FIG.
SS lines had to be placed on the substrate, which involved forming contact holes. However, integrated circuits (ICs)
), it is necessary to reduce the number of wiring lines extending over the IC. Also, due to circuit design, Vs
Place the S-line on an already formed device,
There are also problems related to wiring, etc.
〔問題点を解決するための手段〕 □本発明
は、上記問題点を解消したＶｓｓ線をなくした０ＭＯＳ
を提供するもので、その手段は、相補型ＭＯＳ（Ｃ−Ｍ
ＯＳ ）構造のｎチャンネルトランジスタにおいて、エ
ピタキシセル層のｐウェルに設けたドレイン拡散層とソ
ース拡散層のうちソース拡散層は基板内に達する深さの
ものであり、ｐウェルの基準電位はソース拡散層を通し
て前記基板から引出す構成としたことを特徴とする半導
体装置によってなされる。[Means for solving the problems] □The present invention is a 0MOS without a Vss line, which solves the above problems.
The means for this purpose is complementary MOS (C-M
In an n-channel transistor with an OS) structure, of the drain diffusion layer and source diffusion layer provided in the p-well of the epitaxial cell layer, the source diffusion layer has a depth that reaches into the substrate, and the reference potential of the p-well is the source diffusion layer. A semiconductor device characterized in that it is drawn out from the substrate through a layer.
上記装置においては、ｃｎｏｓのｎチャンネルトランジ
スタにおいて、ｐウェルの基準電位（νＳＳ ）を基板
の表面から配線を用いてとるのではなくて、ソース拡散
層をエピタキシャル層を超えて基板内にまで達する深さ
に形成することにより基板の裏面から基準電位をとるも
のである。In the above device, in the CNOS n-channel transistor, the p-well reference potential (νSS) is not taken from the surface of the substrate using wiring, but the source diffusion layer is deep beyond the epitaxial layer and reaches into the substrate. The reference potential is taken from the back surface of the substrate by forming the electrode on the back surface of the substrate.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図に本発明にかかるＣＭＯＳが断面図で示され、同
図において、１はｎ型シリコン基板、２はｐ１型埋込層
、３はエピタキシャル層、４はｎ＋型）’レイン拡散層
、５は基板に達する深さのｎ＋型ソース拡散層、６はゲ
ート電極、を示し、これらでｎチャンネルトランジスタ
７が構成されている。FIG. 1 shows a cross-sectional view of a CMOS according to the present invention, in which 1 is an n-type silicon substrate, 2 is a p1-type buried layer, 3 is an epitaxial layer, 4 is an n+ type)' rain diffusion layer, Reference numeral 5 indicates an n+ type source diffusion layer deep enough to reach the substrate, and reference numeral 6 indicates a gate electrode, which constitute an n-channel transistor 7.
そしてこのトランジスタ７において、エピタキシャル層
３はｐ型不純物の拡散によってｐウェルとなっている。In this transistor 7, the epitaxial layer 3 becomes a p-well by diffusion of p-type impurities.
ｐチャンネルトランジスタ８の部分は、ｐ−型層９、ｎ
４型層１０１．ｐ″型のドレイン拡散層１１とソース拡
散層１２、ゲート１３によって構成される。The p-channel transistor 8 portion has a p-type layer 9, an n
Type 4 layer 101. It is composed of a p'' type drain diffusion layer 11, a source diffusion layer 12, and a gate 13.
本―明は、ＣＭＯＳのｎチャンネルトランジスタ７に特
徴があり、このトランジスタにおいて、ソース拡散層は
、ｐウェルをこえて基板内に達する深さに形成されてい
るので、Ｖｓｓ電位は、ソース拡散層（ｎゝ型）一基板
（ｎ−型）の径路でとり出すことができるので、従来の
Ｖｓａ線は設ける必要がな（なっている、奄して、ｐ＋
型埋込層２はウェル抵抗を減少するために設けたもので
ある。The present invention is characterized by a CMOS n-channel transistor 7, in which the source diffusion layer is formed deep enough to reach into the substrate beyond the p-well. (n type) can be taken out through the path of one substrate (n- type), so there is no need to provide a conventional Vsa line.
The mold burying layer 2 is provided to reduce well resistance.
次に、第１図の装置のｎチャンネルトランジスタ７を作
る方法について説明する。Next, a method of manufacturing the n-channel transistor 7 of the device shown in FIG. 1 will be explained.
■−固有抵抗１Ω・ｃｍ、結晶方位（１００）のｎ型シ
リコン基板１を用意する。そして、ｐウェル抵抗を減少
するためのｐ＋型埋込層２を、砒素をドーズＩ Ｘ １
０ ｉ３／ ｃｓ＋２．２０ＫｅＶの加速エネルギーで
イオン注入して形成する。- Prepare an n-type silicon substrate 1 with a specific resistance of 1 Ω·cm and a crystal orientation of (100). Then, the p+ type buried layer 2 for reducing the p-well resistance is doped with arsenic I x 1
It is formed by ion implantation with an acceleration energy of 0 i3/cs+2.20 KeV.
■エピタキシャル成長によって１．５μ鴎の厚さのエピ
タキシャル層３を形成する。(2) Form an epitaxial layer 3 with a thickness of 1.5 μm by epitaxial growth.
■混酸化法により１μ−の厚さのフィールド酸化膜（図
示せず）を形成する。以下の工程は、フィールド酸化膜
によって分離された素子領域に対して実施される。(2) A field oxide film (not shown) with a thickness of 1 μm is formed by a mixed oxidation method. The following steps are performed on device regions separated by field oxide films.
■図示しないゲスト絶縁膜（ゲート酸化膜）を形成する
。■A guest insulating film (gate oxide film) (not shown) is formed.
■全面に多結晶シリコン（ポリシリコン）を５０００Ａ
の膜厚に成長し、それをパターニングしてゲート電極６
を形成する。■5000A polycrystalline silicon (polysilicon) on the entire surface
The gate electrode 6 is grown by patterning it to a thickness of
form.
■砒素をイオン注入しでドレイン拡散層４とソース拡散
層５を形成する。この段階で、ソース拡散層５の深さは
ドレイン拡散層４の深さ・と同じである。(2) A drain diffusion layer 4 and a source diffusion layer 5 are formed by ion-implanting arsenic. At this stage, the depth of the source diffusion layer 5 is the same as the depth of the drain diffusion layer 4.
■ドレイン拡散層４をレジストでカバーして、ソース拡
散層５だけに、燐を、ドーズ５ Ｘ １０１１／ｃｖａ
’以上、２００にｅＶの加速エネルギーでイオン注入し
てｐ＋埋込層２をこえて基板内に達する拡■全面に燐・
シリケート・ガラス（ＰＳＧ）を１■ＰＳＧ層にコンタ
クトホールを′開ける。このとき、ｎチャンネルトラン
ジスタのソースのコンタクトホールは作らなくてよい。■Cover the drain diffusion layer 4 with resist and apply phosphorus only to the source diffusion layer 5 at a dose of 5 x 1011/cva.
As described above, ions were implanted at an acceleration energy of 200 eV to spread phosphorus over the entire surface beyond the p+ buried layer 2 and into the substrate.
A contact hole is opened in the PSG layer of silicate glass (PSG). At this time, it is not necessary to make a contact hole for the source of the n-channel transistor.
［株］全面にアルミニウムを被着し、それをパター；＊
（％Ｊ（７）ご＝：ニス↓：：ご゛、１″゛″゛以上説
明し衣ように本発明によれば、Ｃ間ｓインバータにおい
て、ｎチャンネルトランジスタのソース拡散層をｐウェ
ルをこえて基板内に達する縦型構成とすることにより、
従来のＶｓｓ線が不要になり・更にｎチャンネルトラン
ジスタのソースのコンタクトホールも不要になり、Ｃｒ
３Ｏ２の高集積化が可能になるだけでな″く、設計の自
由度が増大する効果がある。[Co., Ltd.] Covers the entire surface with aluminum and uses it as a putter; *
(%J(7)GO=:varnish↓::go, 1'''''') As explained above, according to the present invention, in a C-to-C S inverter, the source diffusion layer of an n-channel transistor is connected to a p-well. By adopting a vertical configuration that reaches beyond the board,
The conventional Vss line is no longer required, and the contact hole for the source of the n-channel transistor is also no longer required.
This not only enables high integration of 3O2, but also has the effect of increasing the degree of freedom in design.
第１図は本発明実施例の断面図、第２図は従来のｃｎｏ
ｓインバータの断面図である。
図中、ｌはｎ型シリコン基板、２はｐ＋型埋込層、３は
ｐウェル、４はｎ”型ドレイン拡散層、５はｎ ＋、型
ソース拡散層、６はゲート電極−１７はｎチャンネルト
ランジスタ、をそれぞれ示す。
第１図Figure 1 is a sectional view of the embodiment of the present invention, Figure 2 is a conventional CNO
FIG. 3 is a cross-sectional view of the s-inverter. In the figure, l is an n-type silicon substrate, 2 is a p+ type buried layer, 3 is a p well, 4 is an n'' type drain diffusion layer, 5 is an n+ type source diffusion layer, 6 is a gate electrode -17 is an n The channel transistors are shown in Figure 1.
Claims (1)
ンジスタにおいて、エピタキシャル層のｐウェルに設け
たドレイン拡散層とソース拡散層のうちソース拡散層は
基板内に達する深さのものであり、ｐウェルの基準電位
はソース拡散層を通して前記基板から引出す構成とした
ことを特徴とする半導体装置。In an n-channel transistor with a complementary MOS (C-MOS) structure, of the drain diffusion layer and source diffusion layer provided in the p-well of the epitaxial layer, the source diffusion layer has a depth that reaches into the substrate; A semiconductor device characterized in that a reference potential is drawn out from the substrate through a source diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252905A JPS61131476A (en) | 1984-11-30 | 1984-11-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252905A JPS61131476A (en) | 1984-11-30 | 1984-11-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61131476A true JPS61131476A (en) | 1986-06-19 |
Family
ID=17243797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59252905A Pending JPS61131476A (en) | 1984-11-30 | 1984-11-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61131476A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489557A (en) * | 1987-09-30 | 1989-04-04 | Toshiba Corp | Semiconductor device |
| US6191454B1 (en) | 1996-12-11 | 2001-02-20 | Nec Corporation | Protective resistance element for a semiconductor device |
| DE10110458A1 (en) * | 2001-03-05 | 2002-10-17 | Kord Gharachorloo Wahid | Production of a CMOS inverter comprises preparing a n-doped substrate, masking the surface, forming a p+-doped recess and further processing |
-
1984
- 1984-11-30 JP JP59252905A patent/JPS61131476A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489557A (en) * | 1987-09-30 | 1989-04-04 | Toshiba Corp | Semiconductor device |
| US6191454B1 (en) | 1996-12-11 | 2001-02-20 | Nec Corporation | Protective resistance element for a semiconductor device |
| DE10110458A1 (en) * | 2001-03-05 | 2002-10-17 | Kord Gharachorloo Wahid | Production of a CMOS inverter comprises preparing a n-doped substrate, masking the surface, forming a p+-doped recess and further processing |
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