JPS61139071A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce gate leakage currents without sacrificing conductivity between a source and a drain by constituting the title transistor by a second layer consisting of a semiconductor substance forming a well for potential to a junction section with a first layer and the source and the drain brought into contact with and shaped to the first layer. CONSTITUTION:A Schottky-diode is formed on a boundary section C between a gate 17 and a layer 14. The thickness T6 of a source and a drain extends over a range of 1,000-4,000Angstrom , and the thickness T5 of a protective layer 15 extends over a range of 100-700Angstrom . A distance W1 between the source and the drain extends over a range of 2-10mu, and the width W2 of the gate extends over a range of 0.25-2mu. The band 14 has thickness T4 of 100-400Angstrom , and a band 13 has thickness T3 of 50-200Angstrom . Since the band 14 not doped is made to be contained in a FET along the doped band 13, the threshold voltage of the FET and an electric field on the boundary section C between the gate 17 and the band 14 can be controlled independently. Accordingly, leakage currents in the gate can be reduced to a permissible level while maintaining threshold voltage V at a predetermined value.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to field effect transistors (FETs), and more particularly to modulated doping heterostructure FETs.

[Prior art and its problems]

The following modulation doping heterostructure FET is No DF
It's called ET. Conventional gallium hiso(GaAs) MOD
Regarding F revision, for example, Journal Applied Physics, May 1980, No. 19@, 1225-12
As stated on page 27 and [EEE's EDL, January 1981, pages 14-15, f2a As
The first layer of is grown on a semi-gloss aQILAs substrate. ^l
,,3 G II,,7 A s C and below! AI- to n
A G42 layer (referred to as ^3) is formed on the first layer, and a heterojunction is formed between these 2G layers.

The AIGaAs layer has a lattice structure similar to pseudo^slll, but with a wider bandgap, resulting in a potential Illll wall of about 0.3 V at its heterojunction. The source and drain contacts extend through the 11th layer to the second layer, and the gate is formed on the top surface of the 2nd layer between the source and drain. The AI-h layer is doped with silicon, and the silicon preferentially replaces the GaN atoms in the lattice. Due to the extra valence electrons of Si relative to Ga, Si acts as a donor.

The electrons supplied by the donor Siff child are retained for one hour by the potential barrier at the heterojunction. H4I between the gate and AIGa^3III! The potential suppresses the amount of donor electrons located just below the gel, thereby controlling the source-drain conductance.

In order to reduce the resistance between the source and drain in the ON state of the FET, it is best to dope GaAs NJ as heavily as possible. However, doping to such levels results in an undesirable amount of gate leakage. Therefore, the dopant level is
It is selected in consideration of conductivity between drains and gate leakage. Therefore, acceptable gate leakage current can only be achieved at the expense of increased source-drain conductivity in the on-state.

Conventional MODFETs also have some limitations that are believed to be caused by the trap levels created by the 51 dopant. These No DF ETs have a transconductance as a function of gate voltage, which is gH6 at the incident light level. These 11100F ETs also have a low frequency roll that seems to be related to the trap level.
Gates 11i12! with rolloff gain, thus eliminating the effects of trap levels! ll
It is necessary not to sacrifice the conductivity of the FET to reduce the current.

[Purpose of the invention]

The present invention eliminates the above-mentioned drawbacks, reduces gate leakage Ti current, and improves low frequency roll-off gain without sacrificing drain-source conductivity.

[Summary of the invention]

The No OFET according to the invention has improved properties.

This type of MODEET is hereinafter referred to as pulsed (PIJLSE) doped garden DFEr, and in FIG. Formed on one layer.

And to prevent deterioration of the second calendar 12-14 due to exposure to the surrounding environment! An i-layer may be formed and source and drain contacts 18.19 extending through the second Ai 212-14 to the 1111th layer are formed. 2nd #1
A metal gate 17 is formed on 2-14. The second semiconductor material has a similar lattice structure as the first semiconductor material, but has a larger bandgap between the valence band and the conduction band than the first semiconductor material. This difference in bandgap creates a potential barrier at the heterojunction between the first and second semiconductor layers. This difference also creates a potential well that extends a short distance from the potential barrier into the first semiconductor layer.

[Acts of the Invention J] Figure 143 is a sectional view of a field effect transistor according to the present invention, and Figures 1 and 2 show the manufacturing process thereof. P.I.J.
11 to 15 are CaAs grown on the semi-insulating axis M substrate 10 by molecular beam epitaxy at a temperature of about 620'C and a growth rate of 0.9 microns/hour;
Layers 12-14 have AI 6.3 Gaa, 7 S (hereinafter referred to as Alm Ag), and layer 15 is a protective layer of false A3 that protects layers 12-14 from the surroundings. 1JJ1
Band 13 of 2-14 is doped with silicon. However, since bands 12 and 14 are undoped in the zero molecular beam epitaxial process, the deposited elements are vaporized separately, so controlling which elements are vaporized can control the composition of the deposited layer. It is easy to change. Therefore, layer 11
-15 is formed in a single step. That is, various sublayers are formed by controlling which elements are vaporized at a given time.

Other methods such as organic total vapor phase epitaxial (OMVPE), chemical vapor deposition may be used.

OMVPE is beneficial when tellurium is used as a dopant instead of silicon. This is because tellurium can be supplied as an organometallic mixture. Tin may be used as a dopant, but tin exhibits a step change in concentration level than silicon. Similarly, beryllium may be used as a dopant to make NOOFETs, but the carriers are primarily holes rather than conduction electrons.

AIcaA* is selected for ff12-14. This is because it has a lattice structure similar to layer 11, and Ga
This is because the third layer 11 has a higher conduction band energy than the main layer 11. This results in a boundary mA between layer 11 and layers 12-14.
A potential barrier is generated in the layer 11 from the boundary A.
It creates a potential well in the vicinity of the Fermi level located in a region extending a distance of 0 QAa degrees. The silicon dopant atom is located at the same lattice position δ as the Ga atom.
Since the IS+ atom has 111 m more valence band electrons than the Ga atom, the St atom acts as an electron donor. The donor electrons gather in a potential well near the boundary A. This potential well region serves as the FET channel. In a MODFET using an acceptor dopant such as beryllium, the material for layers 12-14 will have a lower valence band energy than the layers 11. must be selected.

The thickness 1 of layer 11 ranges from 0.25 to 2 microns.

Because the silicon atoms are located at irregularly located discrete points, the electric field generated by the silicon donor atoms is affected by this irregular spatial distribution, with a component that varies randomly in the plane of the Peter junction. The component decreases rapidly as it moves away from the silicon donor atom. Therefore, to prevent diffusion in the channel due to this randomly varying component, the undoped band 11 bounds the periodic component mA
thick enough to make it negligible. layer 1
The thickness T2 of 2 is in the III range of θ to 200A, preferably 100^. The thickness of T, ~T, is discussed below in connection with FIG.

The pedestal shown in Figure 1 is created by etching layers 11-14 using conventional etching techniques. A layer of photoresist is then deposited to form holes over region R. patterned and developed to form a gold/germanium gold layer.The photoresist layer is then removed and the gold layer placed on the photoresist layer is patterned and developed.
The TQ portion is removed. As a result, A u in Fig. 2
/ G e 74 region 110.111 is formed. The wafer was then heated to 430°C for about 10 seconds, and the area 18
．． 19 is alloyed into layers 11-15. During this period of increased salinity, region 110.111 melts and diffuses into layer 11-15 in region R bounded by points &1112.113. As a result, a source contact 18 and a drain contact 19 shown in Figure K3 are formed. These source and drain contacts are connected to the calendar 1 as shown in Figure 3.
1, all that is required is that the source-drain contacts be in electrical contact with the region of R11 where the potential well is formed. The region in which the well is located acts as a channel between the source and drain contacts; this electrical contact means that current can flow between the source contact and the channel, and between the channel and the drain contact.

The wafer is then covered with photoresist, patterned, developed and etched to form notches 16 in which the gate regions will be located.

This notch extends a short distance into the band 14 via the JPJ:115. Band 14 remaining below the notch
The thickness of is indicated by 1. This notch extends across the entire FET, as well as perpendicular to the plane of FIG. A titanium layer and a gold layer are formed. The photoresist is then removed to remove the titanium and gold layer on top of the photoresist. This makes gate 17 a region? , it extends into the contact pad. As shown in Figure 3, gate 1
7 is located between the source and drain contacts to limit the flow of current in the channel between the source and drain contacts.

fA3 diagram (7) MOOFIT Nioite, Gate F is W
In physical contact with Il+, at the interface C between gate 17 and layer 14, a Schottky diode is formed.

In a material such as CaAs that has a high concentration state at an interface such as Ti interface C, the voltage change on the gate spreads downward toward the channel formed close to interface A. A Schottky diode type junction from the gate to K114 is required to generate the electric field change. If this did not occur, changes in the gate voltage would not affect the conductivity between the source contact 18 and the drain contact 19, for a form of material in which there is no high concentration of surface states. There is no gap between Gate 17 and Calendar 14! The thickness of the source and drain in which II may be included is in the range of 1000 to 40001, and the thickness of the protective layer 1
The thickness T of 5 is in the range of 10 (1 to yooλ). The distance between the source and drain #W is 2 to 10 microns jtl
M, and the gate width W□ is 0125 to 2 microns I
It is in the i circle. The band 14 has a thickness of 100-400 λ, the band 3 has a thickness of 50-2° GA, the undoped band 14 is similar to the doped band 13.
, so that the threshold voltage of the FET and the electric field at the boundary WIC between gate 17 and band 14 can be independently controlled. This allows the 1islt current at the gate to be reduced to an acceptable level while maintaining the threshold voltage V at a predetermined value.

The present invention will be explained in more detail below in comparison with a conventional example. In the conventional GaA3 +10 DFET,
Bands 13.14 of layers 12-14 are doped with Si atoms, which act as electron donors. The donor electron is the first
．． 142 is located in the potential well at the heterojunction between the layers. FIG. 4 shows the energy at the bottom of the conduction band as a function of distance along point &i4 of FIG. Heterojunction WBA is located between Mll and band 12, junction B is located between bands 13.14, and junction C is located between band 14 and gate 17. The Fermi level is represented by a dotted line EP, and the heights of potential barriers at points A and C are represented by EA and Ed. Charged Si
The level of the donor atom is indicated by a positively charged circle 43. The donor electrons reside in a potential well 44 extending into layer 1 at a distance less than IOA.

Band 12 is undoped and thin enough to be ignored in FIG. 4; spacer band 12 is thick enough that the irregular electric field component from the donor S1M element decreases to nearly zero at the boundary Mk. , the electric field from these positively charged atoms is uniform in the region of potential well 44. The dopant concentration in a conventional FIG DF ET, which eliminates undesirable diffusion-like layers due to irregular electric field components, is
Due to the Poisson relationship between charge and electric field, band 13
．． 14, the curve &I41 has an almost parabolic shape in the region between points A and 0.

The electric field proportional to the derivative of curve 41 increases linearly across bands 13.14, and the electric field is maximum at interface C between gates 1-17 and layers 12-14. A large electric field in this barrier causes the width of the barrier to decrease,
Increases tunneling phenomenon. A large electric field also increases the impingement layer near this barrier. Both of these effects increase gate leakage current. Further, the strong electric field at the boundary between the gate 17 and the band 14 causes the threshold voltage Vd to strongly depend on the distance jlT between the boundary A and 0. As a result, changes in T due to changes in the process, such as the growth rate of layers 12-14, the rate of etching through protective layer 15 to create gate 17, etc. will strongly affect Va.

According to the invention, there is no Si dopant in band 14. In FIG. 5, the energy at the bottom of the conduction band as a function of the distance subtended to the dotted line 4 in FIG. 3 is shown. The energy at the bottom 51 of the conduction band is parabolic in the region between boundaries A and 8. As a result, the electric field (eg, the slope of curve 51) is lower at junction C between band 14 and gate 17 compared to the conventional MODF ET shown in FIG.

This reduces leakage current and threshold voltage changes due to process changes. In fact, conventional MODp
iNio+truv, Hag, -EA->Na-r%e.

- 10' pulse-doped MODF E according to the present invention
In T, Ee −E A −%/VI T)
(2T-10,000)/ie.

, where EA is the height of the potential barrier at boundary A, Ec is the height of the thermal equilibrium m wall at boundary MC, q is the amount of charge, and Nd is the concentration of S1 dopant atoms. , T3 is the thickness of the band 13, T is the distance between the boundary A and 0, and e is the 1s electric conductivity.

Therefore, dV, T is for the conventional 1lIODF revision,
2(vA-Ec+EA)/T, and the MO of the present invention is
For DF ET, (V, -Ec+EA)/T
becomes.

Therefore, for given vT and T, the conventional MO
The threshold 1a voltage of the OFET is twice as sensitive to thickness T as the inventive MOOFET, in fact since the electric field in band 14 of the inventive +10 DFET is reduced. , for a given vT, T is somewhat larger than for a conventional MOOF ET,
Therefore, in the conventional No DP IT, the sensitivity of the V-factor to changes in T is greater than for the MOOFET according to the present invention.

The No OF ET according to the present invention also has better low-frequency gain characteristics and is less photosensitive than the conventional MODF ET, which means that due to silicon doping, the energy of several trap levels is lowered to the Fermi level E,
This is thought to be due to the fact that it is prevented from intersecting with This can be seen by comparing FIGS. 4 and 5. In FIG. 4, the trap levels exist along the curve 45, which is the trap energy ET below the bottom of the conduction band. Since the zero curve 45 intersects the Fermi level E, these trap levels above the Fermi level Level 46 is ionized. These trap levels 47 below the Fermi level are not charged. When the gate'+H pressure changes, some trap levels are moved across the Fermi level and become charged or neutral depending on the polarity of the gate voltage change. This changes the amount of charge in the potential well 44, thereby changing the transistor's transconductance, g, and causing a low frequency roll-off of the transistor.

In FIG. 5, in the Ill0DFET of the present invention, since there is no silicon doping, the trap level energy curve 56 does not intersect the Fermi level EF, so the influence on g seen in the conventional 11) DFET is real. The above was confirmed by experimenting with the NODFET of the present invention, which does not appear in the NODFET of the present invention. In addition, the transconductance vs. gate voltage characteristics under various light irradiation conditions show that the MODFET of the present invention is better than the conventional MODFET.
It was found that the photosensitivity was lower than that of II) DF according to the invention, since the trap level especially generates photosensitivity.
Photosensitivity in ET is reduced.

〔Effect of the invention〕

As explained above, the MODFET according to the present invention has a small gate leakage current and low photosensitivity without sacrificing conductivity between the source and drain, and has better low frequency characteristics.

Claims (1)

[Claims] a first layer of semiconductor material, a second layer of semiconductor material formed in contact with the first layer and forming a potential well in the first layer in a region proximate the junction; A field effect transistor comprising a source in contact with the layer and a drain in contact with the first layer.