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JPS61128551A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS61128551A
JPS61128551A JP59250255A JP25025584A JPS61128551A JP S61128551 A JPS61128551 A JP S61128551A JP 59250255 A JP59250255 A JP 59250255A JP 25025584 A JP25025584 A JP 25025584A JP S61128551 A JPS61128551 A JP S61128551A
Authority
JP
Japan
Prior art keywords
lead
lead frame
semiconductor device
tie
sections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59250255A
Other languages
Japanese (ja)
Inventor
Masami Shimada
島田　政見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59250255A priority Critical patent/JPS61128551A/en
Publication of JPS61128551A publication Critical patent/JPS61128551A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve reliability remarkably by bending the interface between the surface of a tie-bar lead and a resin sealing layer under the state of resin sealing and lengthening the intrusion path of water. CONSTITUTION:An annular recessed groove 11 is formed to the surface of a bed section 2, and the annular recessed groove 11 is shaped so that the periphery of a semiconductor chip 7 mounted is positioned onto the groove 11. On the other hand, projecting stripes 12... crossing the surfaces in the vicinity of connecting sections with the bed section 2 in the width direction are shaped to tie-bar lead sections 3. Since these projecting stripes 12... and recessed grooves 11 are formed by processing a lead frame by a press, the back side of the recessed groove 11 is shaped in a projecting section and the back sides of the projecting stripes 12 in recessed sections. The intrusion path of water passing on the surfaces of the tie-bar lead sections 3 is lengthened by the projecting stripes 12.... Accordingly, the time when intruding water reaches a conductive paste layer 8 is retarded, thus inhibiting an adverse effect by the intrusion of water.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置、特に樹脂封止型半導体装置の製造
に用いるリードフレームの改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in lead frames used in the manufacture of semiconductor devices, particularly resin-sealed semiconductor devices.

〔発明の技術的背景〕[Technical background of the invention]

半導体装置、特に樹脂封止型半導体装置の製造において
、個々の半導体チップをパッケージングする工程は銅、
ＮＳＣ（Ｎｉ　／Ｓｎ合金）等の導電性材料でできた５
第１図のようなリードフレームを用いて行なわれる。同
図において、１はリードフレームの外枠である。該外枠
１で囲まれた中央には半導体チップのマウント部２が配
設され、該マウント部２はタイバーリード３を介して外
枠１に連結支持されている。また、マウント部２の周囲
にはこれに離間して多数の内部リード４・・・が配設さ
れ、該内部リード３・・・は外部リード５・・・として
延設されている。そして、この内部リード４・・・及び
外部リード５・・・は前記外枠１に連結支持されている
。従来のリードフレームでは、ベッド部２、タイバー３
、内部リード４及び外部リード５の表面は何れも平坦に
形成されてる。In the production of semiconductor devices, especially resin-encapsulated semiconductor devices, the process of packaging individual semiconductor chips uses copper,
5 made of conductive material such as NSC (Ni/Sn alloy)
This is done using a lead frame as shown in FIG. In the figure, 1 is the outer frame of the lead frame. A semiconductor chip mounting portion 2 is disposed in the center surrounded by the outer frame 1, and the mounting portion 2 is connected and supported to the outer frame 1 via tie bar leads 3. Further, a large number of internal leads 4 are arranged around the mount portion 2 at a distance therefrom, and the internal leads 3 are extended as external leads 5 . The inner leads 4 and the outer leads 5 are connected and supported by the outer frame 1. In the conventional lead frame, the bed part 2, tie bar 3
The surfaces of the internal leads 4 and external leads 5 are both formed flat.

上記リードフレームを用いて樹脂封止型半導体装置を製
造する際には、まず半導体チップをリードフレームのマ
ウント部２上にマウント（ダイボンディング）し、半導
体チップ表面のポンディングパッドと対応する内部リー
ド３・・・の先端部との間を金線またはアルミニウム線
等のボンディングワイヤで接続した後、エポキシ樹脂等
のトランスファーモールドにより樹脂封止を行なう。第
２図は樹脂封止後の状態を示す平面図であり、図中６は
樹脂封止層である。続いて、リードフレームの所要箇所
を切断して個々のリードを分離形成しくリードフォーミ
ング）、更にこれらリードを所定方向に折り曲げて第３
図に示す樹脂封止型半導体装置が得られる。When manufacturing a resin-sealed semiconductor device using the above lead frame, first the semiconductor chip is mounted (die bonding) on the mount part 2 of the lead frame, and internal leads corresponding to the bonding pads on the surface of the semiconductor chip are mounted. 3. After connecting with the tip portions using a bonding wire such as a gold wire or an aluminum wire, resin sealing is performed using a transfer mold such as an epoxy resin. FIG. 2 is a plan view showing the state after resin sealing, and 6 in the figure is a resin sealing layer. Next, the lead frame is cut at required points to form individual leads (lead forming), and then these leads are bent in a predetermined direction to form the third lead frame.
The resin-sealed semiconductor device shown in the figure is obtained.

〔背景技術の問題点〕[Problems with background technology]

前記のダイボウディング工程において半導体チップをマ
ウント部２上に接合するための材料としては、材料コス
ト及び作業性の点で優れた導電性ペースト、例えば銀／
エポキシ系接着剤が広く用いられている。この場合、従
来のりドフレームは既述のようにそのベッド部２が平坦
であるため、使用ペースト量が多すぎたりマウント位置
がズしたすした場合には、ダイボンディングの際に導電
性ペーストがチップの周辺にはみ出して盛り上がった状
態になることが多い。第４図（Ａ）（Ｂ）はこのような
状態でダイボンディングされた樹脂封止型半導体装置の
断面図で、図中７は半導体チップ、８は導電性ペースト
、９はボンディングワイヤである。As the material for bonding the semiconductor chip onto the mount portion 2 in the die boarding process, a conductive paste that is excellent in terms of material cost and workability, such as silver/
Epoxy adhesives are widely used. In this case, as mentioned above, the bed part 2 of the conventional glued frame is flat, so if too much paste is used or the mounting position is shifted, the conductive paste will be removed during die bonding. It often protrudes around the chip and becomes raised. 4A and 4B are cross-sectional views of a resin-sealed semiconductor device die-bonded in such a state, in which 7 is a semiconductor chip, 8 is a conductive paste, and 9 is a bonding wire.

上記第３図（Ａ）（Ｂ）の状態で製造された樹脂封止型
半導体装置では、特に次理由から信頼性に劣るという問
題があった。The resin-sealed semiconductor device manufactured in the state shown in FIGS. 3(A) and 3(B) has a problem of poor reliability, particularly for the following reasons.

樹脂封止パッケージはセラミックパッケージに比較して
耐湿性が低く、特に第３図（Ｂ）に示すようにタイバー
イード３の切断端面が樹脂封止層６の側面に露出してい
るため、外部からタイバーリードの表面を通してベッド
部２まで水分が侵入し易い。侵入した水分は導電性ペー
スト８に含まれるハロゲン或いはアルカリ金属（ＣＩ−
。Resin-sealed packages have lower moisture resistance than ceramic packages, and in particular, as shown in FIG. Moisture easily enters the bed portion 2 through the surface of the tie bar lead. The infiltrated moisture is absorbed by the halogen or alkali metal (CI-
.

Ｎａ”、に＋等）を活性化するから、第３図（Ａ）（Ｂ
）の状態ではこうして活性化されたイオンがチップ７の
表面に到達し易く、従ってチップ表面の電極や配線を腐
蝕して信頼性の低下を生じ易いのである。3 (A) (B).
), the ions thus activated tend to reach the surface of the chip 7, and therefore corrode the electrodes and wiring on the chip surface, resulting in a decrease in reliability.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてなされたもので、樹脂封止型
半導体装置の信頼性を向上することができる半導体装置
用リードフレームを提供するものである。The present invention has been made in view of the above circumstances, and provides a lead frame for a semiconductor device that can improve the reliability of a resin-sealed semiconductor device.

〔発明の概要〕[Summary of the invention]

本発明による半導体装置用リードフレームは、半導体チ
ップをマウントすべき金属性のベッド部と、先端をこの
ベッド部近傍に位置させて配設された金属製リードパタ
ーンと、該リードパターンの他端部に連結されてこれを
支持する支持体と、該支持体に一端部が連結されると共
に他端部が前記ベッド部に連結されてこれを支持するタ
イバーリード部と、前記ベッド部において半導体チップ
のマウント予定部周縁の内側近傍から外側近傍に亙る溝
幅で形成された凹溝と、前記ベッド部との連結部近傍に
おいて前記タイバーリード部の表面にその全幅に亙って
形成された凸条とを具備したことを特徴とするものであ
る。A lead frame for a semiconductor device according to the present invention includes a metal bed portion on which a semiconductor chip is to be mounted, a metal lead pattern disposed with a tip located near the bed portion, and the other end portion of the lead pattern. a support body connected to and supporting the support; a tie bar lead portion having one end connected to the support body and the other end connected to the bed portion to support it; a concave groove formed with a groove width ranging from near the inner side to near the outer side of the peripheral edge of the planned mounting portion; and a protrusion formed on the surface of the tie bar lead portion over the entire width near the connecting portion with the bed portion; It is characterized by having the following.

本発明のリードフレームを用いて樹脂封止型半導体装置
を製造すれば、前記凹溝により導電性ペーストの這い上
りを防止して半導体チップのダイボンディングを行なう
ことができる。また、樹脂封止した状態においてタイバ
ーリード表面と樹脂封止層との界面が屈曲し、水の侵入
経路が長くなるため、外部から侵入する水がベッド部に
達する時間を遅延させることができる。この二つの作用
によって、本発明のリードフレームを用いた樹脂封止型
半導体装置では信頼性が顕著に向上する。If a resin-sealed semiconductor device is manufactured using the lead frame of the present invention, die bonding of semiconductor chips can be performed while preventing the conductive paste from creeping up by the grooves. Furthermore, in the resin-sealed state, the interface between the tie bar lead surface and the resin sealing layer is bent, and the water intrusion route becomes longer, so that the time for water intruding from the outside to reach the bed portion can be delayed. These two effects significantly improve the reliability of the resin-sealed semiconductor device using the lead frame of the present invention.

〔発明の実施例〕[Embodiments of the invention]

第１図（Ａ）は本発明の一実施例になるリードフレーム
の要部を示す平面図であり、同図（Ｂ）はそのＢ−Ｂ線
に沿う断面図である。これらの図において、第１図（Ａ
）と同じ部分には同一の参照番号を付しである。即ち、
２はベッド部、３はタイバーリード部である。タイバー
リード部３は第２図（Ａ）の場合と同様、図示しないフ
レーム外枠１に連結されている。この実施例において、
ベッド部２の表面には環状の凹溝１１が形成されている
。この環状凹溝１１は、第１図（Ｂ）に示したようにマ
ウントされる半導体チップ７（図中想像線で示す）の周
縁がその上に位置するように形成されている。他方、前
記タイバーリード部３には、ベッド部２との連結部近傍
表面を幅方向に横断する凸条１２・・・が設けられてい
る。これら凸条１２・・・および前記凹溝１１はリード
フレームをプレス加工して形成されており、このため第
１図（Ｂ）に示したように凹溝１１の裏面側は凸部、凸
条１２・・・の裏面側は凹部になっている。なお、その
他の構成は第２１ｉ１（Ａ）に示した従来のリードフレ
ームと同様であり、ベッド部２の周囲には図示しない内
部リード部の先端が配置され、該内部リード部が延設さ
れた外部リード部はフレーム外枠に連結されている。FIG. 1(A) is a plan view showing a main part of a lead frame according to an embodiment of the present invention, and FIG. 1(B) is a sectional view taken along the line BB. In these figures, Figure 1 (A
) The same parts are given the same reference numbers. That is,
2 is a bed portion, and 3 is a tie bar lead portion. The tie bar lead portion 3 is connected to the frame outer frame 1 (not shown) as in the case of FIG. 2(A). In this example,
An annular groove 11 is formed on the surface of the bed portion 2. As shown in FIG. 1B, this annular groove 11 is formed so that the peripheral edge of the semiconductor chip 7 (indicated by imaginary lines in the figure) to be mounted is positioned above it. On the other hand, the tie bar lead portion 3 is provided with protrusions 12 that cross the surface in the vicinity of the connecting portion with the bed portion 2 in the width direction. These protrusions 12... and the grooves 11 are formed by pressing the lead frame. Therefore, as shown in FIG. The back side of 12... has a concave portion. The other structure is the same as the conventional lead frame shown in No. 21i1(A), and the tip of an internal lead part (not shown) is arranged around the bed part 2, and the internal lead part is extended. The external lead portion is connected to the frame outer frame.

上記実施例のリードフレームを用い、第２図（Ａ）〜（
Ｃ）について説明したのと同様の方法で樹脂封止型半導
体装置を製造すると、そのタイバーリード３，３に沿う
断面構造は第１図（Ｃ）に示すような特徴を具備するよ
うになる。第一に、半導体チップ７をダイボンディング
する際、チップ７の周縁では導電性ペースト８が凹溝１
１内に貯溜されて這い上りが防止されるから、チップ７
の表面とペースト層８との間に充分な距離が保たれる。Using the lead frame of the above example, FIGS.
When a resin-sealed semiconductor device is manufactured by the same method as explained in case C), the cross-sectional structure along the tie bar leads 3, 3 will have the characteristics as shown in FIG. 1(C). First, when die-bonding the semiconductor chip 7, the conductive paste 8 is placed in the groove 1 at the periphery of the chip 7.
Chip 7 is stored in the chip and prevented from climbing up.
A sufficient distance is maintained between the surface of the paste layer 8 and the paste layer 8.

第二には、凸条１２・・・によってタイバーリード部３
表面を通る水の侵入経路が従来の場合よりも延長されて
いる。この結果、侵入した水が導電性ペースト層８に達
するまでの時間が遅延されるから、水の侵入による悪影
響を抑制できることになる。従って、上記実施例のリー
ドフレームを用いることにより、樹脂封止型半導体装置
の信頼性を著しく向上することができる。Secondly, the tie bar lead portion 3 is
The water entry path through the surface is longer than in the conventional case. As a result, the time required for the infiltrated water to reach the conductive paste layer 8 is delayed, so that the adverse effects of water intrusion can be suppressed. Therefore, by using the lead frame of the above embodiment, the reliability of the resin-sealed semiconductor device can be significantly improved.

これらの基本的な効果に加えて、上記の実施例になるリ
ードフレームではベッド部表面に形成された環状の凹溝
１１が半導体チップ７のマウント位置を明示することに
なる。従ってダイボンディングをマニュアル的に行なう
場合に、チップのマウント位置の判明が容易になるとい
う効果が得られる。In addition to these basic effects, in the lead frame according to the above embodiment, the annular groove 11 formed on the surface of the bed clearly indicates the mounting position of the semiconductor chip 7. Therefore, when die bonding is performed manually, it is possible to easily determine the mounting position of the chip.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明による半導体装置用リード
フレームは、これを用いて製造された樹脂封止型半導体
装置の信頼性顕著を図れる等、顕著な効果が得られるも
のである。As described in detail above, the lead frame for a semiconductor device according to the present invention provides remarkable effects such as significantly improving the reliability of a resin-sealed semiconductor device manufactured using the lead frame.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（Ａ）は本発明の一実施例になる半導体装置用リ
ードフレームの要部を示す平面図であり、同図（Ｂ）は
その断面図、第１図（Ｃ）は同図（Ａ）（Ｂ）の実施例
になるリードフレームを用いて製造された樹脂封止型半
導体装置の断面構造を示す説明図、第２図（Ａ）〜（Ｃ
）は従来の半導体装置用リードフレーム及びこれを用い
て樹脂封止型半導体装置を製造する工程を示す説明図、
第３図（Ａ）（Ｂ）は第２図（Ａ）〜（Ｃ）で製造され
た樹脂封止型半導体装置の構造および問題点を示す断面
図である。 １・・・フレーム外枠、２・・・ベッド部、３・・・タ
イバーリード部、４・・・内部リード部、５・・・外部
リード部、６・・・樹脂封止層、７・・・半導体チップ
、８・・・導電性ペースト層、９・・・ボンディングワ
イヤ、１１・・・環状凹溝、１２・・・凸条。 出願人代理人　弁理士　鈴江武彦 （Ｃ） ＾ 第２図 （Ｃ）FIG. 1(A) is a plan view showing the main parts of a lead frame for a semiconductor device according to an embodiment of the present invention, FIG. 1(B) is a sectional view thereof, and FIG. A) An explanatory diagram showing the cross-sectional structure of a resin-sealed semiconductor device manufactured using the lead frame according to the embodiment of (B), FIGS. 2(A) to (C)
) is an explanatory diagram showing a conventional lead frame for a semiconductor device and a process of manufacturing a resin-sealed semiconductor device using the lead frame,
3(A) and 3(B) are cross-sectional views showing the structure and problems of the resin-sealed semiconductor device manufactured in FIGS. 2(A) to 2(C). DESCRIPTION OF SYMBOLS 1... Frame outer frame, 2... Bed part, 3... Tie bar lead part, 4... Internal lead part, 5... External lead part, 6... Resin sealing layer, 7... ... Semiconductor chip, 8 ... Conductive paste layer, 9 ... Bonding wire, 11 ... Annular groove, 12 ... Convex strip. Applicant's agent Patent attorney Takehiko Suzue (C) ^ Figure 2 (C)

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップをマウントすべき金属性のベッド部と、
先端をこのベッド部近傍に位置させて配設された金属製
リードパターンと、該リードパターンの他端部に連結さ
れてこれを支持する支持体と、該支持体に一端部が連結
されると共に他端部が前記ベッド部に連結されてこれを
支持するタイバーリード部と、前記ベッド部において半
導体チップのマウント予定部周縁の内側近傍から外側近
傍に亙る溝幅で形成された凹溝と、前記ベッド部との連
結部近傍において前記タイバーリード部の表面にその全
幅に亙つて形成された凸条とを具備したことを特徴とす
る半導体装置用リードフレーム。a metal bed portion on which a semiconductor chip is to be mounted;
A metal lead pattern disposed with its tip located near the bed portion, a support connected to the other end of the lead pattern to support it, and one end connected to the support. a tie bar lead portion whose other end portion is connected to and supports the bed portion; a groove formed in the bed portion with a groove width ranging from near the inside to near the outside of the periphery of the portion where the semiconductor chip is to be mounted; 1. A lead frame for a semiconductor device, comprising a protruding strip formed on the surface of the tie bar lead portion over its entire width in the vicinity of the connection portion with the bed portion.
JP59250255A 1984-11-27 1984-11-27 Lead frame for semiconductor device Pending JPS61128551A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59250255A JPS61128551A (en) 1984-11-27 1984-11-27 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59250255A JPS61128551A (en) 1984-11-27 1984-11-27 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS61128551A true JPS61128551A (en) 1986-06-16

Family

ID=17205158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59250255A Pending JPS61128551A (en) 1984-11-27 1984-11-27 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS61128551A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
EP0788157A3 (en) * 1996-02-01 2004-02-25 NEC Compound Semiconductor Devices, Ltd. Resin molded package with excellent high frequency characteristics
JP2016122811A (en) * 2014-12-25 2016-07-07 Ｓｈマテリアル株式会社 Lead frame and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788157A3 (en) * 1996-02-01 2004-02-25 NEC Compound Semiconductor Devices, Ltd. Resin molded package with excellent high frequency characteristics
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
JP2016122811A (en) * 2014-12-25 2016-07-07 Ｓｈマテリアル株式会社 Lead frame and manufacturing method thereof

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