JPS61126846A - Break signal processing method - Google Patents

Abstract

PURPOSE:To eliminate useless error processing after detecting the line-break signal by not transferring the received data to the external computer but receiving only until receiving a normal data after detecting the line-break signal. CONSTITUTION:If a data control part 12 receives a break signal 50 for 2 bytes consecutively, the line-break signal is detected as in common USART, and a break detecting signal is transmitted to a received data control part 14 to set a status register 32. And later on, the data control part 12 takes the break signal 50 by unit of 1 byte as data in the internal receiving buffer register 38, and performs the error check, but the data becomes a start stop error data. The data is transmitted to a data buffer 30 of the receiving data control part 14, however, because a status register 32 is in set status, a transmission control part 34 does not transmit the data to an I/O bus 15. Thereafter, the data control part 12, if receives one character of the normal data 53, resets the status register 32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for processing a break signal from an asynchronous terminal device in a data transmission device or similar device that communicates with an asynchronous terminal device.

[Background of the invention]

Regarding conventional data transmission equipment that communicates with asynchronous terminal equipment,
(John E., McNamara) After receiving a break signal from an asynchronous terminal and detecting a line break with a bit length of 2 bytes, as described on pages 1 to 14.

The system is such that the subsequently received break signal is sent to other data processing units via the bus as start-stop error or parity error data. Therefore, after a break is detected, error processing must be performed on the data processing section side, which is one of the causes of a decrease in data transmission efficiency.

[Purpose of the invention]

An object of the present invention is to prevent data transmission caused by a break signal (start-stop error or parity error data) after detecting a line break as described above in a data transmission device or similar device that communicates with an asynchronous terminal device. An object of the present invention is to provide a break signal processing method for preventing a decrease in efficiency.

[Summary of the invention]

According to the present invention, to achieve the above object.

After a data transmission device or similar device that communicates with an asynchronous terminal device detects a break signal from an asynchronous terminal device, it discards the received data and transmits it to an external device (for example, a computer) until the data is received normally. is configured not to be forwarded.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to one drawing.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. Reference numeral 10 denotes a data transmission device, which includes a data control section 12 and a received data control section 14.

Reference numeral 15 denotes an input/output bus between the data transmission device 10 and other data processing units (not shown).

The data control unit 12 has an interrupt line 16 . address line 18
It is connected to the input/output bus 15 through a transmission data line 20, and connected to the reception data control section 14 through an internal signal line 22. The reception data control section 14 is connected to the input/output bus 15 via the reception data line 24. The data transmission device 10 communicates data with one or more asynchronous terminal devices (not shown) via an asynchronous serial transmission line (not shown). and receives and transmits data to and from that line via the transmission line 28. Also, the data control section 12.

The received data from the asynchronous terminal device is transmitted to the internal signal line 22,
Reception data control unit 14. The data is transferred to another data processing unit via the receive data line 24 and the input/output bus 15, and the transmitted data is transferred from there to the input/output bus 15 and the transmit data line 20.
transferred via.

The reception data control circuit 14 is set by a data buffer 30 to which reception data is set from the data control unit 12, a break detection signal sent from the data control unit 12, and is then given a normal reception data signal from the data control unit 12. Status register 32.
It consists of a transfer control circuit 34 that sends the data in the data register 30 to the input/output bus 15 via the reception data line 24 only when the status register 32 is in the reset state.

The data control unit 12 is a general-purpose synchronous type asynchronous type receiving transmitter (Universal 5 synchronous type receiving transmitter).
Asynchronous Receiver
Transmit, ter: USA RT). Inside this data control unit 12,
Similar to the general USART, a 16-bit receive buffer register 38 as shown in FIG. 2 is provided. Bits 2° to 27 are the receive character buffer where data received from the line via the receive line 26 is set, bit 212 is the PE bit which is set to 1" when the received data has a parity error, and bit 213 is the receive character buffer where the data received from the line via the receive line 26 is set. The FE (framing error) bit is set to ``1'' when a start-stop error occurs, and the bit 214 is the OE (overrun error) bit where re 1 tt is set when a reception overrun occurs.Bit 215 is the PE bit.
E where the logical sum of PE bit and OE bit is set
This is an RR (error flag) bit.

FIG. 3 shows the format of asynchronous character data. As is well known, the state when the line is idle (energized) is "'1" state (marked state), and the current cutoff state is "0".
This is called the "0" state (state).

Before transmitting character data 40 (5 to 8 bits in length, but in this embodiment described as 8 bits or 1 byte), a line is spaced for one bit period. This bit 41 is called a start bit. Following the last bit (parity bit) of character data 40, one line is marked for one bit period or more. This bit 42 is called a stop bit. In this way, data transmission is performed while character data is separated by start bits and stop bits, but a special control signal called a break signal can also be sent over the line.

This break signal is a space state signal consisting of consecutive start bits.

Next, break signal processing in this embodiment will be explained with reference to FIG. When the data control unit 12 receives two consecutive bytes of the break signal 50,
Similarly to RT, a line break is detected, a break detection signal is sent to the received data control section 14, and the status register 32 is set. After that, the data control unit 12 takes in the break signal 50 as data in 1-byte units into the internal reception buffer register 38 and performs an error check, as in a general USART, but the data becomes start-stop error data. . This data is sent to the data buffer 30 of the reception data control section 14, but since the status register 32 is in the set state, the transfer control circuit 34
does not send the data to the input/output bus 15. In other words,
Such start-stop error data is sent to the data transmission device i10.
The data is discarded within the unit and is not transferred to other data processing units. Furthermore, in that case, the data control unit 12 does not report the start-stop error to other data processing units.

Thereafter, when the data control unit 12 receives one character of normal data 53, it transfers the data to the data buffer 30 and at the same time sends out a normal data reception signal to reset the status register 32. When the status register 32 is reset, the transfer control circuit 34 begins to send the contents of the data register 30 to the input/output bus 15.

In this way, the data transmission device 10 accepts and discards the break signal, that is, start-stop error data, which is subsequently received after the first line break is detected, and does not transfer it to other data processing units. There is no need to perform this on the processing unit side, and as a result, data communication can be performed more efficiently than before.

Since the operations other than the break communication processing described above are the same as those of the conventional system, the explanation thereof will be omitted.

FIG. 5 is a schematic configuration diagram of a configuration network according to another embodiment of the present invention. This configuration network 60 includes one or more start-stop synchronization terminal devices 62.

It houses a host computer 64 as a packet terminal device, and exchanges data between the asynchronous terminal device 162 and the host computer 64 through packet exchange. 6
Reference numeral 5 denotes a loop transmission line consisting of an optical fiber cable, etc., which connects an exchange 66 that supports CCITT Recommendations X and 28 as a node and an exchange 68 that supports CCITT Recommendations X and 29 in a loop. . The break signal processing method of the present invention is applied to the switching center 66 (however, the break signal processing method of the present invention can also be applied to the switching center 68). Although only two exchanges are shown, this is just an example.

A schematic block diagram of the exchange 66 is shown in FIG.

In this figure, 112 is a data control unit that transmits and receives data to and from the asynchronous terminal device 162, and 114 is a received data control unit. 115 is a packet processing control unit 13
3 input/output bus, and the data control unit 112 has an interrupt line 116, an address line 118, and a transmission data line 12.
0 to the input/output bus 115, and to the reception data control unit 114 via an internal signal line 122. Reception data control section 114 is connected to input/output bus 115 via reception data line 124. The data control unit 112 communicates data with one or more asynchronous terminal devices (not shown) via an asynchronous serial transmission line (not shown), and 126 and 128 communicate with the line. These are a receiving line and a sending line for receiving and transmitting data. The data control unit 112 also transmits the received data from the step synchronization terminal device 62 to the internal signal line 122. Reception data control unit 114. The data is transferred to the packet processing control section 133 via the reception data line 124 and the input/output bus 115, and the transmission data is transferred from the packet processing control section 133 via the input/output bus 115 and the transmission data line 120.

The received data control circuit 114 includes a data buffer 130 .into which received data is set from the data control unit 112 . A status register 132 that is set by a break detection signal sent from the data control unit 112 and then reset when a normal data reception signal is given from the data control unit 112. Only when the status register 132 is in the reset state, the data register 130 is The transfer control circuit 134 sends the data to the input/output bus 115 via the reception data line 124.

Note that the data control unit 112 is a general-purpose synchronous asynchronous receiver/transmitter (Universal Synchronous Transmitter).
ronous Asynchronous Rec
eiver Transmit, er: U
5ART).

134 is a loop transmission/reception control section which is an interface section with the loop transmission line 65. This loop transmission/reception control unit 134 receives packetized data from the loop transmission path 65, and if the packet is addressed to its own station, the input/output bus 1
15 to the packet processing control unit 132, and packets that are not addressed to the local station are transmitted as they are to the loop transmission line 65, and from the packet processing control unit 132 to the input/output bus 115.
The packetized data sent via the loop transmission line 65 is transmitted to the loop transmission line 65. The packet processing control section 132 creates transmission data to the corresponding asynchronous terminal device 62 from the packetized data received from the loop transmission path 65 and sends it to the data control section 112, or sends it to the data control section 112. It functions to packetize the received data and send it to the loop transmission/reception control section 134.

Next, the operation when a break signal is sent from the asynchronous terminal device 62 will be explained. The communication status in this case is
Shown at the bottom of the figure.

A break signal is sent (■), and when the data control unit 112 of the exchange 66 receives 2 bytes of the break signal,
Send a break detection signal to the status register 132
While setting , it interrupts the packet processing control unit 132 and reports one line break. As a result, the packet processing control unit 132 generates an interrupt (IT) packet.

It is sent to the loop transmission path 65 via the loop transmission/reception control unit 134 (■). This interrupt packet is sent to host computer 64 via switching center 68.

The host that received this line break interrupt packet
Computer 64 sends an interrupt confirmation (IF) packet to switching center 66 via switching center 68 . In the switching center 66, while the status register 132 is set, that is, until 1 byte (1 character) of normal data is received from the asynchronous terminal device 62 after a line break, the received data is stored in the received data control unit 114.
, and does not transfer it to the packet processing control unit 132. Therefore, the break signal that is subsequently received after the break detection, that is, the start-stop error data, is not sent to the host computer 64. Thus, the host computer 64 needs to send the start-stop error data after the line break detection. There is no longer a need to perform error handling. therefore.

This enables more efficient data communication than before.

Note that the operations other than the break signal processing of 9 and above are the same as those of the prior art, so a description thereof will be omitted.

〔Effect of the invention〕

As explained above, according to the break processing method of the present invention, in a data transmission device or similar device that communicates with an asynchronous terminal device, after detecting a line break, the received data is discarded until normal data is received. Since the data is not transferred to a computer, etc., unnecessary error processing after a break is detected can be eliminated, and data communication can be performed more efficiently than before.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a data transmission device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of a receiving buffer register,
FIG. 3 is a diagram showing the format of asynchronous character data, FIG. 4 is an explanatory diagram of break signals and their processing, and FIG. 5 is a schematic configuration diagram of a local network according to another embodiment of the present invention.
FIG. 6 is a schematic block diagram of the 28-support switching center shown in FIG. 10... Data transmission device, 12... Data control unit. 14... Reception data control unit, 15... Computer input/output bus, 24... Reception data line, 30
...Data buffer, 32...Status register, 34...Transfer control circuit, 50...Break signal, 53...Normal data, 60...Internal network, 62...Start-stop synchronization terminal device , 65・
...Loop transmission line, 66...X, 28 support switching center, 68...X, 29 support switching center, 64...
・Host computer (packet terminal device),
112... Data control unit, 114... Reception data control unit, 130... Data buffer, 132...
...Status register [34... Transfer control circuit, 115... Input/output bus, 133... Packet processing control section, 134... Loop transmission/reception control section.

Claims (1)

[Claims] (1) In a data transmission device or similar device that communicates with an asynchronous terminal device, after detecting a break signal from the asynchronous terminal device, the break signal from the asynchronous terminal device is maintained until normal data is received from the asynchronous terminal device. A break signal processing method characterized by internally discarding data received from a synchronous terminal device and not transmitting it to the outside.