JPS61102069A - field effect transistor - Google Patents

Abstract

PURPOSE:To prevent the creeping of currents to a substrate by forming a non- doped semiconductor layer having small electronic affinity up to the position shallower than the depth of a low resistance region under source-drain electrodes. CONSTITUTION:A non-doped AlGaAs layer 12 having small electronic affinity is grown on a semi-insulating substrate 11 in an epitaxial manner, and a non- doped GaAs layer 13 as a channel layer is formed onto the layer 12. An AlGaAs layer 14 containing an N type impurity is shaped. Metals as source-drain electrodes are applied and thermally treated, and ally layers 17 having low resistance are prepared under these electrodes 15, 16. The layers 17 are made to reach the layer 12 so as to be excellently brought into ohmic-contact with an electron group in the channel layer. According to such constitution, superior current saturation characteristics and current interrupting characteristics are obtained even through a channel is shortened.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention utilizes a heterojunction interface C: a heterojunction in which a two-dimensional electron accumulation layer induced by a difference in electron affinity serves as a conductive channel. Regarding field effect transistors, especially current saturation characteristics and current cutoff characteristics (pinch-off characteristics)
Regarding field effect transistors with excellent performance.

[Technical background of the invention and its problems]

A semiconductor layer with low electron affinity containing n-type impurities and 1
When a heterojunction is formed between substantially impurity-free semiconductor layers with high electron affinity, a two-dimensional electron accumulation layer is formed at the interface due to the difference in electron affinity between the two. A field effect transistor that uses this electron storage layer as a conductive channel is a high electron mobility transistor (HEMT).
), or selectively doped field effect transistor (MD
FET), etc., and has superior high frequency characteristics compared to ordinary metal-semiconductor field effect transistors (MB8FET).

Normally, high electron mobility transistors are as shown in Figure 3.
A non-doped semiconductor layer (e.g. GaAs) with high electron affinity is epitaxially grown relatively thick (~1 #m) on a semi-insulating substrate (e.g. GaAs), and
A semiconductor layer with low electron affinity containing n-type impurities (
For example, it has a structure formed by epitaxially growing AlGaAs. Ohmic contact to the channel formed at the heterojunction interface is made through a low resistance metal alloy formed from the semiconductor surface.

It has been experimentally verified that transistors with this type of structure exhibit good high-frequency characteristics, but when a device with a short channel length is fabricated, the saturation characteristics in the current saturation region are not necessarily good. In many cases, the current blocking characteristics when applying a reverse voltage to the gate were also insufficient. It is qualitatively understood that the decrease in saturation and cutoff characteristics is due to the phenomenon that current flows around the semiconductor layer below the heterojunction interface, and in order to improve the characteristics, it is necessary to Although attempts have been made to introduce a layer with low electron affinity between the channel layers and form a potential barrier there, there is no quantitative understanding of current wraparound, It was not clear whether or not it would be effective to form the following:

[Purpose of the invention]

In view of the above points, it is an object of the present invention to provide a heterojunction field effect transistor that has good current saturation characteristics and current cutoff characteristics even when the channel is shortened.

[Summary of the invention]

In the field effect transistor of the present invention, in order to prevent current from flowing into the substrate side from the above-mentioned heterojunction interface, a semiconductor layer that has low electron affinity and does not substantially contain impurities is in contact with the source and drain electrodes. It is characterized by being formed at a depth shallower than the depth of the low resistance region formed from the semiconductor surface.

The present invention is based on the findings described below. We developed a two-dimensional model that can accurately simulate the distribution of potential, carriers, current, etc. inside a semiconductor element, and used this to analyze a high electron mobility transistor with a conventional structure. It is clear that the depth of the current flow to the side is closely related to the depth of the low resistance region formed under the source and drain electrodes. FIG. 4 is an example of the calculated current distribution inside the element.

This device has a gate length of 1 μm, and a low-resistance alloy metal is formed under the source and drain electrodes to a depth of 0.15 m from the channel. As is clear from FIG. 4, the current generated at the end of the gate electrode on the drain side reaches the depth of this alloy layer. This is because the change in the shape of the conduction band near the gate edge caused by the voltage applied to the drain electrode depends on the shape of the low resistance region. Therefore, in order to suppress the flow of current toward the substrate side, it is effective to form a low-resistance region under the source and drain electrodes to the depth of the heterojunction interface, but the resistance between the channel region and the This method is undesirable in order to press it down to a small size, and it becomes difficult to make confectionery because it is necessary to precisely control the depth of the low resistance region.

In the structure of the present invention, a semiconductor layer with low electron affinity is arranged at a position shallower than the depth reached by the low resistance regions under the source/drain electrodes, and a potential barrier is formed to suppress current circulation. This makes it possible to avoid various problems in terms of characteristics or device fabrication.

〔Effect of the invention〕

As described above, the device with the structure of the present invention has good current saturation characteristics even when the channel is shortened, without any difficulties in device manufacturing. This has the effect of providing current interrupting characteristics.

[Embodiments of the invention]

FIG. 1 shows the device structure of the present invention using GaAs and AlGaAs.
This figure shows an example of the case of fabrication using. This element is manufactured as follows. First, AIGaAsm having a low electron affinity, indicated by 12 in the figure, is epitaxially grown in a non-doped manner on the semi-insulating substrate 11 directly or via a ζ non-doped GaAs layer serving as a buffer layer. On this layer, a non-doped GaAs layer 13, which will become a channel layer, is grown to a thickness within a range where current circulation does not seriously affect device characteristics.

Next, an n-type impurity (SL
etc.) is grown. To perform this series of growth, MBE method or MOCVD is used.
The law is appropriate. After metals such as AuGa/Au, which will become source and drain electrodes, are deposited and formed on the surface of the wafer thus formed, a low-resistance alloy layer 17 is formed under these electrodes by applying heat treatment. This alloy layer seems to have good ohmic contact with the electronic system of the channel layer (12 in the figure).
It is formed so as to reach the AI GaA m layer shown in . Finally, a Schottky gate electrode 18 is formed on the wafer surface to complete the process. When manufacturing this device, an n"GaAs layer was inserted under the source and drain electrodes to improve ohmic characteristics, and a recess structure was inserted under the C electrode to reduce parasitic resistance between the source and gate. It is easy to combine known characteristics improvement techniques, such as by introducing.

FIG. 2 shows another embodiment of the invention. The difference between this embodiment and the one shown in FIG. 1 is that the AlGa8b layer with high electron affinity inserted under the channel layer
1 composition ratio gradually decreases toward the channel. By introducing such a structure, AJGaAs
Even if the A1 composition ratio of r#lJ is increased, the channel GaA
It is possible to prevent roughness from occurring at the interface with the s-layer, and it is possible to more effectively confine current in the channel region without impairing device characteristics.

In the above embodiments, GaAs is used as the semiconductor combination.
Although InP and AlGaAs have been used, the device of the present invention can be made of combinations of other materials, such as InP and InGaAs, GaAs
It goes without saying that the structure can be similarly constructed using other materials such as AlGa8b and AlGa8b.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a field effect transistor according to one embodiment of the present invention, FIG. 2 is a structural diagram of a field effect transistor according to another embodiment of the present invention, and FIG. 3 is a high electron mobility transistor with a conventional structure. FIG. 4 is a diagram showing a current distribution inside a high electron mobility transistor with a conventional structure obtained using a two-dimensional numerical analysis model. 11... Semi-insulating semiconductor substrate (GaAs). 12... Non-doped semiconductor layer with low electron affinity (A
IGaAs). 12'...A non-doped semiconductor layer whose composition gradually changes. 13... Non-doped semiconductor layer with high electron affinity (G
aAs). 14... Semiconductor layer (A) GaAs) containing n-type impurities and having low electron affinity. 15... Source electrode, 16... Drain electrode. 17...Low resistance alloy layer, 18...Gate electrode. Agent: Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Rei

Claims (1)

[Claims] A first semiconductor layer that does not substantially contain impurities and has a low electron affinity, a second semiconductor layer that does not substantially contain impurities and has a high electron affinity, and is formed in sequence on a semi-insulating substrate. A gate that has a third semiconductor layer containing impurities and has a low electron affinity, has an electron accumulation layer formed at an interface between the second and third semiconductor layers as a channel, and controls the number of electrons in this channel. A field effect transistor characterized in that an electrode and an input/output electrode in ohmic contact with the channel via a low resistance region are formed on a semiconductor surface, and the low resistance region reaches the first semiconductor layer.